KR19990031662A - MOS field effect transistor manufacturing method - Google Patents

Abstract

The present invention relates to a method for manufacturing a MOS field effect transistor, a conventional method for manufacturing a MOS field effect transistor is formed by forming a salicide layer directly on top of the drain, the contact resistance of the drain and the salicide layer is lowered, When a signal is applied to the drain, thermal charges occur, which deteriorates the characteristics of the MOS field effect transistor, thereby reducing reliability. In view of the above problems, the present invention provides a method of manufacturing a gate 2, a source and a drain 4, and forming a salicide layer 5 on top of the gate 2, the source and the drain 4. In the method of manufacturing a Mohs field effect transistor comprising a, further comprising an ion implantation step of injecting the implanted or en-type impurity ions into the drain before forming the salicide layer (5) to the junction resistance between the salicide layer and the drain; By increasing, by preventing the generation of thermal charge when a high voltage is applied, there is an effect of improving the reliability of the MOS field effect transistor.

Description

MOS field effect transistor manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS field effect transistor, and more particularly, to a MOS field effect by implanting impurity ions into the drain of a MOS field effect transistor to increase the contact resistance between the drain and silicide, thereby reducing the maximum electric field, thereby making it suitable for preventing generation of thermal charges. The present invention relates to an effect transistor manufacturing method.

In general, a MOS field effect transistor forms a silicide layer on top of a gate, a source, and a drain for the purpose of lowering a contact resistance between a drain, a source, and a metal. In this case, the silicide formed is particularly referred to as salicide formed by a self-aligned (SELF-ALINE) method using no mask. The formation of the silicide reduces the contact resistance between the metal and the semiconductor device, but the heat charge is generated to deteriorate the characteristics of the MOS field effect transistor. When described in detail with reference to as follows.

1A and 1B are cross-sectional views of a manufacturing process of a conventional MOS field effect transistor. As shown in FIG. Forming step (FIG. 1A); Forming a salicide layer 5 on the gate 2 and the source and drain 4 (FIG. 1B).

Hereinafter, a method of manufacturing a conventional MOS field effect transistor configured as described above will be described in more detail.

First, as shown in FIG. 1A, a gate oxide film and polysilicon are deposited on the substrate 1, and then the gate 2 is formed by a photolithography process. Subsequently, low concentration impurity ions are implanted into lower portions of both side substrates 1 of the gate 2 to form a low concentration source and drain, and a nitride film or the like is deposited on the side of the gate 2 to dry the sidewalls 3. ). After the side wall 3 is formed as described above, high concentration impurities are injected into the lower portion of the side substrate 1 of the side wall 3 by using the side wall 3 and the gate 2 as an ion implantation mask to form a high concentration source and drain. To form an LDD structure source and a drain 4.

Then, after forming the basic structure of the MOS field effect transistor as described above, as shown in Fig. 1b, titanium is deposited on the gate 2 and the LDD structure source and drain 4, and then diffused to form a gate. The salicide layer 5 is formed on (2) and the source and drain 4.

In the subsequent process, a metal electrode, a protective layer, and the like are formed to manufacture a MOS field effect transistor.

However, as described above, in the conventional method of manufacturing a MOS field effect transistor, a salicide layer is directly formed on the upper portion of the drain, so that the contact resistance between the drain and the salicide layer is lowered, whereby a high potential signal is applied to the drain. Thermal charges are liable to occur, which causes deterioration of the characteristics of the MOS field effect transistor, thereby reducing reliability.

In view of the above problems, the present invention provides a MOS field effect transistor having a low contact resistance on the source and gate side to improve operating characteristics, and a high contact resistance on the drain side to prevent thermal charges, thereby improving reliability of operation. Has its purpose.

1A and 1B are cross-sectional views of a manufacturing process of a conventional MOS field effect transistor.

Figure 2a to 2c is a cross-sectional view of the manufacturing process of the MOS field effect transistor of the present invention.

*** Description of the symbols for the main parts of the drawings ***

1: Substrate 2: Gate

3: side wall 4: source and drain

5: salicide layer

The above object is achieved by reducing the maximum electric field by increasing the contact resistance between the drain and the metal by further including the step of injecting impurity ions into the drain before forming the salicide layer. When described in detail with reference to the drawings as follows.

2A to 2C are cross-sectional views of a manufacturing process of the present embodiment of the Morse field effect transistor. As shown therein, a gate 2 is formed on the substrate 1, and both side substrates 1 of the gate 2 are formed. Forming a source and a drain 4 of the LDD structure in the film (FIG. 2A); Forming a pattern by applying and exposing a photoresist (P / R), and then implanting impurity ions having different properties from those of the drain (FIG. 2B); Forming a salicide layer 5 on the gate 2 and on the source and drain 4 (FIG. 2C).

Hereinafter, with reference to the accompanying drawings of the present invention configured as described above in detail.

First, as shown in FIG. 2A, a gate oxide film and polysilicon are deposited on the substrate 1, and then the gate 2 is formed by a photolithography process. Subsequently, low concentration impurity ions are implanted into lower portions of both side substrates 1 of the gate 2 to form a low concentration source and drain, and a nitride film or the like is deposited on the side of the gate 2 to dry the sidewalls 3. ). After the side wall 3 is formed as described above, high concentration impurities are injected into the lower portion of the side substrate 1 of the side wall 3 by using the side wall 3 and the gate 2 as an ion implantation mask to form a high concentration source and drain. To form an LDD structure source and a drain 4.

Next, as shown in FIG. 2B, a photoresist (P / R) is applied and a pattern is formed on the gate 2, the sidewall 3, and the LDD structure source and drain 4 to form the drain. Expose Impurity ions are then implanted into the drain using the photoresist P / R as an ion implantation mask.

At this time, the implanted impurity uses impurity ions having a valence different from that of the source and drain 4 of the LDD structure. That is, in the case of the NMOS field effect transistor, the source and the drain 4 are injected with a pentavalent element, and a trivalent element is injected into the drain of the NMOS field effect transistor to increase the contact resistance. In contrast, in the case of the PMOS field effect transistor, a pentavalent element is injected.

Next, as shown in FIG. 2C, the photoresist P / R is removed, a titanium layer is deposited on the gate 2, the source and the drain, and the titanium ion of the titanium layer is subjected to heat treatment. The salicide layer 5 is formed by diffusion into the gate 2 and the source and drain 5 of the LDD structure.

As described above, in the method of manufacturing the MOS field effect transistor of the present invention, the impurity ions are implanted into the drain to increase the junction resistance between the salicide layer and the drain, thereby preventing the occurrence of thermal charge when a high voltage is applied. There is an effect of improving the reliability of.

Claims (2)

A method of manufacturing a MOS field effect transistor, comprising: forming a gate, a source, and a drain; and forming a salicide layer on top of the gate, the source, and the drain. Method of manufacturing a MOS field effect transistor, characterized in that it further comprises an ion implantation step of implanting impurity ions. The method of claim 1, wherein the ion implantation step comprises implanting impurity impurities in the case of the NMOS field effect transistor and injecting the N-type impurity in the case of the PMOS field effect transistor.