KR19990031196U - Printed Circuit Board of the Memory Module - Google Patents

Abstract

The present invention is designed to speed up the system in which the memory is mounted, and to prevent the degradation of the speed caused by the interface between the memory module and the system, and the loading and current driving capability, which are a problem in the operation of the memory module. A printed circuit board of a memory module, in which a plurality of mounting portions are formed and connected to signals input from a system, respectively, in order to mount a plurality of memory elements, wherein the signals input from the system are converted into a plurality of identical signals. It further includes a register for distributing and connecting the memory devices to the memory devices, thereby preventing collision between data due to memory loading problem and lack of current driving capability.

Description

Printed Circuit Board of the Memory Module

The present invention relates to a printed circuit board of a memory module, and more particularly, due to a high speed of a system in which a memory is mounted, which is caused by an interface between a memory module and a system, and a loading and current driving capability problem. The present invention relates to a printed circuit board of a memory module capable of preventing a decrease in speed.

Memory is a general term used to temporarily or permanently store data or instructions used in computers, communication systems, image processing systems, and the like, and is typically a semiconductor, tape, disk, or optical method. Occupies. There are many kinds of such semiconductor memories, such as DRAM, SRAM, Flash Memory, and ROM, which are classified according to electrical characteristics of a data storage method.

The DRAM (Dynamic Random Access Memory) requires a periodic refresh operation to restore the storage potential to its original state periodically because the storage potential changes with time, and the read operation because the amount of charge stored in the capacitor serves as a data determination criteria. Since the voltage difference is induced by the difference in the amount of charge, the voltage difference is sensed and amplified, and the data is output. Therefore, the destroyed stored data must be recovered and stored in the cell.

When the above memory is actually used in a system, it is produced by making it into a module. A module is a set of devices having a single function, and various packaging devices such as semiconductor devices are mounted on a printed circuit board (PCB). A plurality of connecting pins are connected to the panel and the like by tabs.

Synchronous Dynamic Random Access Memory (SDRAM) is a DRAM that has a three-stage pipeline that divides open address acquisition, data readout, and output port output into a three-stage pipeline.

In general DRAM, only one data can be processed after receiving the open dress until the output is terminated, but since SDRAM is divided into three stage pipelines and processed in synchronization with each clock, the first data output takes three clocks. After that, the output can be performed every one clock, so that high-speed access is possible.

FIG. 1 is a schematic view of a printed circuit board of a general memory module, and illustrates a printed circuit board of a 168-pin 100 MHz registered SDRAM DIMM.

As shown in FIG. 1, on the printed circuit board 10, 18 mounting elements 25 for mounting 18 on the front and 18 on the back are formed, and various signals and data for driving the memory device. Is made up of a tab 15 for connection with a system (not shown).

The memory module configured as described above has various signals transmitted from the system, that is, five , , , Fourteen ADDRESS and eight DQ signals come from the system and are coupled to 36 memory elements 20, respectively.

Since one signal input from the system is connected to 36 memory devices, when the speed of the interface between the system and the memory device 20 is increased to 100 MHz or more, the signal is correctly synchronized with the control signal due to memory loading problems or high-speed operation. Five at the same time , , , Since 14 ADDRESS and 8 DQ signals are not enabled or disabled, each memory device operates differently, resulting in a collision between data and a high speed operation due to a lack of current driving capability.

The present invention was created to solve the above problems, and an object of the present invention is to add a device capable of distributing a signal input from the system into a plurality of identical signals so that the memory device can be controlled with a stable signal. To provide a printed circuit board of a memory module.

1 is a schematic view of a printed circuit board of a 168-pin 100 MHz registered SDRAM DIMM as a printed circuit board of a general memory module.

2 is a schematic view of a printed circuit board of a 168-pin 100 MHz registered SDRAM DIMM as a printed circuit board of the memory module according to the present invention.

3 is a partially enlarged view of a portion added to the present invention in FIG.

-Explanation of symbols for the main parts of the drawings-

10 substrate 20 memory element

30: register 40: PLL element

The present invention for achieving the above object is in the printed circuit board of the memory module formed with a plurality of mounting portions are formed so that a plurality of memory elements can be mounted and connected to each of the signals input from the system, the signal input from the system And a PLL element for distributing a plurality of identical signals to connect to each of the memory elements, and a PLL element for synchronizing the register with a system clock.

Referring to the operation of the present invention made as described above are as follows.

The signal input from the system is first inputted to a register to output a plurality of identical signals. The signals are connected to a plurality of memory elements mounted in the memory module and synchronized with the clock input from the system to stably input the input signals. Supply to the memory device.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as the conventional configuration using the same reference numerals and names.

2 is a schematic view of a printed circuit board of a 168-pin 100 MHz registered SDRAM DIMM as an embodiment according to the present invention.

As shown in FIG. 2, thirty six mounting portions 25 into which thirty six memory elements 20 can be mounted are formed, and tabs 15 for connecting to a system (not shown) are formed. And all the signals input from the system through the tab 15 are connected to two registers 30 and the output of the register 30 is connected to each of the 36 mounting portions 25. In addition, a PLL element 40 for distributing the clock signal received from the system to the register 30 is provided so that four registers 30 may be synchronized with the clock signal to output the input signal.

Four registers (30) are divided into four blocks so that the 36 mounting units (25) can be controlled simultaneously by nine blocks using the 1 TO 4 register (30) that outputs four identical signals when one signal is input. . That is, the register 30 in this embodiment uses four registers 30 that receive nine signals and output 36 signals.

In order to explain in detail the operation of the present embodiment made as described above with reference to Figure 3 is enlarged 'A' portion of Figure 2 as follows.

3 is a diagram illustrating a connection state of a register added by the present invention, when four address (A ₁ ) signals are input, four address (A ₁ ) signals are output as outputs. The four output first address A ₁ signals are connected to the first address 1A ₁ signal to the first address pin BA ₁ of the memory device 20 of the first block BL1. The first address pin BA ₁ of the memory device 20 of the second block BL2 is connected to the second first address 2A ₁ signal. Similarly, the first address pin BA ₁ of the memory device 20 of the fourth block BL4 is connected to the fourth address 4A ₁ signal, respectively.

In this way, five inputs from the system , , , , 14 ADDRESS and 8 DQ signals are connected to the inputs of the 4 registers 30 and the 4 signals outputted are the first block BL1, the second block BL2, the third block BL3, and the fourth signal. Each block is divided into blocks BL4.

In order to synchronize the four registers 30 with the clock signal CLK inputted from the system, the four registers 30 are synchronized with the input clock using the PLL element 40.

As described above, the present invention distributes a number of signals from a system and connects them to a plurality of memory elements mounted in a memory module divided into several blocks, thereby increasing the number of mounting of memory elements in the memory module. In addition, due to the high speed, it is possible to prevent data collisions caused by the memory loading problem for controlling multiple memory devices with one signal and the lack of the current driving ability to prevent data collision caused by high speed operation. The advantage is that you have the ability.

Claims (2)

In the printed circuit board of the memory module formed with a plurality of mounting portions are formed so that a plurality of memory elements can be mounted and connected to each of the signals input from the system, A register for distributing a signal input from the system into a plurality of identical signals and connecting the signals to the memory devices, respectively; PLL device for synchronizing the register with the system clock Printed circuit board of the memory module, characterized in that further comprises. The method of claim 1, wherein the register is The printed circuit board of the memory module, characterized in that the 1 TO 4 register to receive one signal and output four identical signals.