KR19990028451A - Apparatus and method for improved deposition of high aspect ratio conformal liner thin films and plugs - Google Patents

Abstract

Sputter systems and methods include a vacuum system 36, a target 44, a collimator 46, and a substrate 38. The target 44 is biased and sputtered to deposit a layer of material on the substrate 38 via the collimator 46. The substrate 38 may be biased to be etched simultaneously with deposition. The etching redistributes the deposited material in the contacts to reduce excess deposition in the contact openings and produces a more conformal deposition inside the contacts than when there is no bias in the substrate. The present invention is particularly useful for creating fill free of voids in conformal liners and microsized contacts having high aspect ratios.

Description

Apparatus and Method for Improved Deposition of High Aspect Ratio Conformal Liner Thin Films and Plugs

In the manufacture of integrated circuits, in particular, logic and memory circuits, the circuit structures used are more and more dense and compact. In addition, integrated circuits are now used to increase the interconnection of a plurality of metal levels as well as to increase the density of interconnections per level. In integrated circuit fabrication, continuously shaped holes, gaps and trenches are formed in the substrate, and in particular, holes / gaps are formed in the metal layer of the integrated circuit to provide interconnection between the metal layers. For example, when one substrate metal layer is formed on top of another layer, holes are made in the top layer to provide interconnection to the bottom layer. Holes and gaps often relate to techniques relating to contacts or vias, and will collectively relate to places such as "contacts." When interconnection is made between the layers, the contacts are filled with a suitable metal plug. Sometimes the metal plug has proceeded to the deposition of a liner thin film.

In the manufacture of integrated circuit devices, various interconnect metal layers are made in electrical contact to a semiconductor substrate or to other levels of interconnect through the contacts. The contacts form various interconnect metal layers by etching, masking or other techniques known to those of ordinary skill in the art. At one time a contact is formed and the interconnect metal layer or plug is deposited into the contact to provide electrical interconnection between the layers. Such thin films and layers may generally be deposited by known techniques such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

A conventionally known physical vapor deposition technique is sputter deposition. In sputter deposition, a target of a material, such as a metal target, is generally placed in a vacuum chamber opposite the substrate that receives a plug or layer of material. The working gas is introduced into a vacuum chamber adjacent to the target and electrically excited to produce a gas plasma having positively charged gas ions. The target is negatively biased and the ionized plasma species impinge on a negative electrode target, such as a dislodging material or a "sputtering" target. The evicted or sputtered material is deposited on the substrate surface and covers the substrate surface, thus forming or filling a line with certain contacts formed on the exposed substrate surface.

In densifying and densifying circuit structures on a substrate, the critical dimensions of the interconnects are made smaller and smaller. The “aspect ratio” of the contact is the ratio of the contact length to the width (or diameter if the contact hole is annular). If the contact dimension is made small, the aspect ratio of the contact portion becomes higher and higher. The high aspect ratio of these contacts is difficult to fill due to the interference of the material sputtered by the high contact walls, resulting in shadowing of the parts inside the contacts. However, current integrated circuit technology with smaller structures is desirable to improve performance and low cost.

In general, sputter deposition has been useful in testing conductive liner thin films and conductive plugs, and conventional sputter deposition techniques are problematic when deposition such as thin films and plugs into contacts is very high in aspect ratio, eg, aspect ratio is greater than or equal to 1.5. As such, when the aspect ratio of the contact exceeds 1, conventional sputter deposition becomes ineffective for depositing material into the bottom and side portions of the contact. Physical shading of the sidewalls of the contact occurs during deposition of the inclined sidewalls and the contact is hardly deposited at the bottom corners. As can be seen, this problem is exacerbated when the contact aspect ratio increases.

One known technique for improving the coating or coverage of the bottom and sidewalls in high aspect ratio contacts is to use plate-shaped collimators. The plate collimator is typically placed parallel to the substrate. The collimator has a wall, continuous tube, which blocks some sputtered material from the target. At an angle away from 0 ° (relative to the collimator), the sputtered material or incident flux is removed. Only a portion of the incident flux is allowed to pass through the collimator within an angle proportional to the ratio of the height of the hole to the collimator hole diameter. With this reduction in ratio, the aspect ratio of the collimator tube is increased and a large percentage of the total flux is incident on the substrate within a very small angle from vertical. However, at high aspect ratios of the plate collimator, suitable deposition is provided, which results in a large reduction in deposition rate, and reduces the efficiency of target utilization because abundant sputter material is deposited on the collimator. The present invention allows a low aspect ratio collimator to achieve a deposition profile similar to that of a high aspect ratio collimator and reduces the impact on deposition rate and target utilization. In addition, the present invention allows greater use of the collimator by reducing the proportion of material that accumulates.

Recently, the use of titanium and titanium nitride is preferred for lining contacts. In general, titanium and titanium nitride are collimator technologies for deposition conductors that produce thin films with regular crystal morphology, low impurity concentrations and low resistivity. However, conventional collimator processes still have the undesirable disadvantage of reducing the reliability of subsequent interconnect processes. In general, this disadvantage is that deposition inside the contacts can still be non-uniform with materials that are unsuitable for the corners of the contacts. For example, FIG. 1 shows a substrate 10 having an upper surface 12 that receives a layer of deposition material 14. The contact 16 formed in the substrate 10 has a sidewall 18 and a bottom surface 20. As shown in FIG. 1, sputter deposition by a conventionally known collimator technique produces a liner thin film 22 on a sidewall 18 that slopes from top to bottom, and the bottom corners of the contact 16 ( 21 may be produced discontinuously. Discontinuities in the sidewall thin film 22 and the corners can cause electrical failure of the interconnects.

A further disadvantage is the accumulation of material in the openings of the adjacent surface 12 contact 16. Referring again to FIG. 1, the round accumulations 24, typically associated with “overdeposit”, are overdeposited into the sidewalls 18 shade and contact openings of the contact 16. This overdeposition sometimes results in voids associated with the keyhole in the plug subsequently deposited on the contacts. 2, a conductive liner thin film 26, such as titanium or titanium nitride, is deposited by sputter deposition or chemical vapor deposition (CVD) (shown in FIG. 1), followed by a plug layer 22 such as aluminum or tungsten. ) Is deposited on the liner thin film 26 to fill the contact 16. The plug layer of aluminum is deposited by sputtering, and the plug layer of tungsten is deposited by chemical vapor deposition. In the plug filling process, the round excess deposition 24 in the contact opening grows faster than the plug layer 28 that is out of the contact opening closure before the contact is completely filled with the deposition material. In process temperature dependence, the plug layer 28 does not flow to the bottom of the contact 16 and sometimes leaves a void 30 associated with the keyhole. These keyholes appear due to the hasty closure of contacts in both sputter deposited aluminum and chemical vapor deposited tungsten, and are particularly challenging for contacts with high aspect ratios. The voids in the keyholes reduce manufacturing yields, resulting in unreliable electrical contacts, and reduce the number of devices available per substrate.

Accordingly, it is an object of the present invention to improve the adequate filling of contacts with conductive materials.

Yet another object of the present invention is to create a conformal liner layer at the contacts having a high aspect ratio.

Another object of the present invention is to increase the reliability of electrical contacts made in high aspect ratio contact holes.

Another object of the present invention is to reduce the overdeposition of the conductive layer in the inclined sidewalls and contacts.

It is another object of the present invention to produce a conductive plug free from openings, keyholes or voids, and to provide more reliable electrical interconnection between wafer layers.

Another object of the present invention is to increase the production yield of substrates with high aspect ratio contacts and to increase the number of devices available from the substrate wafer.

Another object of the present invention is to extend the collimator life.

The present invention relates to the formation of conductive liners and the formation of conductive plugs or the formation of non-conductive plugs for producing electrical interconnects or circuit elements for integrated circuits (IC's). In particular, the invention relates to the formation of conductive liners and conductive plugs in apertures or substrate contacts with high aspect ratios.

BRIEF DESCRIPTION OF THE DRAWINGS The drawings accompanying the partial constructions and embodiments of this specification illustrate embodiments of the invention and at the same time describe the invention given above, which are accepted to illustrate the principles of the invention and the embodiments given below will be described in detail. do.

1 is a cross-sectional view showing a contact having a layer of material deposited with a conventional collimator.

FIG. 2 is a cross-sectional view of a contact showing a layer of material deposited on the substrate contact of FIG. 1. FIG.

3 is a cross-sectional diagram illustrating a sputter deposition arrangement for practicing the present invention.

4A is a graph showing deposition rate and substrate current as a function of high frequency bias voltage in accordance with the principles of the present invention.

4B is a graph showing deposition rate and substrate current as a function of additional direct current bias voltage in accordance with the principles of the present invention.

4C is a graph showing the ratio of the substrate bias to the sputtered flow rate using the collimator and the net sputtered flow rate obtained using the collimator without the substrate bias shown as a function of the DC bias voltage.

4D is a bar graph depicting deposition rate as a function of substrate bias voltage.

5A is a bar graph showing the measured resistance of the substrate as a function of substrate bias voltage.

5B is a bar graph showing the uniformity of sheet resistance of a substrate coated in accordance with the principles of the present invention as a function of substrate bias voltage.

6A, 6B, and 6C are diagrams showing uniformity of plate resistance when the high frequency substrate bias voltages are 0 volts, 250 volts, and 450 volts, respectively.

7 is a bar graph showing measured reflectance of a substrate coated in accordance with the principles of the present invention as a function of substrate bias voltage.

8A, 8B and 8C are photographs showing various substrate contacts with suitable thin films deposited with a 450 volt high frequency substrate bias in accordance with the present invention.

The present invention provides improved coverage of bottom and sidewalls in sputter deposition and, in particular, improved coverage for useful contact substrates having high aspect ratios. The present invention is useful for depositing even more uniform and suitable conductor plugs to improve the electrical reliability of the liner thin film and the interconnections formed on the liner thin film. In addition, the present invention is to reduce excess accumulation in the openings of the contacts for providing interconnect plugs without voids. A further invention is used to plug the contacts with a conductive material.

The present invention utilizes a sputter deposition apparatus having a collimator in combination with an electrical biasing system operatively coupled to the substrate during sputter deposition for biasing the substrate. The collimator is disposed between the target material and the substrate, and in particular arranged to promote uniform deposition into the high aspect ratio contact and the substrate contact and to block sputtered particles at a predetermined angle of incidence. An electrical biasing system is operatively coupled to the substrate during sputter deposition for the substrate to be biased, and ions from the sputtering plasma impinge upon the substrate surface and at the same time effectively etch the surface with sputter deposition. The collimator provides nearly perpendicular incidence of sputter deposited particles for growing thin films in high aspect ratio contacts. By electrically biasing the wafer negatively with respect to the collimator, at the same time ion collisions occur during layer growth. The collimator affects the ion bombardment of the substrate with incident ions nearly perpendicular to the growth substrate layer to yield the advantages and results of the present invention.

At the same time the sputter deposition and effectively perpendicularly incident ion bombardment redistributes the material comprising overdeposition or round deposition in the openings of the contacts. The redistributed material is transferred into and into the contact with a flat area of the substrate with a plug or more uniform, conformal liner thin film within the contact. The present invention is to provide a more uniform and conformal liner layer without substantial overdeposition in the openings of the contacts. Subsequently, the layer of material deposited on the substrate and the plug deposited into the contacts have no voids or keyholes, and by providing such layers and plugs, the failure of electrical interconnects is minimized. This increases the manufacturing yield of circuits and devices from the substrate. In addition, the present invention significantly provides uniform properties in improved flat areas for conventional biased collimators (ie, collimators without substrate bias). For example, the uniformity and reflectivity of the plate resistance relates to improved non-biased collimation techniques.

In a suitable embodiment of the invention, a collimator having an aspect ratio between 1 and 2 is used. The combination of these collimators and biased substrates provides uniform and conformal deposition and reduces excess deposition to the extent possible with collimators, typically having high aspect ratios such as 2-3. With the low aspect ratio collimator used in the present invention, the deposition rate is not significantly reduced as is the case with the high aspect ratio collimator. That is, some sputter deposition material is collected by the collimator and then further available for deposition on the substrate. In particular, the present invention is useful for the deposition of liner layers and plugs in sub-microns (mm) with high aspect ratio contacts.

Other objects and advantages of the present invention are shown and described in the accompanying drawings.

3 shows an arrangement of equipment for practicing the present invention. In particular, a sputter deposition apparatus for practicing the present invention includes a process housing 32 defined within a process chamber containing a substrate. The housing 32 is operatively coupled to a vacuum device 36 for generating a vacuum in the chamber 34. A suitable device for practicing the present invention is Exrips Mark II available from the Materials Research Association of Congers, NY. The substrate 38 in the chamber 34 is supported on a substrate support 40 that is operably coupled to the substrate 38, and supports the back side of the substrate 38 and the support 40 for efficient heating of the substrate. A backside heating gas (not shown) is provided between the surfaces of the < RTI ID = 0.0 >

Substrate 38 disposed in chamber 34 is a target mount 42 that is coupled to target 44 material to be deposited on top surface 45 of substrate 38. Placed between the target 44 and the substrate 38 is a collimator having a plurality of gaps 48 in a limited place. The electrode 48 is either hexagonal or annular in shape, and the collimator 46 provides for the blocking of sputtered particles from the target 44 to yield sputtered particles in a suitable direction to impinge on the substrate surface 45 and The charging section or line contact section formed therein provides a liner layer or a plug. The shield 50 surrounds the target 44, and the chamber 34 blocks sputter deposited particles from deposition on the wall. The blank 50 is preferably grounded, can be removed, and replaced during periodic maintenance of the system 30.

The target support 42 and the target 44 are electrically connected to a DC power supply for biasing the target 44. As shown in FIG. 3, the target 44 is negatively biased relative to the collimator 46 held at ground potential. Upon deposition, gas is introduced into the chamber 34 from the process gas supply 54. The gas is suitably introduced between the cathode target 44 and the collimator 46. The power source is coupled to the process gas in the chamber 34 to ignite the plasma shown in FIG. 3, such as the plasma cloud 56. Various ions charged in an amount attracted to the negative electrode target 44 that are negative are generated by the plasma cloud ( 56), thereby colliding the target. The target particles are sputtered or expelled from the target 44 as shown by a suitable arrow and reference numeral 60. Some sputtered particles 60 are moved to the process chamber 35 toward the substrate 38. These some particles 60 have an excessively predetermined angle of incidence or an angle of flight caused by the particles to collide into the collimator 40, and the particles are blocked. These target particles 60 having an angle of incidence associated with a predetermined angle below the surface of the collimator are not blocked by the collimator 46 and are deposited on the substrate surface 45. Since the sputtered particles below the predetermined angle of incidence are blocked, the collimator is a function of the depth and diameter of the collimator gap 48 as is well known to those skilled in the art. Therefore, we do not discuss it here anymore.

The gap 48 of the collimator 46 has a limited height or depth 60 and a width or diameter 64. The ratio of the depth 62 to the width 64 is defined as the aspect ratio of the collimator 46. As is known, the high aspect ratio collimator gap 48 has a deep depth 62 and / or a narrow width 64 and generally has a greater number of sputters than the collimator gap having a small aspect ratio (ie, width and or shallow gap). Will block the particles 60. For example, the sputter particles 60b have an angle of incidence Φ from the target surface 57 associated with the face of the collimator that ensures to hit the side wall of one of the gaps 48. However, the sputtered particles 60a have a flight path that is more perpendicular to the surface 57 and then have an angle of incidence θ that avoids impingement on the sidewall surface of the collimator gap 48 for passing through the collimator, It is deposited on the substrate surface 45 and then contributes to create a metal layer or plug in the contacts located on the substrate surface 45. In general, the collimator is used to provide sputter deposition of particles having an angle of incidence of the incident surface 45 near normal. Sputter particles 60 at an angle of 90 ° have a flight path, and generally the vertical flight path will be blocked by the collimator 46. If the aspect ratio of the collimator gap is large, the percentage of sputtered particles is large and will block a lot. As mentioned above, the collimator provides assistance to the filling contact by removing these sputtered particles. However, the collimator evaluates the blocking of sputter particles, the collimator 46 reduces the deposition rate of sputter deposition, and is efficient because a large number of sputtered particles are deposited on the collimator 46 rather than being deposited on the substrate 38. Will reduce target usage.

In order to fill contacts with high aspect ratios, collimators with 2.5 or more high aspect ratio gaps will be useful. However, as a result of the reduction in deposition rate, the efficiency of the sputter deposition process is reduced, thus increasing the overall cost. The present invention typically provides a suitable coating of high aspect ratio contacts using a collimator 46 having an aspect ratio lower than the aspect ratio required for conventional collimator techniques. Therefore, the present invention effectively increases the deposition rate beyond that achieved with conventional collimators. In other words, the present invention provides a suitable liner on the order of sub-microns and generally provides high aspect ratio contacts with only a relatively high aspect ratio collimator.

In accordance with the principles of the present invention, the substrate support 40 and the substrate 38 are alternating or pulsed direct current sources to be operable to a source for biasing to provide a bias to the substrate 38 during sputter deposition. 70) or in direct current source (72).

In general, substrate 38 is negatively biased against collimator 46 maintained at ground potential. Like particles 59, ionized plasma particles of plasma cloud 56 are attracted to negatively biased substrate 38 to impinge upon surface 45. For example, other particles 59 ionized in the plasma 56 are attracted to the negatively biased substrate 38 while some particles 58 are attracted to the negative target 44 of the cathode. Ionized particles 59 are attracted to surface 45 and impinge on the surface, thus etching the layer of sputter deposited material on the surface.

Also, in accordance with the principles of the present invention, some of the ionized particles 59 attracted to the substrate 38 impinge on the collimator, as shown by the particles 59a to be blocked by the collimator, and from the surface 45 etching. Is blocked. For example, other ionized particles, particles 59b will be passed through collimator 46 to etch surface 45. In that way, the present invention provides a collimated etch and generally focuses the etch particles to have normal incidence on the surface 45. The invention provides more efficient etching and redistributes the sputter deposited material within the contacts than conventional collimators.

A particular advantage of the present invention is the redistribution of the sputter deposited material in the contacts to remove the voids formed in the corners at the junction of the side walls and the bottom. In addition, the sputter etching provided simultaneously by the present invention redistributes the excess deposition material into the contact to provide a more uniform and suitable liner layer. In addition, the reduction of excess deposition helps to remove voids in the corners. When the present invention is used for all contacts, it is used in particular for submicron sized contacts having a high aspect ratio. Providing a more uniform and suitable liner will result in less overdeposition at the contact openings, and subsequent conductive plugs will be deposited into the contact without creating keyholes or voids in the contact. Therefore, the present invention provides increased yield of chips and devices from the substrate, and also provides increased reliability of the device. In addition, the flat area substrate properties obtained by sputter deposition at the same time and the etching of the invention are accepted for industrial use.

Various process runs are made using the present invention to determine the properties of flat areas. The Exrips Mark II apparatus available from the Institute of Materials Research for process operations is used as described above. The substrate is processed with no bias (0 volts), direct current bias 200 and 400 volts, high frequency bias (13.56 MHz) 250 and 450 volts. Continuously 1500 to 5000 micron thin films are deposited between one and five wafers to obtain flat area data as discussed below. The flat area properties of the wafer to wafer are measured at the center of the wafer, and two to five wafers above the average value depend on the total number of wafers operating at a given bias condition. Titanium (Ti) with a film thickness of 2000 μs is deposited on pure silicon (Si) with silicon dioxide (SiO ₂ ) of 10 kÅ to obtain plate resistivity data and reflectance. Titanium with a film thickness of 2000 μs was deposited on pure silicon with the native oxide to obtain stress data. Titanium with a film thickness of 2000 to 5000 micrometers is deposited on the shaped / active wafers for contact fill information.

The collimator having an aspect ratio of 1.5 is used, the collimator for the present invention preferably uses a collimator having an aspect ratio in the range of 1.25 to 2.0. The holes of the collimator are hexagonal, have a diameter of 15.875 mm (0.625 inch), and the thickness of the collimator plate is 23.825 mm (0.938 inch). The separation distance maintained between the collimator and the substrate is 38.100 mm (1.500 inches).

The sputter cathode uses an IC-12 rotating magnet having a titanium target. The target spacing to the collimator is maintained at 36.880 mm (1.452 inches). The rotating magnet behind the target is rotated at 140 rpm to provide uniform sputter deposition. Power of 15 kW is supplied to the cathode target, and the substrate support 40 or the rear plane has a rear plane pressure of 6 to 8 tor for thermal heat exchange purposes, and the temperature is maintained at 300 ° C. A flow rate of argon (Ar) of 25 sccm is used, as a result of which the chamber 32 is maintained at an operating pressure of 1.1 m Torr.

Process result

Deposition rate

Deposition rates are measured according to high frequency and direct current bias functions. In addition, the total backplane current is also measured. The ground current in the DC rear plane is measured with a multimeter connected in series with a DC power supply, and measured as a voltage drop over a series of precision resistors connected in series. The high-frequency current measurement is performed with a current transformer, which can be purchased from Pearson, Palo Alto, Calif., With current monitor model 4100, with a sensitivity of 0.50V / A and a ± 3dB, and a bandwidth of 140Hz to 35MHz. Have The current transformer output is determined to be 50 ohms in the monitoring oscilloscope.

The deposition rate is removed by stripping of the sputter deposited layer, and the thickness measurement is calculated by using a pen-stripping lift-off, and the thickness of adjacent stripped films is calculated from the deposition rate. Is measured for. The thickness measurement is measured with a profiler, which can be purchased from Denko Instruments, Mountain View, California.

4A shows a graph of deposition rate and measured wafer vs. ground current for various high frequency bias voltages. As shown in Figure 4A, the deposition measurement bias value is better used than to determine other flat areas. In the figure, the reference arrow pointing to the X axis is particularly related to the curve. Referring to Figure 4A, the current increases the high frequency bias while the deposition rate is reduced.

4B shows a graph of wafer versus ground current and deposition rate as a function of direct current bias voltage. FIG. 4B shows a nearly inverse relationship between current and deposition rate as shown in FIG. 4A while the current increases the increased direct current bias, but generally the deposition rate is reduced. The increased bias of the substrate is reduced due to the re-sputtering generated in the substrate 38, and the effective deposition rate is reduced, and the increased number of plasma ions 59 leads to the substrate biased to the cathode.

Pure deposition rate is calculated from the measured direct current bias. Assuming that it is actually neutral, the ion flow rate is spatially uniform, and the evaluation of the pure deposition rate is given by the following equation.

Rnet = R ′ _C -R _W ∝ Φnet = Φ _C -Φ _W

Where? Is the particle flow rate, and the subscripts C and W relate to wafer deposition from cathode and wafer sputtering, respectively. The flow rate of the particles is received by the wafer from the cathode and given by equation (2).

The flow rate of particles sputtered from the wafer is given by equation (3).

Where P is the mass density of the target material, R is the deposition rate, N _A is the number of avogadros, W is the atomic mass (mass / mole) of the target material, I is the ion current through the wafer, and e is the process gas Ionic charge, and A is the wafer area. The yield (Y) for the argon / titanium device is obtained by the following equation.

Where t is the target, P is the particle, E is the ionization energy (keV), Z is the atomic number, and U is the binding energy (eV) of the surface atoms (Journal of Applied Physics 36,37 (1985)). .

The ratio Φ _net / Φ _c of the two theoretical and experimental flow rates is shown in FIG. 4C. The theoretical curve 80 of FIG. 4C accurately predicts a decrease in the deposition rate measured with increasing direct current bias as a result of re-sputtering on the substrate 38. However, at 400 volts DC bias there is an exceptionally high deposition rate due to the actual thickness measurement of the deposition.

Referring to FIG. 4D, the deposition rate is a bar graph as a function of bias voltage. From the measured deposition rates, the direct current bias proved more effective at resputtering the substrate than for high frequency bias for a given bias level.

Plate resistance

The plate resistance was measured at the center of the wafer with a Model 280, 4D automatic four point probe meter available from Prometrics. The resistance is derived by measuring and multiplying the sheet resistance as the thickness of the thin film deposited at the center of the wafer. The resistance is shown in FIG. 5A as a bar graph as a function of bias voltage. As shown, the resistance of the wafer increases as the bias voltage increases. Usually high resistance is the result of increased defects in the thin film, and the thin film in the deposited layer degrades the grain structure and is etched at the same time as the deposition. In addition, the incorporation of argon into titanium is expected in biased deposition and also serves to increase the resistance.

5B shows uniform plate resistance in the wafer WiW as a function of bias voltage. As shown, generally uniform plate resistance is improved with increased bias voltage. That is, there is a slight percentage change in the wafer for increased wafer bias.

6A, 6B and 6C show uniform and improved plate resistance to increase high frequency bias. 6A shows uniform reciprocal wafer plate resistance for zero volt bias while FIGS. 6B and 6C show uniform reciprocal wafer plate resistance for 250 volt high frequency bias and 450 volt high frequency bias, respectively. As shown, the substrate of FIG. 6C has improved plate resistance effectively and uniformly at 450 volt bias contours.

reflectivity

Reflectance measurements were made with NanoSpec / FT microarea gauges available from Sunnyvale Nanometrics, Calif., And are shown as bar graphs in FIG. The range of reflectance is typically high enough to accommodate 120% of the lower limit for optimum bias conditions.

Stress

In addition, the stress measurement was measured using the Model F 2300 available from Sunnyvale Flexus, California. The stress measurement results show that the residual stress decreases as the high frequency bias increases.

Process work data

Tables 1 to 4 below show various raw data measured from various process operations made using the present invention. The results of the process operations shown in the table below from the figure discussed above show that the present invention yields an acceptable calculation of flat area performance when compared to the standard uncollimated process.

In addition, the present invention provides a high aspect ratio plug for improved step coverage performance and suitable thin film deposition and sub-micron size contacts, and in fact improves liner and plug, which is important for prior art devices and methods. Yields a deposited deposition. 8A, 8B and 8C are photographs of the various contacts of a substrate process in accordance with the principles of the present invention, showing improved step coverage and suitable thin film coverage.

8A-8C illustrate the deposition of titanium on sub 0.5 micron contacts in accordance with the principles of the present invention using a collimator having a high frequency bias of 400 volts and an aspect ratio of 1.5: 1 on the wafer. 8A shows a contact 90 having an aspect ratio of 3.5: 1. The deposited thin film 92 is suitable and does not dramatically tilt in the corners of the bottom to eliminate voids in the corners as a result of prior art apparatus and methods (see FIG. 1). In addition, overdeposition 96 on top of the contact is effectively reduced. FIG. 8B shows a narrower contact 98 having a high aspect ratio of 4.5: 1 while FIG. 8C is an enlarged portion of the contact of FIG. 8B. As shown in FIG. 8B, even sub 0.5 micron sized contacts with a high aspect ratio of 4.5: 1 are more apparent than in FIG. 8C, and the thin film 100 is well suited, with empty space in the corner 102. It does not occur and does not slope down the bottom corner 102. As shown in FIG. 8C, the thin film 100 fits on the sidewall 104 and the bottom portion 106 of the contact portion 98 and the protrusion 108 at the top of the contact portion are reduced (see FIG. 8B). ). Thus, the present invention is suitable for deposition in very small places, which are high aspect ratio contacts, and provide improved step coverage. In addition, the reduction of overdeposition produced by the invention reduces the keyholes that occur when subsequent layers or plugs are deposited on the wired contacts (see FIG. 2).

Reflectance Bias (Bolts) Wafer number center Corner 405 nm 436 nm 480 nm 405 nm 436 nm 480 nm 0 V dc 3 111.4 123.0 137.3 108.9 120.7 134.7 0 V dc 4 110.2 121.8 136.2 107.9 119.5 133.6 0 V dc 5 108.8 120.6 135.1 106.8 118.3 132.1 0 V dc 6 108.8 120.4 134.7 108.0 119.6 133.9 0 V dc 7 108.5 120.1 134.6 106.1 117.8 131.9 250 rf 3 111.3 122.8 137.3 109.6 120.6 134.7 250 rf 4 111.4 123.0 137.5 109.7 121.1 135.0 450 rf 3 110.6 122.2 136.2 108.3 119.9 133.1 450 rf 4 109.3 120.7 134.6 110.2 121.7 135.9 200 dc 3 113.3 125.1 139.3 113.5 125.3 139.7 200 dc 4 113.5 125.2 139.3 113.1 125.0 139.0 400 dc 3 107.4 118.4 132.2 108.6 119.7 133.5 400 dc 4 106.2 117.8 131.2 106.8 118.0 132.0

Deposition rate Bias (Bolts) Wafer number Thickness (A) (A / s) Time in seconds 100 rf 3 1811.1 9.6 189 250 rf 6 1767.0 9.3 189 325 rf 9 1738.0 9.2 189 450 rf 12 1738.0 9.2 189 0 dc 15 1693.0 8.9 190 100 dc 3 1741.0 9.2 190 200 dc 6 1706.0 9.0 190 300 dc 9 1649.0 8.7 190 400 dc 3 1709.0 9.0 190 400 dc 12 1695.0 8.9 190 0 dc 3 1941.0 10.3 189 0 dc 6 1968.0 10.4 189 0 dc 9 1968.0 10.4 189 0 dc 12 1935.0 10.2 189 0 dc 15 1942.0 10.3 189 200 dc 7 1296.0 9.1 142 200 dc 13 1676.0 8.9 189 400 dc 10 1687.0 8.9 189 400 dc 3 1676.0 8.9 189 250 rf 3 4652.0 9.8 474 450 rf 12 1767.0 9.3 189 450 rf 15 1763.0 9.3 8.9

Stress Bias (Bolts) Wafer number (dyne / cm ² ) 0 dc 8 -2.22E + 09 0 dc 9 -2.11E + 09 250 rf 5 -1.88E + 09 250 rf 6 -1.86E + 09 450 rf 5 -5.49E + 07 450 rf 6 -6.89E + 06 200 dc 5 -9.68E + 09 200 dc 6 3.67E + 09 200 dc 6 (seconds working) 1.30E + 09 200 dc 7 4.58E + 09 400 dc 5 -1.52E + 08 400 dc 6 -2.54E-08

Plate resistance Bias (Bolts) Wafer number σ (μΩ-cm) Rs (Ω / sq) Unif (%) 0 dc 3 62.02 3.179 4.77 0 dc 4 24.04 3.283 4.00 0 dc 5 63.70 3.265 4.16 0 dc 6 62.66 3.212 4.34 0 dc 7 61.69 3.162 4.42 250 rf 3 69.32 3.737 2.39 250 rf 4 69.55 3.749 1.97 450 rf 3 77.23 4.375 1.23 450 rf 4 76.80 4.351 1.19 200 dc 3 61.79 3.633 2.27 200 dc 4 61.20 3.599 1.59 400 dc 3 67.49 4.014 2.04 400 dc 4 68.83 4.094 2.16

Although the present invention has been illustrated by various embodiments, these embodiments have been described in considerable detail, but the applicant of the present invention is not intended to limit the scope of the appended claims in detail as above. Additional advantages and improvements will be readily apparent to those skilled in the art. Accordingly, the scope of the broad features of the invention is not limited to the specific details representing the apparatus and method, and to the embodiments shown and described. Accordingly, the present invention can be improved from the details without departing from the general spirit or scope of the applicant.

Claims (30)

A sputter deposition system comprising a vacuum chamber having a sputtering plasma therein for sputter depositing a layer of material into a substrate contact having a very small size, the sputter deposition system comprising: To deposit on the substrate surface in the chamber and within the substrate contacts, ions from the sputtering plasma A target of deposition material, located in a vacuum chamber, coupled to a target bias source for negatively biasing the target to impinge on the target and produce material particles, A collimator disposed opposite the target and arranged to block sputtered particles of a predetermined angle of incidence on the substrate surface to promote uniform deposition in the substrate contact, An electrical bias system operatively coupled to the substrate during sputter deposition, wherein ions from the sputtering plasma collide with the substrate surface and generally reduce the excess deposition in the contacts and further promote uniform deposition in the contacts. By including an electrical bias system, operable to bias the substrate to effectively etch the surface concurrently with sputter deposition and to redistribute the deposited particles within the contacts, A substrate contact having a large aspect ratio can be uniformly coated with a layer of material and can be filled with a material having a reduced number of void spaces. 2. The sputter deposition system of claim 1, wherein the collimator is operably coupled to the substrate bias system and the target bias source and acts as a common reference potential for both the target and the biased substrate. The sputter deposition system of claim 1, wherein the substrate bias system comprises one of an alternating current source and a pulsed direct current source to bias the substrate during sputter deposition. 4. The sputter deposition system of claim 3, wherein the bias source operates at 200 MHz or less. 4. The sputter deposition system of claim 3, wherein the bias source operates at 20 MHz or less. 2. The sputter deposition system of claim 1, wherein the substrate bias system comprises a direct current source to bias the substrate with a direct current voltage during sputter deposition. 10. The sputter deposition system of claim 1, wherein the substrate bias system is operable to bias the substrate in the range of 10 to 5000 volts. A sputter deposition system comprising a vacuum chamber having a sputtering plasma therein for sputter depositing a layer of material into a substrate contact having a very small size, the sputter deposition system comprising: Deposition, coupled to a target bias source for negative biasing of the target, located in the vacuum chamber, so that ions from the sputtering plasma impinge on the target and produce material particles for deposition on the substrate surface in the chamber and within the substrate contacts. The target of the material, A collimator disposed opposite the target and arranged to block sputtered particles of a predetermined angle of incidence on the substrate surface to promote uniform deposition in the substrate contact, An electrical bias system operatively coupled to the substrate during sputter deposition, wherein ions from the sputtering plasma collide with the substrate surface and generally sputter deposition to reduce excess deposition in the contacts and promote uniform deposition in the contacts. And an electrical bias system, operable to negatively bias the substrate to effectively etch the surface and simultaneously redistribute the particles deposited within the contacts. A substrate contact having a large aspect ratio can be uniformly coated with a layer of material and can be filled with a material having a reduced number of void spaces. A sputter deposition system for sputter depositing a layer of material into a substrate contact having a very small size, With vacuum chamber, A gas supply for providing gas into the chamber; An excitation system for exciting the gas into a sputtering plasma comprising ions, A support for supporting a substrate having a contact portion having a small size, inside the chamber, A target support for supporting a target of deposition material in a chamber opposite the substrate support, such that ions from the sputtering plasma collide with the target and produce material particles to deposit on the surface of the substrate and into the contact; A target support operable to bias the Sputtered particles disposed between the target support and the substrate support and disposed at a predetermined angle on the surface of the substrate to promote uniform deposition inside the substrate contact and to promote empty filling of the substrate contact. Collimator configured to block, In order to reduce excess deposition in the contacts and further promote uniform deposition in the contacts, ions from the sputtering plasma collide with the substrate surface, effectively etch the surface simultaneously with sputter deposition, and redistribute the particles deposited in the contacts, An electrical bias system operatively coupled to the substrate to bias the substrate during sputter deposition, A substrate having a very small aspect ratio can be uniformly coated with a layer of material and filled with a material having a reduced number of void spaces. 10. The sputter deposition system of claim 9, wherein the collimator is operably coupled to a substrate bias system and the biased target support and acts as a common reference potential to the target and the biased substrate. 10. The sputter deposition system of claim 9, wherein the target support is operable to bias the target in the range of about 10 to 1000 volts. 10. The apparatus of claim 9, wherein the substrate bias system is operable to bias the substrate in the range of about 10 to 5000 volts. 10. The sputter deposition system of claim 9, wherein the substrate bias system comprises one of an alternating current source and a pulsed direct current source for biasing the substrate during sputter deposition. 14. The sputter deposition system of claim 13, wherein the bias source operates between approximately direct current and 20 MHz. 14. The sputter deposition system of claim 13, wherein the alternating current or pulsed direct current source operates between about 100 KHz and 20 MHz. 10. The sputter deposition system of claim 9, wherein the substrate bias system comprises a direct current source for biasing the substrate with a direct current voltage during sputter deposition. A method of sputter depositing a layer of material into a substrate contact having a very small size, Positioning the substrate in the vacuum chamber; Exciting a sputtering plasma comprising ions in the chamber; To create a deposition of sputtered material particles on the surface of the substrate and in the contacts formed within the substrate surface, the target of the deposition material is placed in a chamber opposite the substrate such that ions from the sputtering plasma impinge on the target, and Biasing the target, Blocking sputtered particles incident at a predetermined angle on the substrate surface to promote uniform deposition in the substrate contacts and to promote void-free filling of the substrate contacts; In order to reduce excess deposition in the contacts and further promote uniform deposition in the contacts, ions from the sputtering plasma collide with the substrate surface and effectively etch the surface generally at the same time as the sputter deposition, and particles deposited in the contacts Biasing the substrate to redistribute A sputter deposition method, characterized in that a substrate having a contact with a large aspect ratio can be uniformly coated with a material layer and filled with a material having a reduced number of void spaces. 18. The method of claim 17, wherein blocking the sputtered particles comprises placing a collimator between the target and the substrate to block the sputtered particles. The sputter deposition method further comprises electrically coupling a target and a substrate to the collimator such that the collimator acts at a common reference potential to the target and biased substrate. 18. The method of claim 17, further comprising negatively biasing the substrate to etch the substrate surface with positively biased ions from the plasma. 18. The method of claim 17, further comprising biasing the target in the range of about 10 to 1000 volts. 18. The method of claim 17, further comprising biasing the substrate in the range of about 10 to 5000 volts. 18. The method of claim 17, further comprising biasing the substrate with an alternating voltage during sputter deposition. 23. The method of claim 22, further comprising biasing the substrate between direct current and about 20 MHz. 23. The method of claim 22, further comprising biasing the substrate between about 100 KHz and 20 MHz. 18. The method of claim 17, further comprising biasing the substrate with a direct current voltage during sputter deposition. A method of sputter depositing a layer of material into a substrate contact having a very small size, Positioning a target of material in the sputter deposition chamber; Placing the substrate in a chamber opposite the target, with the substrate surface having the formed contact facing the target; Impinging particles from the excited gas plasma onto a target to sputter deposit a layer of material on the substrate surface and within the contact; In order to reduce excess deposition in the contacts and to promote uniform deposition in the contacts, particles are collided with the substrate surface to etch the substrate surface and the material layer generally simultaneously with sputter deposition of a material layer, and the contacts Redistributing the deposited material within A sputter deposition method, characterized in that a substrate having a contact with a large aspect ratio can be uniformly coated with a material layer and filled with a material having a reduced number of void spaces. 27. The method of claim 26, further comprising blocking sputtered particles incident at a predetermined angle on the substrate surface to further promote uniform deposition within the substrate contacts. 27. The method of claim 26, wherein blocking the particles comprises placing a collimator between the target and the substrate to block the sputtered particles. 27. The method of claim 26, further comprising electrically coupling a substrate and a target to the collimator such that the collimator acts as a common reference potential to the target and the substrate. 27. The method of claim 26, further comprising biasing the substrate to etch the substrate surface with positively biased ions from the plasma.