KR19990026754A - Recorder - Google Patents

Recorder Download PDF

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Publication number
KR19990026754A
KR19990026754A KR1019970049045A KR19970049045A KR19990026754A KR 19990026754 A KR19990026754 A KR 19990026754A KR 1019970049045 A KR1019970049045 A KR 1019970049045A KR 19970049045 A KR19970049045 A KR 19970049045A KR 19990026754 A KR19990026754 A KR 19990026754A
Authority
KR
South Korea
Prior art keywords
signal
address
analog
digital
input
Prior art date
Application number
KR1019970049045A
Other languages
Korean (ko)
Inventor
진영기
Original Assignee
구본준
엘지반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 구본준, 엘지반도체 주식회사 filed Critical 구본준
Priority to KR1019970049045A priority Critical patent/KR19990026754A/en
Publication of KR19990026754A publication Critical patent/KR19990026754A/en

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Abstract

The present invention relates to a recording apparatus, and since the conventional apparatus records only video and audio data input after being operated, there is a problem in that the input signal cannot be recorded because it has already passed if a user wants to record it when an input occurs . Accordingly, the present invention provides an input device for receiving an external input signal; An analog / digital converter for receiving a signal from the input unit and converting the signal; A clock generator for generating read and write signals and a reference signal; A read signal generator for receiving a recording signal and generating a read signal according thereto; An address counter which receives a reference signal from the clock generator and generates an address signal according thereto; A memory configured to receive an address signal of the address counter and store data of the analog / digital converter at an address corresponding to the address signal; A digital / analog converter for converting digital data of the memory into an analog signal; An analog output signal outputted from the digital / analog converter can be configured to output an input signal even if the recording device is operated after a desired input signal is generated.

Description

Recorder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording apparatus, and more particularly, to a recording apparatus in which a memory circuit can be recorded to record past video and audio data.

Fig. 1 is a block diagram showing the configuration of a conventional recording apparatus, and as shown therein, an input unit 10 for receiving a signal from the outside; An amplifier (11) for receiving a signal from the input unit (10) and amplifying it; It consists of an output unit 12 that receives the amplified signal of the amplifier 11 and outputs it, the operation of the conventional device configured as described above will be described.

First, the external input signal input through the input device 10 is amplified by the amplifier 11, and the amplified signal is recorded in the recording apparatus by the predetermined control signal through the output device 12.

Since the conventional apparatus operating as described above only records video and audio data input after being operated, there is a problem in that the input signal cannot be recorded because it has already passed if a user wants to record it when an input occurs.

Accordingly, an object of the present invention is to provide a recording apparatus capable of recording the same even if the recording apparatus is operated after a desired input signal is generated.

1 is a block diagram showing the structure of a conventional recording apparatus.

2 is a block diagram showing the configuration of the recording apparatus of the present invention.

3 is a circuit diagram of a read signal generator in FIG.

4 is an operation timing diagram of each part in FIG. 2;

* Explanation of symbols for main parts of the drawings

10: input device 12: output device

20: analog / digital converter 21: digital / analog converter

22: memory 23: clock generator

24: read signal generator 25: address counter

It is a bus 26

The above object is an input unit for receiving an external input signal; An analog / digital converter for receiving a signal from the input unit and converting the signal; A clock generator for generating read and write signals and a reference signal; A read signal generator for receiving a recording signal and generating a read signal according thereto; An address counter which receives a reference signal from the clock generator and generates an address signal according thereto; A memory configured to receive an address signal of the address counter and store data of the analog / digital converter at an address corresponding to the address signal; A digital / analog converter for converting digital data of the memory into an analog signal; The present invention is described by achieving an output device for outputting an analog signal output from the digital / analog converter.

Fig. 2 is a block diagram showing the construction of an embodiment of the recording apparatus of the present invention, and an input device 10 for receiving an external input signal as shown in the drawing; An analog / digital converter 20 which receives a signal from the input unit 10 and converts the signal; A clock generator 23 for generating a write signal Wt and a reference signal CLK; A read signal generator 24 which receives the recording signal REC and generates a read signal Rd according thereto; An address counter 25 which receives a reference signal CLK from the clock generator 23 and generates an address signal Addr according thereto; A memory 22 which receives an address signal Addr of the address counter 25 and receives data of the analog / digital converter 20 through a data bus 26 at a corresponding address; A digital / analog converter 21 for converting the digital data of the memory 22 into an analog signal; The output unit 12 outputs an analog signal output from the digital / analog converter 21.

FIG. 3 is a block diagram showing the configuration of the read signal generator 24, which has a falling edge detector 30 for detecting falling edges from the recording signal REC as shown in FIG. An AND operator (AN1) for ANDing the detection signal and the address signal (Addr) when the falling edge is detected by the falling edge detector (30); A register (31) for storing an address value output from the AND operator (AN1); A comparator 32 for comparing an address value stored in the register 31 with an address signal Addr generated by the address counter 25; RS flip-flop 33 which receives the output value of the comparator 32 and the recording signal REC and outputs the read signal Rd accordingly. Referring to the timing diagram of FIG. Will be explained.

First, when power is applied, the memory 22 and the address counter 25 are reset, and the address counter 25 designates the address of the memory 22 to which data is stored or read while increasing the address signal Addr by one. A signal such as (a) of FIG. 4 input from the outside through the input unit 10 is converted into a digital value by the digital / analog converter 21, and the digital value is stored in the memory 22 designated by the address counter 25. Is stored at the address of.

At this time, when the recording signal REC is set at the time t2 of FIG. 4 as shown in FIG. 22).

Here, the signal recorded in the memory 22 is data in which the signal input at the time point t1 of FIG. 4 is stored in the memory 22, and the signal input from the input unit 10 is the analog / digital converter 20. The converted value is converted into a digital value and stored in the memory 22 by the write signal Wt of the clock generator 23.

If the recording signal REC is reset, the delay time until the address value at that time is stored in the register 31 of the read signal generator 24 and an address value equal to the address value is generated in the address counter 25. The operation of reading the data in the memory 22 is continued during td).

Since the above operation is continued until the time t4 when the operation is reset, the input data up to the time t4 when the recording signal REC is reset is also stored in the memory 22.

Accordingly, the data stored in the memory 22 is converted by the digital / analog converter 21 by the read signal Rd of the read signal generator 24, and outputs the converted signal through the output unit 12.

The present invention operating as described above has an effect that the input signal can be recorded even if the recording device is operated after a desired input signal is generated by incorporating a memory circuit.

Claims (2)

  1. An input unit for receiving an external input signal; An analog / digital converter for receiving a signal from the input unit and converting the signal; A clock generator for generating a write signal and a reference signal; A read signal generator for receiving a recording signal and generating a read signal according thereto; An address counter which receives a reference signal from the clock generator and generates an address signal according thereto; A memory configured to receive an address signal of the address counter and receive data of the analog / digital converter through a data bus at an address corresponding to the address signal; A digital / analog converter for receiving digital data of the memory through the data bus and converting the digital data into an analog signal; And an output unit for outputting an analog signal output from the digital / analog converter.
  2. The read signal generator of claim 1, further comprising: a falling edge detector for detecting a falling edge of the recording signal; An AND operator which outputs an address value when a falling edge is detected by the falling edge detector; A register for storing an address value output from the AND operator; A comparator for comparing an address value stored in the register with an address value generated in an address counter; And an RS flip-flop configured to receive an output value of the comparator and a recording signal and output a read signal accordingly.
KR1019970049045A 1997-09-26 1997-09-26 Recorder KR19990026754A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970049045A KR19990026754A (en) 1997-09-26 1997-09-26 Recorder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970049045A KR19990026754A (en) 1997-09-26 1997-09-26 Recorder

Publications (1)

Publication Number Publication Date
KR19990026754A true KR19990026754A (en) 1999-04-15

Family

ID=66045563

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970049045A KR19990026754A (en) 1997-09-26 1997-09-26 Recorder

Country Status (1)

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KR (1) KR19990026754A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100923367B1 (en) * 2006-09-11 2009-10-23 키몬다 아게 A memory circuit, a dynamic random access memory, a system comprising a memory and a floating point unit and a method for storing digital data

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100923367B1 (en) * 2006-09-11 2009-10-23 키몬다 아게 A memory circuit, a dynamic random access memory, a system comprising a memory and a floating point unit and a method for storing digital data

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E902 Notification of reason for refusal
E601 Decision to refuse application