KR19990025333A - Phase Detection Method and Circuits for Timing Recovery of Residual Sideband HDTV Systems - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing recovery circuit of a high-definition digital television system (HDTV). In particular, the present invention relates to timing information of a residual sideband (VSB) HDTV signal, and corrects the phase of the transmission signal of a transmitter to improve the operating speed of the receiver. It relates to a phase detection circuit for fixing in synchronization with the transmitting side.

In the conventional timing recovery method, since the VSB signal is digitally processed by performing A / D conversion after timing and carrier recovery in the analog region, the entire process of IF signal sampling and timing recovery cannot be performed digitally. Processing time was much longer because synchronization was made using the sync field.

In contrast, the present invention focuses on the characteristic that the bandwidth of the received signal is the same as the symbol rate, and then manipulates the VSB signal on the sampled baseband to obtain information for timing recovery and then tracks the phase error. The present invention extracts the negative band edge signal and the positive band edge signal by band edge filtering the baseband VSB signal obtained by sampling the VSB modulated IF signal, and then converts the negative band edge signal into a conjugate complex signal. By obtaining the timing information by multiplying with the original positive band edge signal, the phase discrimination section for the timing information is set to [-π, π] and then simply arranged mathematically to provide a phase detection circuit having an optimal gate structure. do.

Description

Phase Detection Method and Circuits for Timing Recovery of Residual Sideband HDTV Systems

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing recovery circuit of a high definition television system (HDTV), and more particularly, to obtain information related to timing of a VSB HDTV signal, to correct a wrong phase of a transmission signal of a transmitter to transmit an operation speed of a receiver. A phase detection method and a circuit thereof for locking in synchronization with a side.

The modulation scheme of HDTV is mainly applied by orthogonal amplitude modulation (QAM, quadrature amplitude modulation) or residual sideband modulation (VSB, vestigial side band). The reason for adopting such a modulation scheme is that a multilevel modulation scheme must be used to transmit a large amount of data generated after encoding through a 6 MHz band, which is an existing NTSC transmission channel.

The HDTV transmission scheme adopted by the US "Grand Aliance" organization transmits data in frame units consisting of two fields. The signal to be transmitted is digitally encoded and then transmitted by performing M-level VSB modulation on each symbol.

The VSB modulation scheme of the GA-HDTV will be described in more detail as follows. The baseband input signal is shaped into a square root raised cosine filter, a kind of Nyquist filter. The pulse-shaped in-phase I-channel signal is again complex filtered to generate a quadrature Q channel signal. Orthogonal components of each channel in the baseband are converted to analog signals through D / A conversion, and then modulated into cosine and sine signals in the intermediate frequency band. By subtracting the Q channel signal from the modulated I channel signal, a VSB signal from which the lower band components are removed is obtained. Then, the VSB modulated signal is carried on the carrier to be transmitted to the receiver. That is, in the VSB method, a signal converted into an intermediate frequency is first converted into a radio frequency signal (RF) by a local oscillator and a mixer and transmitted.

Since the spectrum of the VSB modulated signal of GA-HDTV is 10.76M symbol / sec, the minimum bandwidth for signal transmission is 5.38 MHz when the Nyquist filter is applied. In this case, the square root generating cosine filter, which is a kind of Nyquist filter, has a roll-off factor, so that the bandwidth of the signal can be adjusted. The pilot carrier is located at 310 kHz from the left band boundary point. The addition of a pilot carrier has the effect of adding about 0.3 dB of total signal power, but the gain obtained by using this carrier locking is greater. In addition, the pilot signal is located in the sideband of the co-channel NTSC signal so that the interference to the NTSC receiver by the pilot signal can be ignored.

The VSB modulated signal is transmitted through the channel and demodulated through the reception process opposite to the transmitting side. First, the RF signal received through the antenna is lowered to the IF band through the tuner, and the signal tuned by the tuner unit is restored to the frequency and phase of the carrier through the carrier recovery unit. The reconstructed carrier is used to downlink the IF signal to baseband, and then digitally convert the downlinked baseband signal to perform frame synchronization and timing recovery.

The reason for performing the timing recovery is that the received signal located at the baseband is not synchronized at all compared with the transmitted signal when transmitted from the transmitter. This is because the sampling rate of the receiving end is not synchronized with the symbol rate of the transmitting end. In addition, in the digital receiver, in order to obtain a digital signal by sampling the received analog signal through an A / D converter, a frequency error caused by a mismatch between the speed of the transmission signal generated at the transmission stage and the sampling operation speed at the receiver side; Since the phase error has a big impact on the performance of the receiver as a whole, it is very important to take the sampling at the correct timing in the A / D converter that acquires the sampling signal. Timing recovery is what determines the most optimal sampling period.

The timing-restored clock is supplied to the entire system, which greatly affects system performance. Therefore, a more stable clock must be provided. Symbol timing recovery can be configured in both the baseband and the passband. Since digital systems with high data rates such as HDTV require real-time processing, it is known to perform timing recovery in the baseband.

1 is a block diagram illustrating a concept of timing recovery of a digital demodulation system.

As shown in FIG. 1, an interpolation filter 10 resamples a sampled signal obtained by sampling a received signal at a fixed sample clock f _S at an interpolation interval, thereby performing a band edge filter. 12). The band edge filter 12 is a kind of high pass filter that passes only the high pass component including the timing information in order to obtain information necessary for timing recovery. The timing component of the symbol obtained from the band edge filter 12 remains only a phase error component by a phase detector 13, and an average phase error value is passed through a loop filter 14. Obtained and then provided by a timing numerically controlled oscillator (NCO) 15. The timing numerically controlled oscillator 15 generates a control signal using the mean error component and provides it to the interpolation filter 10. The interpolation filter 10 sets a new interpolation interval according to the control signal.

When the phase synchronization is achieved while the new interpolation interval is set (i.e., locked in the timing recovery block), the received signal is then timing-restored by the interpolation filter 10 and output. The timing reconstructed signal is then filtered through a matched filter 11. The matched filter 11 is used to pulse shape the received signal to maximize the signal-to-noise ratio (SNR), and the matched filtered signal is provided to the next equalizer (not shown). The timing recovery block shown in FIG. 1 has many advantages in hardware implementation since the whole process can be digitally processed.

However, in the conventional timing recovery method, zenith's proposed method performs the A / D conversion and digitally processes the VSB signal after timing and carrier recovery in the analog domain, and inserts data synchronization for each field to synchronize data. We tried to recover the timing by using the signal characteristics of the field.

Since this conventional method does not perform timing recovery in the baseband, it is not possible to digitally process all demodulation processes including IF signal sampling and timing recovery. In addition, since the timing recovery is performed only when the data synchronization field signal is present because the data synchronization field signal is used, there is a problem in that processing time is required.

Accordingly, the present invention has been made to solve the above-described problems, and the present invention focuses on the characteristic that the bandwidth of the received signal is the same as the symbol rate, and manipulates the VSB signal on the baseband to provide timing information for timing recovery. It is an object of the present invention to provide a phase detection method and a circuit for reconstructing timing of a VSB signal that tracks a phase error after acquisition.

The phase detection method of the present invention for achieving the above object is a basis obtained by sampling the VSB modulated intermediate frequency signal in the phase error tracking in order to restore the timing by readjusting the sampling interval of the VSB signal on the baseband Band edge filtering the VSB signal on the band to extract a band edge signal of a negative region and a band edge signal of a positive region, respectively; Converting the band edge signal of the negative region into a conjugate complex signal and multiplying the converted conjugate complex signal by the band edge signal of the original positive region to obtain timing information of the input VSB signal; And taking the absolute value of the real I component of the timing information, and then multiplying the absolute value I component and the imaginary Q component of the original timing information to calculate a phase error signal.

In order to achieve the above object, the phase detection circuit of the present invention tracks a phase error in order to restore timing by readjusting the sampling interval of the VSB signal on the baseband. A band edge filter for extracting a band edge component of the negative region and a band edge component of the positive region; A static Hilbert filter extracting only a band edge component of a positive region among the output components of the band edge filter; A negative characteristic Hilbert filter extracting only a band edge component of a negative region among the output components of the band edge filter; Conjugate-converting the band edge component of the negative region of the negative Hilbert filter and multiplying the positive region band edge component of the positive Hilbert filter by the converted conjugate complex component to output timing information of the VSB signal Complex multiplication; And a phase error detector configured to receive timing information of the complex multiplier and calculate and output a phase error.

1 is a block diagram illustrating a concept of timing recovery of a digital demodulation system;

2 is a frequency spectrum for explaining a method for generating a timing signal for timing recovery of a VSB signal according to the present invention;

3 is a block diagram of a phase detection circuit for tracking phase error after generating a timing signal of a VSB signal in accordance with the present invention;

4 is a block diagram for explaining the band edge filter of FIG. 3 in comparison with a matched filter;

FIG. 5 is a diagram illustrating amplitude characteristics according to frequencies for the band edge filter and the matched filter of FIG. 4. FIG.

FIG. 6 is a diagram illustrating amplitude characteristics according to frequency for a signal filtered by the band edge filter of FIG. 4. FIG.

7 is a detailed block diagram of the static Hilbert filter of FIG.

FIG. 8 is a detailed block diagram of the negative Hilbert filter of FIG.

FIG. 9 is a diagram illustrating frequency responses of the static Hilbert filter of FIG. 7 and the negative Hilbert filter of FIG. 8;

10 is a detailed block diagram of the complex multiplication unit of FIG. 3;

11 is a waveform diagram of time of VSB timing information;

12 is a detailed block diagram of the phase error detector of FIG. 3;

FIG. 13 is a waveform diagram of an input / output signal according to time for determining characteristics of the phase error detector of FIG. 12.

FIG. 14 is a block diagram of a phase discrimination circuit having a simple structure by simplifying a common calculation part of a static Hilbert filter and a negative Hilbert filter according to the present invention.

Explanation of symbols on the main parts of the drawings

30: band edge filter 31: static Hilbert filter

32: negative characteristic Hilbert filter 33: complex multiplier

34: phase error detection unit

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, in order to facilitate understanding of the present invention, a process of converting a VSB signal in the intermediate frequency band into a sampled VSB signal in the baseband in the step before performing the timing recovery processing will be described.

The sampling rate is multiplied by '4/7' of the center frequency of the intermediate frequency band By sampling the intermediate frequency signal (f _IF ) and directly analog-to-digital conversion, a sampled VSB signal can be obtained. The sampled VSB signal thus obtained is separated into I-channel component and Q-channel component through complex demodulation and then transitions to baseband. The baseband signal is decimated filtered and output to a system clock that is 1/2 of the sampling clock, and the sampled VSB signal on the baseband output according to the half rate of the sampling clock is input to the timing recovery block. .

In fact, the sampling rate which directly downs the frequency to 44 MHz of the IF is 25.14 MHz, and the baseband sampled VSB signal is provided to the timing recovery block according to 12.57 MHz, which is half the value of this sampling rate.

2 is a frequency spectrum illustrating a method of generating a timing signal for timing recovery of a VSB signal according to the present invention.

FIG. 2A illustrates a signal input to a timing recovery block, that is, a sampled VSB signal on a baseband output according to a system speed (f _S = 12.57 MHz) through complex demodulation. The input VSB signal appears as a complex component (Complex) on the discrete time axis (Discrete_Time), and the pilot carrier of the VSB is carried in the left band edge region. Excess bandwidth exists due to the roll-off factor, but the bandwidth of the VSB is 10.76 MHz. Considering that the symbol rate of the original transmission side VSB signal is 10.76 MHz, it can be seen that the signal (a) of FIG. 2 having a system speed of 12.57 MHz has not yet been reconstructed.

FIG. 2B shows response characteristics of the band edge filter, and both band edge portions of the VSB signal of (a) can be extracted. The bandwidth of this band edge filter is equal to the bandwidth of the VSB signal and the center is at ± f _S / 2.

FIG. 2C is a signal in which the VSB signal of (a) is filtered by the band edge filter of (b). The filtered VSB signal is a band edge component of the negative region and a band edge component of the positive region including the pilot carrier of the VSB.

FIG. 2D shows a result of generating timing information of the VSB signal by appropriately manipulating the signal of (c). The sample rate f _S of the timing information is changed to 10.76 MHz, which is the original symbol rate of the VSB signal, which is possible using an interpolation filter.

That is, as shown in FIG. 2, the timing of the recovery of the symbol rate is obtained by appropriate signal manipulation using both band edge components, taking into consideration that the bandwidth of the VSB signal is the same as the symbol rate. The information can be used to track the phase error.

Therefore, the phase detection method of the present invention extracts the band edge signal of the negative region and the band edge signal of the positive region from the VSB signal on the baseband, and then converts the band edge signal of the negative region into a conjugate complex signal, When the conjugate complex signal and the band edge signal of the original positive region are multiplied by triangulation, timing information as shown in FIG. 2 (d) is obtained. Then, after taking the absolute value of the I component of the timing signal signal, multiplying the absolute value I component by the Q component of the original timing information to obtain a phase error signal.

3 is a block diagram of a phase detection circuit for generating a timing signal of a VSB signal and tracking phase error in accordance with the present invention.

The phase detection circuit calculates a timing phase error present in the VSB signal on the baseband from which the VSB modulated intermediate frequency signal is directly sampled and provides the next connected loop filter.

Referring to FIG. 3, the phase detection circuit receives a baseband VSB signal and extracts a band edge component of a negative region and a band edge component of a positive region on a frequency band, and a positive region. A positive Hilbert filter 31 extracting only the band edge components of the negative characteristic, a negative Hilbert filter 32 extracting only the band edge components of the negative region, and a band edge component of the negative region of the negative characteristic Hilbert filter 32 A complex multiplier 33 for multiplying a conjugate complex number, multiplying the positive region band edge component of the static Hilbert filter 31 by the conjugate complex component, and outputting timing information for a VSB signal, and the complex multiplier ( And a phase error detector 34 that receives the timing information of 33 and calculates and outputs a phase error.

Next, the operation and effect of each component of FIG. 3 will be described in detail with reference to the accompanying drawings.

FIG. 4 is a block diagram illustrating the band edge filter of FIG. 3 compared with a matched filter. FIG. 5 is a diagram illustrating amplitude characteristics according to frequencies of the band edge filter and the matched filter of FIG. 4. 4 is a diagram showing amplitude characteristics according to frequency with respect to a signal filtered by a band edge filter of 4. FIG.

The band edge filter used to extract the band edge signal existing on the frequency band is a filter in which the pulse shaping filter of the transmission stage is moved by 180 °. Therefore, if only the sign of the odd tap of the matching filter which has the same characteristic as the pulse shaping filter of a transmission stage is changed, it can manufacture easily.

Referring to FIG. 4, which simultaneously implements a band edge filter and a matched filter, an even tap memory 40 that outputs an even tap signal and an odd tap signal as an I or Q signal is input, and an odd tap including a center tap An memory 42, an adder 42 that adds the even tap signal and the odd tap signal to output a matched filtered signal, and subtracts the odd tap signal from the even tap signal to output a band edge filtered signal. And a subtractor 43.

As shown in FIG. 4, since the coefficients of the matched filter and the band edge filter are the same, there is an advantage of saving memory.

Referring to Figure 5, the characteristics of the matched filter are located around the baseband and have a band-limited spectrum at the maximum frequency | 1 / 2T |. The characteristics of the matched filter are implemented by the general square root generating cosine filter used at the transmitter and the receiver, which means that it is the same as the shape of the input signal at the receiver. The characteristics of the band edge filter exist only in the portion whose center is at | 1 / T | and the frequency satisfies f ≧ 1 / 2T −α |. Here, T corresponds to a symbol period, that is, 1 / T = symbol rate f _sym .

As can be seen from the characteristics of the band edge filter shown in FIG. 5, the signal obtained by band edge filtering the input signal is input only in the | 1 / 2T -α | ≤ f ≤ | 1 / 2T + α | portion as shown in FIG. 6. The signal will remain. At this time, the component on the negative frequency is called a band edge signal of the negative region, and the component on the positive frequency is called a band edge signal of the positive region.

Since the band edge signal does not have timing information by itself, the band edge signal is manipulated to produce the timing information, taking into account the characteristic that the band of the VSB signal is equal to the symbol rate. The signal output from the band edge filter 30 is separated into a negative region band edge signal and a positive region band edge signal, and then conjugate complex complexes of the negative region band edge signals are multiplied with the positive region band edge signal. In this case, timing information corresponding to the symbol rate can be obtained.

First, a Hilbert filter for separating a band edge signal into a negative region and a positive region is designed to satisfy Equation 1 below.

In Equation 1, zero is present in z = -j to make a notch in the negative band edge region. Therefore, the signal exists only in the positive band edge region of the band edge filtered signal, and the signal existing in the negative region is removed. In addition, when Equation 1 is modified such that zero is present in z = j, a notch is made in the positive band edge region to remove the positive band edge signal, and the signal exists only in the negative band edge region. In addition, in order to improve the performance of the filter in Equation 1, the N value may be increased to increase the number of taps of the filter.

FIG. 7 is a detailed block diagram of the static Hilbert filter of FIG. 3, FIG. 8 is a detailed block diagram of the negative Hilbert filter of FIG. 3, and FIG. 9 is a static Hilbert filter of FIG. Figure showing the frequency response for the Hilbert filter. 7 and 8 implement the Hilbert filter by applying the equation (1) when N = 2 as it is.

The static Hilbert filter of FIG. 7 receives a band edge filtered real I _i component and an imaginary Q _i component and outputs only real I _{o (+)} and imaginary Q _{o (+)} components of a band edge signal in a positive region. Four delay registers (70, 71, 72, 73), two multipliers (74, 75), three subtractors (76, 77, 79), and an adder (78) for multiplying the tap coefficient 2. . By arranging the output signal Y by multiplying the transfer function H of the static Hilbert filter and the input signal X, it is easy to see the input / output relationship between the components of FIG. 7.

In Equation 2, the input signal X is a band edge filtered complex signal I _i + jQ _i , the transfer function H is a static Hilbert filter corresponding to Equation 1, and the output signal Y is a positive band edge filtered complex signal. I _{o (+)} + jQ _{o (+)} .

The negative Hilbert filter of FIG. 8 receives a band edge filtered real I _i component and an imaginary Q _i component and outputs only real I _{o (-)} and imaginary Q _{o (-)} components of a band edge signal in a negative region. It consists of two delay registers 80, 81, 82, 83, two multipliers 84, 85 for multiplying tap coefficients 2, three subtractors 86, 87, 88, and an adder 89.

By arranging the output signal Y by multiplying the transfer function H of the negative characteristic Hilbert filter and the input signal X, it is easy to see the input / output relationship between the components of FIG. 8.

In Equation 3, the input signal X is a band edge filtered complex signal I _i + jQ _i , the transfer function H is a negative Hilbert filter obtained by substituting -j instead of j in Equation 1, and the output signal Y is negative The band edge filtered complex signal I _{o (−)} + jQ _{o (−)} .

Comparing the equations (2) and (3), only the signs of the one-sample delayed signal value 2Q _i z ^-1 of the real component and the one-sample delayed signal value of the imaginary component 2I _i z ^-1 are opposite to each other, and the rest are the same.

That is, when comparing the positions of the adder 78 that finally outputs the imaginary component and the subtractor 79 that finally outputs the real component in FIG. Able to know.

Subsequently, the frequency responses of the static Hilbert filter and the negative Hilbert filter are compared.

Referring to FIG. 9, the characteristic of the static Hilbert filter indicated by the dotted line is notched at the band edge portion (−1 / 2T) of the negative region, and the portion is removed, and only the band edge of the positive region is removed. Pass it through. In addition, the characteristic of the negative characteristic Hilbert filter indicated by the solid line is notched in the band edge portion 1 / 2T of the positive region, and the portion is removed, and only the bend edge of the negative region passes.

FIG. 10 is a detailed block diagram of the complex multiplier of FIG. 3, wherein the complex multiplier 33 selects a band edge component of a negative region of the sub-function Hilbert filter 32 (I _{o (−)} + jQ _{o ( -))} of the complex conjugate conversion was then positive temperature region band edge component amount of the Hilbert filter (31) and (I _{o (+)} + jQ _{o (+)),} the conjugated complex number components (I _{o (-)} -jQ _{o (-)} ) Multiplies by trigonometry to output VSB timing information. The complex multiplier 33 is composed of four multipliers 100, 101, 102, 103, an adder 104, and a subtractor 105. Summarizing the positive region band edge component (I _{o (+)} + jQ _{o (+)} ) and the conjugate complex component (I _{o (-)} -jQ _{o (-)} ), the input and output between the components of FIG. The relationship is easy to see.

The component output from the adder 104 in FIG. 10 is the real I component of the VSB timing information, and the component output from the subtractor 105 corresponds to the imaginary Q component of the VSB timing information.

The phase error detection unit 34 for determining the phase error using the VSB timing information produced by the preprocessing up to now will be described with reference to FIGS. 11 to 13.

11 is a waveform diagram of time of VSB timing information.

The waveform diagram of the VSB timing information in FIG. 11 briefly illustrates the signal output from the complex multiplier 33. FIG. 11 is a simplified diagram for convenience of VSB timing information, and the waveform actually output is not completely identical to that of FIG. 11 because the symbol has a different level for each symbol. Because they have different appearances.

(A) of FIG. 11 is a real I component of VSB timing information, (b) is an imaginary Q component of timing information, and (a) and (b) have a Hilbert relationship with each other. One symbol period of the signals (a) and (b) is indicated by a dotted line, and the information indicated when (a) the signal is sampled at a phase of 90 ° and the signal (b) is sampled at a phase of 0 ° are indicated by a dotted line. It is possible to obtain an optimal sampling signal without loss of.

At this time, (b) since the phase region of the imaginary Q signal has zero crossing for every symbol period T, the phase error is determined using this characteristic.

12 is a block diagram of the phase error detector of FIG. 3, and FIG. 13 is a view illustrating a change of an input / output signal with time to find out characteristics of the phase error detector of FIG. 12.

Referring to FIG. 12, the phase error detector 34 takes an absolute value of the real I signal in the timing information of the VSB through the limiter 110, and an imaginary Q in the absolute value I signal and the VSB timing information of the limiter 110. The signal is multiplied by the multiplier 111 and output. The signal output from the multiplier 111 is the phase error we want to obtain. This phase error signal is then input to a connected loop filter (not shown) to obtain an average phase error and then used to compensate for the timing phase error.

Referring to FIG. 13, (a) shows the real I signal of the timing information of the VSB as a dotted line, and the waveform of the limiter signal for limiting the I signal is shown by a solid line. The absolute value of the real I signal is obtained by multiplying the real I signal by a limiter signal having a value of ± 1.

(b) is a waveform diagram of an imaginary Q signal of timing information of VSB. The position where zero crossing of the imaginary Q signal occurs is the optimal sampling position, and the period is one symbol period.

(c) is a waveform diagram of a phase error signal obtained by multiplying the absolute value of the real I signal obtained in (a) and the imaginary Q signal of (b). The phase error signal has a phase error of 0 at the optimal sample point of each symbol, and the larger the phase error, the larger the error is represented by an S-shaped curve. At this time, the interval in which the phase error can be determined is [-π, π]. The phase errors are sent to the loop filter and adjusted in the direction of decreasing phase error, resulting in full timing recovery.

FIG. 14 is a block diagram of a phase discrimination circuit having a simple structure by simplifying a common calculation part of a static Hilbert filter and a negative Hilbert filter according to the present invention.

The phase discrimination circuit of FIG. 14 includes a common calculating unit 140, a positive characteristic Hilbert filter 142, a negative characteristic Hilbert filter 144, a complex multiplication unit 146, and a phase error discriminating unit 148. .

It has already been described that there are components that are commonly used for the two filters among the components constituting the static Hilbert filter of FIG. 7 and the components constituting the negative characteristic Hilbert filter of FIG. 8. Therefore, the phase discrimination circuit of FIG. 14 separates the components common to the two filters into the common calculation unit 140 without separately designing them, thereby outputting the output value of the common calculation unit (the calculated value in the intermediate stage of the filtering; Median value) may be configured to be used simultaneously for both the static Hilbert filtering and the negative Hilbert filtering.

The common calculator 140 includes two delay registers 140-1 and 140-2 for receiving and processing an input I _i signal, a subtractor 140-3, and a multiplier 140-4, and input Q. _It consists of two delay registers 140-5 and 140-6, a subtractor 140-7 and a multiplier 140-8 which receive and process the _i signal.

The positive Hilbert filter 142 subtracts the output of the multiplier 140-8 for the input Q _i signal from the output of the subtractor 140-3 for the input I _i signal of the common calculator 140 to positive band. A subtractor 142-1 for outputting an edge I _{o (+)} signal and a subtractor 140- for the output of the multiplier 140-4 for the input I _i signal of the common calculator 140 and the input Q _i signal; And an adder 142-2 which adds the output of 7) and outputs a positive band edge Q _{o (+)} signal.

The negative characteristic Hilbert filter 144 adds the output of the multiplier 140-8 for the input Q _i signal from the output of the subtractor 140-3 for the input I _i signal of the common calculator 140. An adder 144-1 for outputting an edge I _{o (−)} signal and a multiplier 140− for the input I _i signal at the output of the subtractor 140-7 for the input Q _i signal of the common calculator 140; And a subtractor 144-2 which subtracts the output of 4) and outputs a negative band edge Q _{o (-)} signal.

The complex multiplier 146 includes four multipliers 146-1 for calculating VSB timing information I + jQ from the band edge signals output from the positive Hilbert filter 142 and the negative Hilbert filter 144. 146-4), and an adder 146-5 for outputting the I signal of the timing information, and a subtractor 146-6 for outputting the Q signal of the timing information. )

The phase error detection unit 148 is composed of a limiter 148-1 and a multiplier 148-2 for multiplying the absolute value of the I signal of the timing information with the Q signal of the timing information. See description in 12)

Summarizing the operation of FIG. 14, a band edge signal I _{o (+)} + jQ _{o (+)} having a positive frequency component of the baseband VSB signal I _i + jQ _i is defined as a static Hilbert filter 142. ), And a band edge signal (I _{o (−)} + j Q _{o (−)} ) having a negative frequency component is extracted through the acoustic Hilbert filter 144. When the negative band edge signal is conjugated and complex multiplied by the positive band edge signal in the complex multiplier 146, timing information (I + jQ) of VSB, which is a symbol rate, can be obtained. The phase error detector 148 calculates the phase error using the information.

As described above, the present invention can digitally perform full timing recovery by directly processing baseband VSB signals to obtain timing information and calculating phase error using the timing information. In addition, timing recovery is performed every time a symbol is transmitted, so that timing recovery can be completed in a short time. In the preprocessing to obtain timing information, the band edge filter 12 (see Fig. 4) for extracting only the band edge components of the baseband VSB signal has hardware advantages, as it uses the same coefficient value as the matched filter. . In addition, the same calculations used in the static Hilbert filtering and the negative Hilbert filtering are implemented by using a common calculation unit 140 (see FIG. 14) externally and can be used in common, thereby reducing the number of hardware by half. Can be configured.

Claims (11)

Band edge filtering the baseband VSB signal obtained by sampling the VSB modulated intermediate frequency signal and extracting the negative edge band band signal and the positive band band edge signal, respectively; Converting the band edge signal of the negative region into a conjugate complex signal and multiplying the converted conjugate complex signal by the band edge signal of the original positive region to obtain timing information of the input VSB signal; And And taking the absolute value of the real I component of the timing information, and multiplying the absolute value I component and the imaginary Q component of the original timing information to calculate a phase error signal. Phase detection method for timing recovery of a signal. In tracking the phase error for restoring the timing by readjusting the sampling interval of the VSB signal on the baseband obtained by sampling the VSB modulated intermediate frequency signal, A band edge filter 30 which receives a VSB signal on a baseband and extracts a band edge signal of a negative region and a band edge signal of a positive region on a frequency; A static Hilbert filter 31 for extracting only band edge signals of positive regions among the output components of the band edge filter 30; A negative characteristic Hilbert filter 32 which extracts only a band edge signal of a negative region among the output components of the band edge filter 30; Conjugate-converts the band edge signal of the negative region of the negative characteristic Hilbert filter 32 and multiplies the positive region band edge signal of the positive characteristic Hilbert filter 31 by the converted conjugate complex signal to a VSB signal. A complex multiplier (33) for outputting timing information about the complex number; And a phase error detector (34) for receiving timing information of the complex multiplier (33) to calculate and output a phase error. 3. The tap coefficient of the band edge filter 30 is equal to the coefficient of a matched filter for detecting a signal by maximizing an input signal-to-noise ratio (SNR), and an even number for outputting an even tap signal according to an input signal. A tap memory 40; An odd tap memory 41 including a center tap for outputting an odd tap signal in accordance with an input signal; And a subtractor (43) for subtracting the odd tap signal from the even tap signal to output a band edge filtered signal. The transfer function characteristic of the static Hilbert filter 31 is (N = number of taps), the notch occurs at the band edge portion (-1 / 2T) of the negative region, and the portion is removed, and the real I _{o (+)} for the band edge signal of the positive region _. A delay register (70, 71, 72, 73) for outputting only the component and the imaginary Q _{o (+)} component, a multiplier (74, 75), a subtractor (76, 77, 79), and an adder (78), The transfer function characteristic of the negative characteristic Hilbert filter 32 is , (N = number of taps), where notches occur in the band edge portion (1 / 2T) of the positive region and the portion is removed, and the real I _{o (-)} component of the bend edge signal of the negative region. And a delay register (80,81,82,83), a multiplier (84,85), a subtractor (86,87,88), and an adder (89) for outputting only and an imaginary Q _{o (-)} component. Phase Detection Circuit for Timing Recovery of Residual Sideband HDTV Systems. The complex multiplier (33) of claim 2, wherein the complex multiplier (33) converts a band edge signal of a negative region of the sub-character Hilbert filter (I _{o (−)} + j Q _{o (−)} ) by a conjugate complex number. Positive domain band edge signal of static Hilbert filter 31 and (I _{o (+)} + jQ _{o (+)} ) multiply the conjugate complex signal by (I _{o (-)} -jQ _{o (-)} ) trigonometry And a multiplier (100, 101, 102, 103) for calculating and outputting VSB timing information (I + jQ), an adder (104), and a subtractor (105). 3. The apparatus of claim 2, wherein the phase error detector (34) comprises: a limiter (110) which takes an absolute value of a real I signal among timing information (I + jQ) of VSB; And a multiplier 111 for multiplying the absolute value I signal of the limiter 110 and the imaginary Q signal of the VSB timing information to calculate a phase error. Phase detection circuit. Negative frequency by band edge filtering the baseband VSB signal obtained by directly sampling a VSB modulated intermediate frequency signal with a symbol rate of (f _sym = 1 / T) at the sampling rate f _sample = 4/7 × f _sym In calculating the phase error for timing recovery using band edge components obtained at (-1 / 2T) and positive frequency (1 / 2T), respectively, Filtering on a band edge filtered VSB signal to extract positive frequency (1 / 2T) edge components (positive Hilbert filter: , N = taps) and filtering (negative Hilbert filter to extract negative frequency (-1 / 2T) edge components: A joint calculation unit 140 for calculating and outputting a median value jointly included in the calculation process of N = taps; A static Hilbert filter 142 which receives only the intermediate value of the joint calculating unit 140 and extracts only a positive frequency (1 / 2T) edge component; A negative characteristic Hilbert filter 144 which receives only the intermediate value of the joint calculating unit 140 and extracts only a negative frequency (−1 / 2T) edge component; Conjugate complex-converts the negative frequency edge component of the sub-characteristic Hilbert filter 144, and then multiplies the positive frequency edge component of the positive-character Hilbert filter 146 by the converted conjugate complex component to provide timing information for the VSB signal A complex multiplication unit 146 for outputting a; And And a phase error detector (148) for receiving the timing information of the complex multiplier (146) and calculating and outputting a phase error. The method of claim 7, wherein the common calculator 140 comprises: a first delay register (140-1) for receiving a input I _i signal and delaying one tap; A second delay register 140-2 for delaying the output of the first delay register 140-1 by one tap; A first subtractor 140-3 which subtracts the output of the second delay register 140-2 from the input I _i signal; A first multiplier 140-4 which multiplies the output of the first delay register 140-1 by the tap coefficient and outputs the multiplier; A third delay register 140-5 which receives an input Q _i signal and delays a one tap; A fourth delay register 140-6 for delaying the output of the third delay register 140-5 by one tap; A second subtractor 140-7 which subtracts the output of the fourth delay register 140-6 from the input Q _i signal; And a second multiplier (140-8) for multiplying the output of the third delay register (140-5) by the tap coefficient and outputting the multiplier. The method of claim 7, wherein the static Hilbert filter 142 is a second multiplier for the input Q _i signal at the output of the first subtracter 140-3 for the input I _i signal of the common calculator 140 A subtractor 142-1 for subtracting the output of 140-8 to output a positive band edge I _{o (+)} signal; A positive band edge Q _{o is obtained} by adding the output of the first multiplier 140-4 to the input I _i signal of the common calculator 140 and the output of the second subtractor 140-7 to the input Q _i signal. An adder 142-2 for outputting a _positive signal, The negative characteristic Hilbert filter 144 outputs the second multiplier 140-8 for the input Q _i signal from the output of the first subtracter 140-3 for the input I _i signal of the common calculator 140. An adder 144-1 for adding a negative band edge I _{o (−)} signal to add a signal; A negative band edge Q _o by subtracting the output of the first multiplier 140-4 for the input I _i signal from the output of the second subtractor 140-7 for the input Q _i signal of the common calculator 140. _And a subtractor (144-2) for outputting a negative _(-) signal. The complex multiplication unit 146 of claim 7, wherein the complex multiplier 146 outputs the output of the subtractor 142-1 of the positive Hilbert filter 142 and the adder 144-2 of the negative Hilbert filter 144. A first multiplier 146-1 for multiplication; A second multiplier (146-2) for multiplying the output of the adder (142-2) of the static Hilbert filter (142) with the output of the subtractor (144-1) of the subfeature filter (144); A third multiplier (146-3) for multiplying the output of the adder (142-2) of the static Hilbert filter (142) with the output of the adder (144-2) of the subfeature filter (144); A fourth multiplier (146-4) for multiplying the output of the subtractor (142-1) of the static Hilbert filter (142) and the output of the subtractor (144-1) of the subfeature filter (144); An adder (146-5) for adding the outputs of the first multiplier (146-1) and the second multiplier (146-2) to finally output the real I component of the timing information of the VSB signal; And a subtractor 146-6 which adds the outputs of the third multiplier 146-3 and the fourth multiplier 146-4 to finally output the imaginary Q component of the timing information of the VSB signal. Phase detection circuit for timing recovery of residual sideband HDTV system. 8. The apparatus of claim 7, wherein the phase error detector (148) comprises: a limiter (148-1) which takes an absolute value of the output of the adder of the complex multiplier (146) (real I signal in the timing information of VSB); A multiplier 148-2 that multiplies the output of the limiter 148-1 and the output of the subtractor 146-2 of the complex multiplier 146 (an imaginary Q signal of VSB timing information) to calculate a phase error value Phase detection circuit for timing recovery of the residual sideband HDTV system, characterized in that it comprises a).