KR19990024642A - De-flip flop for high speed operation - Google Patents

Abstract

The D flip-flop according to the present invention has a first input terminal and a first output terminal, and the second output terminal is connected to the second output terminal while the clock signal is maintained at the first level voltage regardless of the voltage level of the first input terminal. A first logic circuit for maintaining at a level voltage and maintaining the first output terminal at the same level as an input signal input through the first input terminal while the clock signal is maintained at a second level voltage; A first output connected to the first output terminal, inactive while the clock signal is held at a first level voltage, and having a same level as the first output terminal while the clock signal is held at a second level voltage; A second logic circuit for outputting the signal and its complementary second output signal.

Description

D FLIP FLOP CAPABLE OF HIGH SPEED OPERATION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to logic circuits and, more particularly, to D flip flops (FF), which are capable of high speed operation and high integration.

1, there is shown a circuit diagram showing a detailed circuit of a D flip-flop according to the prior art. 2 is a diagram illustrating a simulation result of FIG. 1. The conventional D flip-flop uses a transmission gate in which each source and drain of one P-channel MOS transistor and one N-channel MOS transistor are commonly connected as a switch element. And such a transfer gate, i.e., a switch, is switched by a clock signal CK and its complementary clock signal CKB, i.e. a dual clock.

The transfer gate used as a switch element in a CMOS circuit has the advantages of stability of circuit operation and signal transfer without attenuation of the transfer signal, but structurally, because each source and drain of the transistors are interconnected, Parasitic capacitance is present at the output stage. The transfer gate of such a structure is disadvantageous in terms of operating speed. For example, in a programmable frequency synthesizer (not shown), an input signal having several tens of MHz is applied to its input stage, and the output signal has various frequencies ranging from several tens of MHz to several hundred MHz generated by a voltage controlled oscillator. As is well known, an output signal with a frequency of several hundred MHz is also used as the input of a divider consisting of D or T flip-flops depending on the negative feedback, making it difficult for such flip-flops to operate properly at high operating frequencies.

It is therefore an object of the present invention to provide a D flip-flop that is capable of high speed operation and high integration.

1 is a circuit diagram showing a detailed circuit of a D flip-flop according to the prior art;

2 is a view showing a simulation result of FIG.

3 is a circuit diagram showing a detailed circuit of a D flip-flop according to the present invention;

4 is a view showing a simulation result of FIG.

Explanation of symbols for the main parts of the drawings

10: first power supply terminal 12: second power supply terminal

14: first input terminal 16: second input terminal

100: first logic circuit 200: second logic circuit

According to one aspect of the present invention for achieving the above object, it has a first input terminal and a first output terminal, the clock signal is maintained at the first level voltage regardless of the voltage level of the first input terminal While maintaining the first output terminal at a second level voltage, and maintaining the first output terminal at the same level as an input signal input through the first input terminal while the clock signal is maintained at a second level voltage. First logic means for; A first output connected to the first output terminal, inactive while the clock signal is held at a first level voltage, and having a same level as the first output terminal while the clock signal is held at a second level voltage; Second logic means for outputting the signal and its complementary second output signal.

In this embodiment, the first level voltage is the level of the ground potential, and the second level voltage is the level of the power supply voltage.

In this embodiment, said first logic means comprises: a first power supply terminal for receiving said power supply voltage; A second power supply terminal for receiving the ground potential; A second input terminal for receiving the clock signal; A first transistor having a current path and a gate, said gate coupled to said first input terminal; A second transistor having a current path and a gate, the gate being connected to the second input terminal; A third transistor having a current path and a gate, the gate being connected to the first input terminal; Each current path of the first, second and third transistors is sequentially formed in series between the first power supply terminal and the second power supply terminal; A fourth transistor having a current path and a gate, the gate being connected to the second input terminal; A fifth transistor having a current path and a gate, wherein the gate is connected to a common connection point at which the current paths of the second and third transistors are commonly connected; A sixth transistor having a current path and a gate, said gate connected to said second input terminal, wherein current paths of said fourth, fifth, and sixth transistors comprise said first power supply terminal and said second power supply; Sequentially formed in series between the terminals and the current paths of the fourth and fifth transistors are commonly connected to the first output terminal.

In this embodiment, the first, second, and fourth transistors are composed of P-channel MOS transistors, and the third, fifth, and sixth transistors are composed of N-channel MOS transistors.

In this embodiment, said second logic means comprises: a second output terminal for outputting said first output signal; A third output terminal for outputting the second output signal; A seventh transistor having a current path formed between the first power supply terminal and the third output terminal and a gate connected to the first output terminal; An eighth transistor having a current path and a gate, wherein the gate is connected to the first output terminal; A ninth transistor having a current path and a gate, the gate of which is connected to the second input terminal; Current paths of the eighth and ninth transistors are sequentially formed in series between the third output terminal and the second power supply terminal; A tenth transistor having a current path formed between the first power supply terminal and the second output terminal and a gate connected to the third output terminal; And an eleventh transistor having a current path formed between the second output terminal and the second power supply terminal and a gate connected to the third output terminal.

In this embodiment, the seventh and tenth transistors are composed of P-channel MOS transistors, and the eighth, ninth and eleventh transistors are composed of N-channel MOS transistors.

According to another aspect of the present invention, there is provided a D flip-flop including a master stage and a slave stage, the master stage comprising: a first dynamic inverter for inverting a phase of an input signal in response to a dynamic drive signal; And a second dynamic inverter for inverting a phase of the dynamic drive signal in response to an output signal of the first dynamic inverter.

In this embodiment, the first dynamic inverter comprises: a first power supply terminal for receiving a power supply voltage; A second power supply terminal for receiving a ground potential; A first input terminal for receiving the input signal; A second input terminal for receiving the dynamic drive signal; A first transistor having a current path and a gate, said gate coupled to said first input terminal; A second transistor having a current path and a gate, the gate being connected to the second input terminal; A third transistor having a current path and a gate, the gate being connected to the first input terminal; Each current path of the first, second and third transistors may be sequentially formed in series between the first power supply terminal and the second power supply terminal.

In this embodiment, the dynamic drive signal is a clock signal.

In this embodiment, the second dynamic inverter comprises: a fourth transistor having a current path and a gate, the gate being connected to the second input terminal; A fifth transistor having a current path and a gate, wherein the gate is connected to a common connection point at which the current paths of the second and third transistors are commonly connected; A sixth transistor having a current path and a gate, said gate connected to said second input terminal, wherein current paths of said fourth, fifth, and sixth transistors comprise said first power supply terminal and said second power supply; And are sequentially formed in series between the terminals and the current paths of the fourth and fifth transistors are commonly connected to the first output terminal.

In this embodiment, the first, second and fourth transistors are composed of P-channel MOS transistors, and the third, fifth and sixth transistors are composed of N-channel MOS transistors. do.

In this embodiment, the first level voltage is the level of the ground potential, and the second level voltage is characterized in that the level of the power supply voltage.

By such a circuit, by implementing a switching operation without using the transfer gate as a switch element, it is possible to prevent the speed drop due to parasitic capacitance present at the input and output terminals of the transfer gate.

Hereinafter, reference will be made in detail with reference to FIGS. 3 and 4 according to an embodiment of the present invention.

3 is a circuit diagram showing a detailed circuit of a D flip-flop according to a preferred embodiment of the present invention. 4 is a diagram illustrating a simulation result of FIG. 3. Referring again to FIG. 3, the D flip-flop according to the present invention consists of first and second logic circuits 100 and 200, and the first logic circuit 100 operates as a master stage and the second stage. The logic circuit 200 operates as a slave stage. The first logic circuit 100 includes three PMOS transistors M10, M11 and M13 and three NMOS transistors M12, M14 and M15.

The current paths of the transistors M10, M11, and M12 constituting the first logic circuit 100 are the first power supply terminal 10 and the ground potential VSS for receiving the power supply voltage VDD. Are sequentially formed in series between the second power supply terminals 12 for receiving the pressure. The gates of the PMOS and NMOS transistors M10 and M12 are connected to an input terminal 14 for receiving an input signal D, and the gate of the PMOS transistor M11 is for receiving a clock signal CK. It is connected to the input terminal 16. The transistors M10, M11, and M12 are composed of a dynamic inverter circuit 102. That is, the phase of the input signal D is inverted in response to the clock signal CK.

Current paths of the transistors M13, M14, and M15 constituting the first logic circuit 100 are sequentially formed in series between the first power supply terminal 10 and the second power supply terminal 12. . Each gate of the PMOS transistor M13 and the NMOS transistor M15 is connected to an input terminal 16, and the gate of the NMOS transistor M14 has a common connection point in which current paths of the transistors M11 and M12 are commonly connected. It is connected to (18). The transistors M13, M14 and M15 are composed of a dynamic inverter circuit 104. That is, the phase of the clock signal CK is inverted in response to the output signal of the dynamic inverter circuit 102.

Referring back to FIG. 3, current paths of the transistors M16, M17, and M18 constituting the second logic circuit 200 are connected between the first power supply terminal 10 and the second power supply terminal 12. Are formed sequentially in series. The gates of the PMOS transistor M16 and the NMOS transistor M17 are commonly connected where the output terminals 20 of the first logic circuit 100, that is, the current paths of the transistors M13 and M14 are connected in common. have. The gate of the NMOS transistor M18 is connected to the input terminal 16 to which the clock signal CK is applied. In addition, the places where the current paths of the transistors M16 and M17 are commonly connected are connected to an output terminal 22 for outputting the output signal QN.

Current paths of the transistors M19 and M20 constituting the second logic circuit 200 are sequentially formed in series between the first power supply terminal 10 and the second power supply terminal 12. Each gate of the PMOS transistor M19 and the NMOS transistor M20 is commonly connected to the output terminal 22. In addition, the places where the current paths of the transistors M19 and M20 are commonly connected are connected to an output terminal 24 for outputting the output signal Q.

The operation of the D flip-flop of the present invention is described below. First, assume that the clock signal CK is 0V and the data input signal D is 0V. The PMOS transistor M11 is turned on by the data input signal D, and the PMOS transistor M10 is turned on by the clock signal CK. Accordingly, the common connection point 18 is charged to the power supply voltage VDD through the transistors M10 and M11. The NMOS transistor M14 is turned on by the common connection point 18 charged to the power supply voltage VDD, and the PMOS transistor M13 is also turned on by the clock signal CK. However, since the NMOS transistor M15 controlled by the clock signal CK is turned off, the output terminal 20 is charged to the power supply voltage VDD through the PMOS transistor M13 even if the NMOS transistor 14 is turned on. Aji.

At the same time, the output terminals 24 and 22 for the first output signal Q and its complementary second output signal QN are connected to each other even though the output terminal 20 is charged with the power supply voltage VDD. Nevertheless, the NMOS transistor M18 is turned off because the clock signal CK is maintained at the level of the ground potential VSS. As a result, no input signal is transmitted to the output terminals 22 and 24. This state is as if data is latched to the master stage 100 when the clock signal CK is 0V, as in a typical flip-flop with a master-slave structure.

Next, when the clock signal CK is applied at 5V, the PMOS transistor M10 is turned off so that the connection point 18 is in the previous state where the level of the clock signal was applied at 0V regardless of the voltage level of the input signal D. 5V, that is, the level of the power supply voltage (VDD) is maintained. Then, the PMOS transistor M13 is turned off and the NMOS transistors M14 and M15 are turned on. As a result, the output terminal 20 is discharged to 0 V, that is, the ground potential VSS at the power supply voltage VDD. Accordingly, the PMOS transistor M16 is turned on, the output terminal 22 is charged to the power supply voltage VDD and the output terminal 24 is charged to the ground potential VSS, respectively.

This operation principle is the same as that of the conventional D flip-flop. In addition, while the conventional D flip-flop latches or outputs an input signal by a dual phase of the clock signal CK and its complementary clock signal CKB, the D flip-flop according to the present invention uses a single phase ( single phase) A dynamic circuit structure that operates only with a clock signal and can operate even when a high-speed input signal is applied to a flip-flop.

As described above, it is possible to implement high-density flip-flops by enabling high-speed operation and reducing the chip area by about 30% compared to the chip area occupied by the conventional flip-flop.

Claims (12)

Having a first input terminal and a first output terminal, maintaining the first output terminal at a second level voltage while the clock signal is maintained at a first level voltage regardless of the voltage level of the first input terminal; and First logic means for maintaining said first output terminal at the same level as an input signal input through said first input terminal while a clock signal is maintained at a second level voltage; A first output connected to the first output terminal, inactive while the clock signal is held at a first level voltage, and having a same level as the first output terminal while the clock signal is held at a second level voltage; D flip-flops comprising second logic means for outputting a signal and a complementary second output signal thereof. The method of claim 1, And said first level voltage is the level of ground potential and said second level voltage is the level of a power supply voltage. The method of claim 2, The first logic means includes a first power supply terminal for receiving the power supply voltage; A second power supply terminal for receiving the ground potential; A second input terminal for receiving the clock signal; A first transistor having a current path and a gate, said gate coupled to said first input terminal; A second transistor having a current path and a gate, the gate being connected to the second input terminal; A third transistor having a current path and a gate, the gate being connected to the first input terminal; Each current path of the first, second and third transistors is sequentially formed in series between the first power supply terminal and the second power supply terminal; A fourth transistor having a current path and a gate, the gate being connected to the second input terminal; A fifth transistor having a current path and a gate, wherein the gate is connected to a common connection point at which the current paths of the second and third transistors are commonly connected; A sixth transistor having a current path and a gate, said gate connected to said second input terminal, wherein current paths of said fourth, fifth, and sixth transistors comprise said first power supply terminal and said second power supply; A D flip-flop formed sequentially in series between the terminals and wherein current paths of the fourth and fifth transistors are commonly connected to the first output terminal. The method of claim 3, wherein And the first, second and fourth transistors are composed of P-channel MOS transistors, and the third, fifth and sixth transistors are composed of N-channel MOS transistors. The method of claim 3, wherein The second logic means includes a second output terminal for outputting the first output signal; A third output terminal for outputting the second output signal; A seventh transistor having a current path formed between the first power supply terminal and the third output terminal and a gate connected to the first output terminal; An eighth transistor having a current path and a gate, wherein the gate is connected to the first output terminal; A ninth transistor having a current path and a gate, the gate of which is connected to the second input terminal; Current paths of the eighth and ninth transistors are sequentially formed in series between the third output terminal and the second power supply terminal; A tenth transistor having a current path formed between the first power supply terminal and the second output terminal and a gate connected to the third output terminal; And an eleventh transistor having a current path formed between the second output terminal and the second power supply terminal and a gate connected to the third output terminal. The method of claim 5, And the seventh and tenth transistors are composed of P-channel MOS transistors, and the eighth, ninth and eleventh transistors are composed of N-channel MOS transistors. For a D flip-flop that includes a master and slave stage: The master stage, A first dynamic inverter for inverting the phase of the input signal in response to the dynamic drive signal; And a second dynamic inverter for inverting the phase of the dynamic drive signal in response to an output signal of the first dynamic inverter. The method of claim 7, wherein And the dynamic driving signal is a clock signal. The method of claim 7, wherein The first dynamic inverter includes: a first power supply terminal for receiving a power supply voltage; A second power supply terminal for receiving a ground potential; A first input terminal for receiving the input signal; A second input terminal for receiving the dynamic drive signal; A first transistor having a current path and a gate, said gate coupled to said first input terminal; A second transistor having a current path and a gate, the gate being connected to the second input terminal; A third transistor having a current path and a gate, the gate being connected to the first input terminal; Each current path of the first, second and third transistors is sequentially formed in series between the first power supply terminal and the second power supply terminal. The method of claim 9, The second dynamic inverter has a current path and a gate, and a fourth transistor having the gate connected to the second input terminal; A fifth transistor having a current path and a gate, wherein the gate is connected to a common connection point at which the current paths of the second and third transistors are commonly connected; A sixth transistor having a current path and a gate, said gate connected to said second input terminal, wherein current paths of said fourth, fifth, and sixth transistors comprise said first power supply terminal and said second power supply; D flip-flop, characterized in that sequentially formed between the terminals and the current paths of the fourth and fifth transistors are commonly connected to the first output terminal. The method of claim 10, And the first, second and fourth transistors are composed of P-channel MOS transistors, and the third, fifth and sixth transistors are composed of N-channel MOS transistors. The method of claim 7, wherein And the first level voltage is the level of the ground potential, and the second level voltage is the level of the power supply voltage.