KR19990024550A - Etching method for wiring formation of semiconductor device - Google Patents
Etching method for wiring formation of semiconductor device Download PDFInfo
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- KR19990024550A KR19990024550A KR1019970045723A KR19970045723A KR19990024550A KR 19990024550 A KR19990024550 A KR 19990024550A KR 1019970045723 A KR1019970045723 A KR 1019970045723A KR 19970045723 A KR19970045723 A KR 19970045723A KR 19990024550 A KR19990024550 A KR 19990024550A
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- 238000005530 etching Methods 0.000 title claims abstract description 57
- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 230000015572 biosynthetic process Effects 0.000 title claims 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 78
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 42
- 239000000463 material Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 2
- 239000007789 gas Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 반도체소자의 배선형성을 위한 식각방법에 관한 것으로, 종래에는 반사방지막을 식각하기 위한 하드마스크로 사용되는 실리콘산화막의 식각과 반사방지막의 식각이 2단계의 공정을 통해 이루어짐으로써, 공정이 복잡한 문제점과, 반사방지막의 식각시 실리콘산화막에 손실영역이 발생하는 문제점이 있었다. 이와같은 문제점을 감안한 본 발명은 반도체소자가 형성된 기판의 상부에 순차적으로 배선물질 및 SiON:H막을 형성하고, 그 SiON:H막의 상부전면에 실리콘산화막을 증착한 후, 감광막을 이용한 사진식각공정을 통해 동일한 식각조건으로 실리콘산화막과 SiON:H막의 일부를 식각하는 단계와; 상기 감광막을 제거하는 단계로 이루어지는 반도체소자의 배선형성을 위한 식각방법을 제공하여 단일식각공정을 통해 하드마스크로 사용되는 실리콘산화막의 손실영역이 없이 0.015㎛ 이하의 임계치수를 갖는 배선을 형성할 수 있고, 아울러 실리콘산화막과 SiON:H막이 88°이상의 프로파일(profile)을 갖는 식각형상을 구현할 수 있는 효과가 있다.The present invention relates to an etching method for forming a wiring of a semiconductor device, and the etching of the silicon oxide film and the anti-reflection film, which are conventionally used as a hard mask for etching the anti-reflection film, are performed through a two-step process. There was a complicated problem and a loss area in the silicon oxide film during etching of the anti-reflection film. In view of the above problems, the present invention sequentially forms a wiring material and a SiON: H film on the substrate on which the semiconductor device is formed, deposits a silicon oxide film on the upper surface of the SiON: H film, and then performs a photolithography process using a photosensitive film. Etching a portion of the silicon oxide film and the SiON: H film under the same etching conditions; By providing an etching method for forming the wiring of the semiconductor device comprising the step of removing the photosensitive film can be formed a wiring having a critical dimension of 0.015㎛ or less without a loss region of the silicon oxide film used as a hard mask through a single etching process In addition, there is an effect that the silicon oxide film and the SiON: H film can implement an etching shape having a profile of 88 ° or more.
Description
본 발명은 반도체소자의 배선형성을 위한 식각방법에 관한 것으로, 특히 게이트배선 및 비트라인형성을 위해 하드마스크(hard mask)로서 화학기상증착법을 통해 증착되는 실리콘산화막과 반사방지막으로서 플라즈마 화학기상증착법을 통해 증착되는 SiON:H막의 적층구조를 식각하기에 적당하도록 한 반도체소자의 배선형성을 위한 식각방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an etching method for forming wirings of a semiconductor device. In particular, a plasma chemical vapor deposition method is used as a silicon oxide film and an anti-reflection film deposited as a hard mask to form a gate mask and a bit line. The present invention relates to an etching method for forming a wiring of a semiconductor device suitable for etching a stacked structure of a SiON: H film deposited through.
일반적으로, 금속배선형성을 위해 하드마스크로 사용되는 실리콘산화막 및 실리콘질화막에 대한 건식식각기술은 확립되어 있으나, 그 실리콘산화막 및 텅스텐 실리사이드등의 금속배선 사이에 반사방지막으로서 플라즈마(plasma) 화학기상증착법을 통해 증착되는 SiON:H(hydrogenated silicon oxynitride, Si-enriched silicon oxynitride)막의 적층구조에 대한 식각은 2단계 식각공정을 사용하며, 그 SiON:H막은 실리콘산화막의 상부 또는 하부에 위치하지만, 설명의 편의를 위하여 후자의 경우로 한정하여 설명한다. 이와같은 종래 반도체소자의 배선형성을 위한 식각방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In general, dry etching techniques have been established for silicon oxide films and silicon nitride films used as hard masks for forming metal interconnections, but plasma chemical vapor deposition is used as an anti-reflection film between the metal oxide films and tungsten silicides. The etching of the stacked structure of the hydrogenated silicon oxynitride (SiON: H) film deposited through the SiON: H film is performed using a two-step etching process, and the SiON: H film is located above or below the silicon oxide film. For convenience, only the latter case will be described. Such an etching method for forming a wiring of a conventional semiconductor device will be described in detail with reference to the accompanying drawings.
도1a 내지 도1c는 종래 반도체소자의 배선형성을 위한 식각방법을 보인 수순단면도로서, 이에 도시한 바와같이 반도체소자가 형성된 기판(미도시)의 상부에 배선물질(1)을 형성하고, 그 배선물질(1)의 상부에 SiON:H막(2)을 증착한 후, 그 SiON:H막(2)의 상부전면에 실리콘산화막(3)을 증착하고, 감광막(PR1)을 이용한 사진식각공정을 통해 실리콘산화막(3)을 부분적으로 식각하는 단계(도1a)와; 그 감광막(PR1)을 제거한 후, 세정하는 단계(도1b)와; 상기 실리콘산화막(3)을 하드마스크로 이용하여 SiON:H막(2)을 식각 및 세정하는 단계(도1c)로 이루어지며, 미설명부호 '4'는 SiON:H막(2)을 식각할 때, 발생하는 실리콘산화막(3)의 손실(loss)영역이다. 이하, 종래 반도체소자의 배선형성을 위한 식각방법을 좀더 상세히 설명한다.1A to 1C are cross-sectional views showing an etching method for forming a wiring of a semiconductor device according to the related art. The wiring material 1 is formed on a substrate (not shown) on which a semiconductor device is formed, as shown in FIG. After depositing a SiON: H film (2) on top of the material (1), a silicon oxide film (3) is deposited on the upper surface of the SiON: H film (2), a photolithography process using a photosensitive film (PR1) Partially etching the silicon oxide film 3 (FIG. 1A); Removing the photoresist film PR1 and then washing it (Fig. 1B); Etching and cleaning the SiON: H film 2 using the silicon oxide film 3 as a hard mask (FIG. 1C). At this time, a loss region of the silicon oxide film 3 is generated. Hereinafter, an etching method for forming a wiring of a conventional semiconductor device will be described in more detail.
먼저, 도1a에 도시한 바와같이 반도체소자가 형성된 기판(미도시)의 상부에 배선물질(1)을 형성하고, 그 배선물질(1)의 상부에 SiON:H막(2)을 증착한 후, 그 SiON:H막(2)의 상부전면에 실리콘산화막(3)을 증착하고, 감광막(PR1)을 도포한 후, 사진식각공정을 통해 실리콘산화막(3)을 부분적으로 식각한다. 이때, SiON:H막(2)은 반사방지막으로 사용되며, 플라즈마 화학기상증착법을 통해 증착되고, 실리콘산화막(3)은 SiON:H막(2)의 식각을 위한 하드마스크로 사용되도록 SiON:H막(2)의 상부에 소정거리 이격되어 형성된다.First, as shown in FIG. 1A, a wiring material 1 is formed on a substrate (not shown) on which a semiconductor device is formed, and a SiON: H film 2 is deposited on the wiring material 1. The silicon oxide film 3 is deposited on the upper surface of the SiON: H film 2, the photoresist film PR1 is applied, and the silicon oxide film 3 is partially etched through a photolithography process. In this case, the SiON: H film 2 is used as an anti-reflection film, and is deposited through plasma chemical vapor deposition, and the silicon oxide film 3 is used as a hard mask for etching the SiON: H film 2. It is formed above the film 2 at a predetermined distance apart.
그리고, 도1b에 도시한 바와같이 그 감광막(PR1)을 제거한 후, 세정한다.Then, as shown in Fig. 1B, the photoresist film PR1 is removed and then washed.
그리고, 도1c에 도시한 바와같이 상기 실리콘산화막(3)을 하드마스크로 이용하여 SiON:H막(2)을 식각 및 세정한다. 따라서, 실리콘산화막(3)의 하부를 제외한 SiON:H막(2)이 식각되며, 실리콘산화막(3)도 손실영역(4)이 발생한다.As shown in FIG. 1C, the SiON: H film 2 is etched and cleaned using the silicon oxide film 3 as a hard mask. Accordingly, the SiON: H film 2 except for the lower portion of the silicon oxide film 3 is etched, and the loss region 4 also occurs in the silicon oxide film 3.
그러나, 상기한 바와같은 종래 반도체소자의 배선형성을 위한 식각방법은 반사방지막을 식각하기 위한 하드마스크로 사용되는 실리콘산화막의 식각과 반사방지막의 식각이 2단계의 공정을 통해 이루어짐으로써, 공정이 복잡한 문제점과, 반사방지막의 식각시 실리콘산화막에 손실영역이 발생하는 문제점이 있었다.However, in the etching method for forming a wiring of a conventional semiconductor device as described above, the etching of the silicon oxide film and the anti-reflection film used as a hard mask for etching the anti-reflection film are performed through a two-step process. There was a problem, and a loss region occurred in the silicon oxide film during etching of the anti-reflection film.
본 발명은 상기한 바와같은 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 단일식각공정을 통해 하드마스크로 사용되는 실리콘산화막과 반사방지막을 식각함과 아울러 실리콘산화막의 손실영역을 없앨 수 있는 반도체소자의 배선형성을 위한 식각방법을 제공하는데 있다.The present invention was devised to solve the above problems, and an object of the present invention is to etch the silicon oxide film and the anti-reflection film used as a hard mask through a single etching process and to eliminate the loss areas of the silicon oxide film. An etching method for forming a wiring of a semiconductor device is provided.
도1은 종래 반도체소자의 배선형성을 위한 식각방법을 보인 수순단면도.1 is a cross-sectional view showing an etching method for forming a wiring of a conventional semiconductor device.
도2는 본 발명에 의한 반도체소자의 배선형성을 위한 식각방법을 보인 수순단면도.Figure 2 is a cross-sectional view showing an etching method for forming a wiring of the semiconductor device according to the present invention.
도3은 도2에 있어서, 임계치수 바이어스, 실리콘산화막의 식각율, 그리고 감광막과의 선택비를 보인 그래프도.FIG. 3 is a graph showing the threshold bias, the etching rate of the silicon oxide film, and the selectivity with the photosensitive film in FIG.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of drawings
1 : 배선물질 2 : SiON:H막1: wiring material 2: SiON: H film
3 : 실리콘산화막 PR1 : 감광막3: silicon oxide film PR1: photosensitive film
상기한 바와같은 본 발명의 목적은 반도체소자가 형성된 기판의 상부에 순차적으로 배선물질 및 SiON:H막을 형성하고, 그 SiON:H막의 상부전면에 실리콘산화막을 증착한 후, 동일한 식각조건으로 실리콘산화막과 SiON:H막의 일부를 식각하는 단계와; 상기 감광막을 제거하는 단계로 이루어짐으로써 달성되는 것으로, 본 발명에 의한 반도체소자의 배선형성을 위한 식각방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.As described above, an object of the present invention is to sequentially form a wiring material and a SiON: H film on a substrate on which a semiconductor device is formed, deposit a silicon oxide film on the entire surface of the SiON: H film, and then deposit a silicon oxide film under the same etching conditions. Etching a portion of the SiON: H film; It is achieved by the step of removing the photosensitive film, it will be described in detail with reference to the accompanying drawings an etching method for forming the wiring of the semiconductor device according to the present invention.
도2a 내지 도2b는 본 발명에 의한 반도체소자의 배선형성을 위한 식각방법을 보인 수순단면도로서, 이에 도시한 바와같이 반도체소자가 형성된 기판(미도시)의 상부에 순차적으로 배선물질(1) 및 SiON:H막(2)을 형성하고, 그 SiON:H막(2)의 상부전면에 실리콘산화막(3)을 증착한 후, 감광막(PR1)을 이용한 사진식각공정을 통해 동일한 식각조건으로 실리콘산화막(3)과 SiON:H막(2)의 일부를 식각하는 단계(도2a)와; 상기 감광막(PR1)을 제거하는 단계(도2b)로 이루어진다. 이하, 본 발명에 의한 반도체소자의 배선형성을 위한 식각방법을 좀더 상세히 설명한다.2A to 2B are cross-sectional views showing an etching method for forming a wiring of a semiconductor device according to the present invention. As shown therein, the wiring material 1 and the semiconductor material are sequentially formed on a substrate (not shown). After the SiON: H film 2 is formed, the silicon oxide film 3 is deposited on the upper surface of the SiON: H film 2, and the silicon oxide film is subjected to the same etching conditions through a photolithography process using the photosensitive film PR1. (3) and etching a part of the SiON: H film 2 (FIG. 2A); Removing the photoresist film PR1 is performed (FIG. 2B). Hereinafter, an etching method for forming a wiring of a semiconductor device according to the present invention will be described in more detail.
먼저, 도2a에 도시한 바와같이 반도체소자가 형성된 기판(미도시)의 상부에 순차적으로 배선물질(1) 및 SiON:H막(2)을 형성하고, 그 SiON:H막(2)의 상부전면에 실리콘산화막(3)을 증착한 후, 감광막(PR1)을 이용한 사진식각공정을 통해 동일한 식각조건으로 실리콘산화막(3)과 SiON:H막(2)의 일부를 식각하고, 도2b에 도시한 바와같이 감광막(PR1)을 제거한다.First, as shown in FIG. 2A, the wiring material 1 and the SiON: H film 2 are sequentially formed on the substrate (not shown) on which the semiconductor element is formed, and the upper portion of the SiON: H film 2 is formed. After the silicon oxide film 3 is deposited on the entire surface, the silicon oxide film 3 and a part of the SiON: H film 2 are etched under the same etching conditions through a photolithography process using the photoresist film PR1, as shown in FIG. 2B. As described above, the photosensitive film PR1 is removed.
이때, SiON:H막(2)은 비정질실리콘, 실리콘산화물, 실리콘질화물, 수소 등의 혼합물로 구성되어 있으므로, 이를 식각하기 위해 비정질실리콘, 실리콘산화막, 실리콘질화막에 대하여 1:0.7∼1.3:0.8∼1.2의 식각선택비를 갖는 공정조건이 필요하다.At this time, since the SiON: H film 2 is composed of a mixture of amorphous silicon, silicon oxide, silicon nitride, hydrogen, etc., it is 1: 0.7 to 1.3: 0.8 to amorphous silicon, silicon oxide film, and silicon nitride film to etch it. Process conditions with an etching selectivity of 1.2 are required.
그리고, 식각가스는 상기한 공정조건에서 큰폭의 C:F비를 갖는 CF4,CHF3,C2F6의 혼합가스에 방전의 안정화를 목적으로 Ar,N2의 혼합가스를 첨가하고, 감광막(PR1)과의 식각선택비를 향상하기 위하여 CH2F2,C4F8의 혼합가스를 첨가하여 사용한다.In the etching gas, a mixed gas of Ar, N 2 is added to the mixed gas of CF 4 , CHF 3 , C 2 F 6 having a large C: F ratio under the above-described process conditions for the purpose of stabilizing discharge, In order to improve the etching selectivity with (PR1), a mixed gas of CH 2 F 2 and C 4 F 8 is used.
그리고, 식각장비는 고밀도 플라즈마장비인 헬리콘(helicon)형 식각장비를 기판온도 0℃, 압력 3mT∼6mT, 소스전력 1000W∼2000W, 바이어스전력 300W∼700W의 조건으로 사용한다.In addition, the etching equipment uses a helicon-type etching equipment, which is a high-density plasma equipment, under the conditions of a substrate temperature of 0 ° C., a pressure of 3mT to 6mT, a source power of 1000W to 2000W, and a bias power of 300W to 700W.
한편, CF4는 5SCCM∼25SCCM, CHF3은 75SCCM∼95SCCM, C2F6은 10SCCM∼30SCCM, N2는 80SCCM∼120SCCM, 그리고 CH2F2및 C4F8은 5SCCM∼15SCCM의 유량을 사용한다.CF 4 uses 5SCCM to 25SCCM, CHF 3 uses 75SCCM to 95SCCM, C 2 F 6 uses 10SCCM to 30SCCM, N 2 uses 80SCCM to 120SCCM, and CH 2 F 2 and C 4 F 8 uses 5SCCM to 15SCCM. do.
그리고, 도3a 내지 도3d는 상기한 바와같은 본 발명에 의한 공정조건에 따른 임계치수(critical dimension:CD) 바이어스, 실리콘산화막(3)의 식각율, 그리고 감광막(PR1)과의 선택비를 도시하였다. 여기서 임계치수 바이어스란 마스크와 감광막의 선폭의 차이를 나타내며, 따라서 단위는 ㎛이다.3A to 3D show the critical dimension (CD) bias, the etching rate of the silicon oxide film 3, and the selectivity with the photoresist film PR1 according to the process conditions according to the present invention as described above. It was. Here, the critical dimension bias represents the difference in the line widths of the mask and the photosensitive film, and thus the unit is µm.
상기한 바와같은 본 발명에 의한 반도체소자의 배선형성을 위한 식각방법은 단일식각공정을 통해 하드마스크로 사용되는 실리콘산화막의 손실영역이 없이 0.015㎛ 이하의 임계치수를 갖는 배선을 형성할 수 있고, 아울러 실리콘산화막과 SiON:H막이 88°이상의 프로파일(profile)을 갖는 식각형상을 구현할 수 있는 효과가 있다.According to the etching method for forming a wiring of a semiconductor device according to the present invention as described above, a wiring having a critical dimension of 0.015 μm or less can be formed without a loss region of a silicon oxide film used as a hard mask through a single etching process. In addition, there is an effect that the silicon oxide film and the SiON: H film can achieve an etching shape having a profile of 88 ° or more.
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