KR19990023296U - VSI's data check circuit - Google Patents

Abstract

The present invention relates to a data check circuit of VSI, and conventionally, in such a system, when receiving character broadcasting data transmitted from a broadcasting station and slicing data from a video signal, a synchronization signal or timing control means is used. This is a problem because it causes errors depending on the received field strength of the video signal.

The present invention provides a buffer 11 for buffering a video signal, and a data slicer for slicing data in a vertical blanking section and generating a data clock so that the system can improve such a conventional problem. (12) and the data clock generator 13, the synchronous separator 14 for separating the synchronous signal from the video signal, the line detector 15 for connecting the output of the synchronous separator 14 and detecting the data line, To provide a data check circuit of VSI including a lock 16 and a linefield controller 18, a decoder 20 and a memory 19, a system microcomputer 17 and a linefield controller 18, and the like. have.

According to the present invention, the error checking data is added to the broadcasting system data signal, and the receiving system checks the data, thereby enabling more reliable data extraction.

Description

VSI's data check circuit

The present invention relates to the data check circuit of VSI with the character broadcasting reception function, which is particularly effective when the character broadcasting data contained in the video signal is less affected by the broadcasting reception state. Receiving This system ensures the accuracy of data extraction.

The character broadcasting of our country is designed to insert various character information or KBIPS information of our own format into the back porch side of the horizontal synchronization section of the video signal, so that it can be used in various ways.

For example, the KB PS signal, which is program information for reservation recording, is information such as a program provided by the broadcasting station, which is formed as shown in FIG. 3, and includes a clock and byte synchronization unit, a data header unit, a data block, and the like. One word is in the form of 8 bits (1 byte).

In addition, the contents included in the KBPS data include current time data, start time of one week program, length, title, day map, corresponding code, broadcast station name, currently broadcasted code name, and the like.

In this type of KB signal, the prior art which is relatively related to the present invention is known to be able to process a simple reservation recording in the VSI system using the KB PS signal, so-called K (K) An example of a VSI system used as a reservation recording means is shown in FIG. 1.

Here, the microcomputer 31 for controlling the VSI system, the servo circuit 32 for driving control of the motor on the system deck side, the remote control unit 33a and the set side wirelessly connected to the remote control transmitter 33c And a timer circuit 33 to which the key portion 33b is connected, and an audio circuit 35 for processing a reproduction or audio recording signal in the system.

In addition, the system includes a video circuit 37 for providing a recording signal to the tape side or processing a reproduction video signal from an RF signal provided from the tuner and the IF unit 38, and an audio signal during double speed reproduction on the system deck side. DMS (36) to control to provide a steady state, the K-PS unit (34) for decoding character data, such as KB PS, and the signal received from the antenna is tuned to the signal of the intermediate frequency And a tuner and eye part 38 to be generated, and a power circuit 39 for supplying system power.

On the other hand, the KB PS part 34 is shown in more detail as shown in FIG.

In this case, the first switch 34b for connecting the antenna side signals provided from the tuner and the IF unit 38 to the buffers 34c and 34j, and the RF signals provided from the buffer 34c side are supplied with the synchronization signal. And a data slicer 34e for detecting KBP data from the composite synchronous signal provided from the synchronous separation Ish 34d.

In addition, the system receives the KBPS data, decodes the data contents, and provides an On Screen Display (OSD) signal to the second switch 34k, and the KBPS decoder ( The program ROM 34g, the system RAM 34f, the character font 34h, and the like which store various program contents processed by 34a) are included.

In addition, the system includes a switch IC 34L for providing an OSD signal provided from the second switch 34k to a D / A (Digital / Analog) converter or providing a signal to a video output terminal of the system. An AD converter 34i for converting an analog signal provided from the ice 34L into a digital signal and providing it to the KB PS decoder 34a, a low-pass filter 34m of 1.9 MHz connected to an external caption section 4, and the like. Consists of the configuration, including.

In such a conventional system, when KBPS or text data is inserted into a back porch section of a video signal as shown in FIG. 3, the video is decoded by a decoder of the system and used as a video program or program reservation information with a caption. .

In the above system, when extracting text data from an input video signal, the sync signal is separated from the complex sync signal, and the text data is extracted in this sync signal section.

However, in such a prior art, since the vertical synchronization period tends to collapse in a state in which video reception is poor, such as a video signal of a broadcast reception system in a weak electric field, there is a problem in obtaining more accurate data.

An object of the present invention is to enable more reliable data extraction by inserting error check data into the data such as text broadcasting provided by the broadcasting station and checking it in the reception system to improve the above problems.

The present invention provides a buffer for buffering an input video signal in a system so as to achieve the above object, and a data slicer and a data clock generator for slicing data in a vertical blanking section and generating a data clock by connecting to the output of the buffer. A synchronous separator for separating the synchronous signal from the video signal, a line detector connected to the output of the synchronous separator to detect a data line, a V-lock unit and a linefield controller, a decoder and a memory, a system microcomputer and a linefield controller, etc. It is characterized by the data check circuit of VSI including.

Hereinafter, more specific features of the present invention will be understood by describing the same in detail with the accompanying drawings.

1 is a system circuit block diagram of a VCR (Video Cassette Recorder) having a general character broadcasting reception function.

2 is a reference diagram specifically showing the character broadcasting decoder in FIG.

Figure 3 is a reference diagram showing a conventional broadcast station side KB PS transmission signal shape

4 is a system circuit block diagram of the present invention.

** Explanation of symbols on main parts of the drawing **

11.Buffer 12. Data Slicer

13. Data Clock Generator 14. Synchronous Separator

15. Line detector 16. V-lock part

17. Microcomputer 18. Linefield Controller

19. Memory 20. Decoder

The data check circuit according to the present invention is shown as shown in FIG.

Here, a buffer 11 for buffering a video signal, a data slicer 12 and a data clock generator 13 for slicing data in the vertical blanking section and generating a data clock, which are connected to the output of the buffer 11, and a video signal. A synchronous separator 14 for separating the synchronous signal from the synchronous signal, and a line detector 15 for detecting a data line following the output of the synchronous separator 14.

The system also includes a V-lock unit 16 for receiving a vertical synchronous signal separated from the synchronous separator 14, and a V-lock unit 16 for locking the vertical synchronous signal, and a data line (i) and data field (DF) signal. A linefield controller 18 for controlling the linefield, received from 16, a decoder 20 and system memory 19 for decoding data carried in the back porch section of the video signal, and a system microcomputer 17 ) And line field controller 18, and the like.

The present invention of such a configuration amplifies the video signal input through the tuner, the eye part, etc. in the buffer 11 as shown in FIG. 4 and provides it to the data slicer 12 and the sync separator 14 again.

The data slicer 12 separates the data carried in the vertical synchronization section of the video signal and provides it to the data clock generator 13.

The data slicer 12 separates the data based on the vertical synchronization signal provided by the sync separator 14 when separating the data, and the data clock generator 13 separates the data clock from the data separated by the data slicer 12. Is generated to be provided to the decoder 20.

In addition, the line detector 150 connected to the synchronous separator 14 detects the data line signal and provides the data line signal to the decoder 20. The V-lock unit 16 locks the vertical synchronization signal, thereby providing the data field and the data line signal. It is provided to the line field controller 18.

The decoder 20 refers to input signals provided from the data clock generator 13, the line detector 15, and the line field controller 18, and includes 13 bits of information data which are planted in the 10H to 16H sections of the vertical synchronization section. After extracting the check bits of 3 bits and providing them to the microcomputer 17, the microcomputer 17 compares the check bits pre-stored in the memory 19 with the check bits inserted in the video signal at the transmitter side and receives the received check bits. You can check whether the signal status is properly received.

For example, the binary 3 bit information planted by the broadcast transmitter may be divided into eight types. When the data of the eight types and the data extracted by the decoder 20 are examined, the receiver does not fit the format. When the data is extracted, it is confirmed that there is an error in the data, and the data is not stored in the memory, and the data can be stored in the memory 19 only when this check parity is matched. Memory can be guaranteed.

The microcomputer 17 also provides a select enable signal SE, a select clear signal SC, a select data signal SD, a busy signal BY, and the like, when the V lock unit 16 is driven. It will perform the action.

The present invention, when extracting the character broadcast data from the VSI system having a character broadcast reception function in the system by referring to the check bit inserted into the video signal by the broadcast system to check the error of the data in the receiver system It is possible to ensure the accuracy of the reception operation.

Claims (1)

In a VSI system having a character broadcasting reception function, the system includes a buffer 11 for buffering a video signal, and a data slicer for slicing data in a vertical blanking section and generating a data clock by connecting to the output of the buffer 11. (12) and the data clock generator 13, the synchronous separator 14 for separating the synchronous signal from the video signal, the line detector 15 for connecting the output of the synchronous separator 14 and detecting the data line, The lock unit 16 and the line field controller 18, the decoder 20 for decoding the data including the check bit in the received data, and the check bit in the data information provided from the system decoder 20, check the authenticity of the data. VSI's data check circuit characterized by a configuration including a microcomputer 17 to verify, a linefield controller 18 and the like.