KR19990021166A - ROM device based on NAND structure and amorphous silicon and manufacturing method thereof - Google Patents

Abstract

The present invention provides a ROM device based on NAND-structure and amorphous-silicon. This ROM device is of a type that includes an array of MOSFET memory cells, configured based on the SOI structure to separate the substrate and the source / drain regions to prevent leakage current. In addition, the SOI structure increases the operating voltage by preventing a breakdown voltage from occurring at the diode junction between the source / drain region and the substrate. In ROM devices, the source / drain regions for MOSFET memory cells are formed of intrinsic amorphous-silicon instead of high-doped polysilicon to greatly simplify the fabrication process of the ROM device.

Description

ROM device based on NAND structure and amorphous silicon and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, in particular a metal oxide semiconductor field effect transistor (hereinafter referred to as a MOSFET) in which a source / drain region is formed of amorphous silicon and manufactured based on a silicon-on-insulator (SOI) structure. The present invention relates to a semiconductor read-only memory (ROM; hereinafter referred to as ROM) device based on amorphous silicon having a NAND structure of a type included in an array.

ROM is widely used in computers and microprocessor systems to permanently store information, including programs and data that are used repeatedly, such as, for example, the BIOS (Basic Input / Output System). It is a nonvolatile semiconductor memory used. ROM requires a very complicated and time-consuming manufacturing process, and expensive manufacturing equipment. Thus, the binary code stored permanently in the ROM is always first defined by the consumer and provided to the factory to be programmed into the ROM.

Most ROMs differ only in the binary code stored therein, and the rest of the structure is the same as that of the semiconductor. Thus, the ROM device can only be manufactured up to the stage at which data programming is possible, and the semi-manufactured product is listed in the waiting list ordered by the consumer. Thus, the consumer supplies the factory with data to be stored in a semi-manufactured ROM using a process called a mask-programming process. Such a procedure is currently used as a standard method in the semiconductor industry for manufacturing ROMs.

In most conventional ROMs, MOSFETs are used as memory cells to permanently store binary data. In the mask-programming process stage, impurities are doped in the selected channel region to provide memory cells with different threshold voltage levels, meaning that different values of binary code data have been stored. Whether a bit of zero or one binary bits is set to be stored in one MOSFET memory cell depends on whether the channel region associated with it is doped with impurities. If one channel region is filled with impurities, the associated MOSFET memory cell is set to a low threshold voltage so that the on-state, meaning that the first binary digit, i.e., 0, is stored, is permanently set in the MOSFET memory cell. Or the MOSFET memory cell associated therewith is set to a high threshold voltage such that a second binary digit, i.e., an off-state meaning that 1 is stored, is permanently set in the MOSFET memory cell.

1A-1C show a typical ROM device, where FIG. 1A is a plan view of the ROM device, FIG. 1B is a cross-sectional view taken along the IB-IB line of the ROM device of FIG. 1A, and FIG. 1C is a ROM of FIG. 1A. Sectional view taken along the IC-IC line of the device.

As shown in Figs. 1A to 1C, a typical ROM device is, for example, a plurality of parallel-spaced bit lines 11 and a plurality of word lines (parallel-spaced across the bit lines 11). 13) includes a semiconductor substrate such as a formed p-type silicon substrate. The word line 13 is insulated from the bit line by the oxide film 12. This ROM device comprises an array of MOSFET memory cells 14 associated with one segmented word line 13 between a pair of bit lines 11 adjacent to each other.

As shown in Fig. 1C, in the method of manufacturing a conventional ROM device, the first step is to form a plurality of parallel-spaced diffusion regions to be provided as the bit lines 11, for example arsenic (As). Is an ion-implantation process for doping an n-type impurity such as) to a selected region of the substrate 10. The gap region between the pair of bit lines 11 adjacent to each other is provided as the channel region 16. Subsequently, a thermal oxidation process is performed on the wafer so that the oxide film 12 is formed over the entire upper region of the wafer. Next, a conductive layer such as, for example, a high-doped polysilicon layer is formed on the wafer, and then selectively removed by a photographic and etching process. The remaining portion of the conductive layer is provided as a word line 13. This is the state in which the manufacture of the semi-manufactured product of the ROM device is complete.

In the mask-programming process, a mask film 15 is first formed on a wafer. This mask film 15 is pre-defined so that a plurality of contact windows are formed in accordance with a bit pattern of binary coded data permanently programmed into the ROM device. These contact windows expose the channel regions associated with a selected group of MOSFET memory cells of a ROM device that are permanently turned on. The covered MOSFET memory cell is intended to be permanently turned off. Subsequently, an ion implantation process is performed on the wafer so that the p-type impurities, such as, for example, boron (B), are doped to the channel regions exposed through the contact window of the mask film 15. In this state, a certain ion implantation process is completed.

In a finished ROM device, the doped channel regions are set to a low threshold voltage so that the associated MOSFET memory cell is permanently set in the MOSFET memory cell, meaning that the first binary digit, i.e., 0, is stored. . Or the MOSFET memory cell associated therewith is set to a high threshold voltage such that a second binary digit, i.e., an off-state meaning that 1 is stored, is permanently set in the MOSFET memory cell.

In the above ROM device, since the source / drain regions are formed in the substrate by ion implantation, the insulating state between the source / drain regions and the substrate is not good. Moreover, since diode junctions are used to insulate the source / drain regions from the substrate, the leakage current increases as the supply voltage increases. In addition, since the magnitude of the leakage current is proportional to the contact area between the source / drain region and the substrate, the operating voltage is limited to a small amount in order to prevent leakage of the current.

Accordingly, an object of the present invention is to provide a ROM device having an SOI structure such that a source / drain region and a substrate are insulated to prevent generation of leakage current.

Another object of the present invention is to provide a ROM device made of an SOI structure which can increase the operating voltage by preventing the occurrence of breakdown voltage at the diode junction between the source / drain region and the substrate.

Another object of the present invention is to provide a method of manufacturing such a ROM device.

Other advantages of the present invention will become apparent from the specific embodiments of the present invention.

In order to achieve the above object, the present invention provides a ROM device and a method of manufacturing the same. This ROM device includes an array of MOSFET memory cells based on NAND-structure and amorphous silicon.

The method for manufacturing a ROM device of the present invention includes a first step of preparing a semiconductor substrate and forming a first insulating layer on the substrate; A second step of forming an intrinsic amorphous silicon layer on the first insulating layer; Removing a selected portion of the intrinsic amorphous silicon layer to form a plurality of substantially parallel spaced apart diffusion regions serving as bit lines facing in a first direction; A fourth step of performing an ion implantation process on the diffusion region by doping the first semiconductor type impurities into the diffusion region to adjust the threshold voltage of the diffusion region to a predetermined level; A fifth step of forming one first sidewall spacer on each sidewall of the diffusion region; A sixth step of forming a second insulating layer on the exposed surface of the first insulating layer, the diffusion region, and the first sidewall spacer; A seventh step of forming a conductive layer on the second insulating layer; A gate region and a lower portion of the gate region defining positions for forming an array of memory cells, so as to form a plurality of substantially parallel spaced gate regions that are directed in a second direction and overlapping the bit lines, and serve as word lines An eighth step of removing selected portions of the conductive layer which are overlapped portions of the plurality of channel regions and the diffusion regions divided into a plurality of source / drain regions located between the channel regions; A ninth step of forming one second sidewall spacer on each sidewall of the gate region; Depositing a mask layer on exposed portions of the second insulating layer, the gate region and the second sidewall spacer, exposing the first position on the gate region to form a first group of memory cells selected to be permanently turned off; And selectively removing the mask layer portion while preventing the second position from being exposed on the gate region to form a second group of memory cells selected to be permanently turned on; In order to allow the doped channel region to be permanently turned off and the undoped channel region to be permanently turned on, an ion implantation process of doping an impurity of a second semiconductor type into the exposed channel region is performed. An eleventh step; Forming a third insulating layer to cover the exposed portions of the second insulating layer, the gate region, and the second sidewall spacer; A plurality of source / drain contact windows in which all source / drain regions are exposed so as to extend through the third and second insulating layers, and a gate contact window exposed at a selected number on the gate regions associated with the on-state memory cells; Forming a thirteenth step; And a fourteenth step of filling the source / drain contact window and the gate contact window with a conductive material to form a plurality of gate electrodes in the gate contact window and a plurality of source / drain electrodes in the source / drain contact window, respectively.

In addition, the ROM device of the present invention includes a semiconductor substrate; A first insulating layer formed on the substrate; A plurality of diffusion regions formed on the first insulating layer and substantially spaced apart in parallel in the first direction to serve as bit lines; First side wall spacers formed on each sidewall of the diffusion region; A second insulating layer covering the first insulating layer, the diffusion region, and the first sidewall spacer; A gate region and a plurality of channel regions located below the gate region and positioned between the channel regions facing in a second direction and provided as a portion overlapping the bit line, that is, a word line, to define an array of memory cells; A plurality of gate regions formed on the second insulating layer to be substantially spaced apart in parallel so as to be divided into a plurality of source / drain regions, wherein the first selected channel region group forms a first memory cell group to be permanently turned off An impurity is doped to form a second memory cell group such that the second selected channel region group is permanently turned on; Second sidewall spacers formed on each sidewall of the gate region; A plurality of source / drain contact windows formed on the second insulating layer and the gate region to expose all the source / drain regions on the diffusion region, and a selected number of positions on the gate region associated with the memory cell in the on state; A third insulating layer having a plurality of gate contact windows for exposing them; A plurality of source / drain electrodes formed in the source / drain contact window in the third insulating layer; And a plurality of gate electrodes formed on the gate contact window in the third insulating layer.

1A is a plan view of a conventional ROM device,

FIG. 1B is a cross-sectional view taken along the IB-IB line of the ROM device of FIG. 1A;

1C is a cross-sectional view taken along the IC-IC line of the ROM device of FIG. 1A;

2A to 2E are cross-sectional perspective views showing the steps involved in the method of manufacturing the ROM device based on the NAND structure and amorphous silicon of the present invention;

2F-2H are cross-sectional views taken along the lines I-I and II-II of FIG. 2E.

Explanation of symbols for main parts of the drawings

30 semiconductor substrate 32 first insulating layer

34: Intrinsic Amorphous Silicon Layer 40: First Side Wall Spacer

42: second insulating layer 44: conductive layer

46 polysilicon gate region 49 second side wall spacer

50 source / drain region 52 photosensitive film

2A-2H are cross-sectional views illustrating the steps involved in the method of the present invention for fabricating ROM devices based on NAND structures and amorphous silicon. In particular, ROM devices are of a type that include an array of MOSFET memory cells to permanently store binary data.

As shown in Fig. 2A, in a first step, a semiconductor substrate 30 of a first semiconductor type, for example a p-type silicon substrate, is prepared. Subsequently, a first insulating layer 32 such as, for example, a silicon oxide film or a silicon nitride film is formed on the substrate 30. Subsequently, a plasma enhanced chemical-vapor deposition (PECVD) process is performed on the wafer with SiH 4 at a temperature of 350 degrees such that the intrinsic amorphous-silicon layer 34 is formed on the first insulating layer 32.

As shown in FIG. 2B, in the second step, the intrinsic amorphous-silicon layer 34 is photographed and formed such that a plurality of substantially parallel and equally spaced amorphous silicon layers 36 are formed in the first direction. It is selectively removed by an etching process. Next, an ion-implantation process is performed on the wafer to dope the amorphous silicon of the amorphous-silicon layer 36 with impurities of the first semiconductor type, for example boron (B), to adjust the threshold voltage to a predetermined voltage. do. The amorphous-silicon layer 36 doped with the impurity then uses the same reference numeral, but denotes the name of the diffusion region.

As shown in FIG. 2C, in the third step, a plurality of first sidewall spacers 40 are formed, one for each sidewall of the diffusion region 36. These first sidewall spacers 40, for example, preferentially deposit a sidewall insulating layer such as a silicon oxide film or a silicon nitride film to a predetermined thickness with respect to the entire upper surface of the wafer, and the upper surface of the insulating layer 32 below. It can be formed by performing an anisotropic dry etching process on the sidewall insulating layer until it is exposed. At this time, the remaining portions of the sidewall insulating layer are provided as the first sidewall spacer 40 described above. Then, the second insulating layer 42 such as the silicon oxide film or the silicon nitride film, which is provided as the gate oxide film, is formed on the entire upper surface of the wafer. Chemical vapor deposition (CVD) and by covering all exposed surfaces of the first insulating layer 32, the diffusion region 36 and the first sidewall spacer 40. Subsequently, a conductive layer 44 such as a polysilicon film is deposited to a predetermined thickness over the entire upper surface of the wafer. Because of the voids between the diffusion regions 36, the polysilicon conductive layer 44 is a non-planarized layer that includes recessed portions between the diffusion regions 36.

As shown in FIG. 2D, in the fourth step, the polysilicon conductive layer (ie, a plurality of polysilicon gate regions 46 spaced apart in parallel to each other is formed toward the second direction perpendicular to the actual diffusion region 36). 44) This is selectively removed by photo and etching processes. Thereafter, an ion implantation process is performed on the wafer such that the polysilicon gate region 46 is doped with impurities of the second semiconductor type. The polysilicon gate region 46 is transformed into a high-doped polysilicon layer with increased conductivity. Since the gate region 46 is formed on the second insulating layer 42 (oxide film), the diffusion region 36 is formed under the gate region, and impurity ions are not implanted into the diffusion region 36, but the gate region 46 is formed. Only injected into Thus, this process is self aligned.

As shown in FIG. 2E, one second sidewall spacer 49 is formed for each sidewall of the gate region 46. The second side wall spacer 49 is, for example, anisotropic dry-type on the sidewall insulating layer until the deposition of the sidewall insulating layer such as the silicon oxide film or the silicon nitride film and the upper surface of the lower first insulating layer 32 are exposed. By performing the etching, it can be formed to a predetermined thickness over the entire upper surface of the wafer. The remaining portions of the sidewall insulating layer are provided as the second sidewall spacer 49 described above.

FIG. 2F is a cross-sectional view of the wafer structure of FIG. 2E taken along lines II ′ and II-II ′. As shown on the left side of FIG. 2F, the diffusion region 36 may be divided into a plurality of regions to provide the plurality of channel regions 48 that are located directly under the gate region 46. The portions located below the interval region between the gate regions 46 are provided as a plurality of source / drain regions 50. Thus, the intersections between gate region 46 and diffusion region 36 constitute an array of positions where memory cells of a ROM device are formed. For example, the portion indicated by reference number 51 shown on the left side of FIG. 2F is one channel region 48, one portion of the second insulating layer 42, and one portion of the gate region 46 located on the upper portion. It refers to one memory cell of a ROM device that includes two source / drain regions 50 on the site, both channel regions 48.

The above-described process steps satisfy the state of semi-production of the ROM device. Once a user defined binary code is received, a mask programming process is performed to permanently write the binary code to the ROM device. Thereafter, conventional processes such as interconnecting metals to complete the manufacture of the ROM device proceed. These processes are described with reference to FIGS. 2G, 2H and 3.

In the mask programming process shown in FIG. 2G, the first step is to coat the photosensitive film 52 over the entire top surface of the wafer. This photoresist film 52 is selectively removed to form a plurality of openings exposing a selected number of positions on the gate region 46 in which the first memory cell group selected to be permanently formed in the off-state is formed. By using the photosensitive film 52 as a mask, an ion-implantation process for implanting p-type impurities on the wafer is performed. In this process, impurity ions pass through the openings of the photosensitive film 52 and penetrate into the associated channel region 48 through exposed portions of the gate region 46 and the second insulating layer 42. The impurity doped channel region 48 allows associated memory cells to be permanently turned off. Conversely, the undoped channel region 48 allows associated memory cells to be permanently turned on. After this step, the photosensitive film 52 is removed.

In FIG. 2G, openings are formed on the memory cell 100 such that the memory cell 100 is permanently turned off through a mask programming process. In contrast, the memory cell 102 is permanently turned on because an opening is not formed in the upper portion thereof.

As shown in Fig. 2H, after the mask programming process, a third insulating layer 54 such as a planarization layer of BPSG is formed over the entire upper surface of the wafer. These third insulating layers 54 may include a plurality of source / drain contact windows 56 exposing all of the upper surfaces of the source / drain regions 50, and gate regions at selected positions. It is optionally removed to form a plurality of gate contact windows 57 exposing all of the top surface of 46. Then, a metal such as aluminum is filled in all the source / drain contact windows 56 and all the gate contact windows 57 so that a plurality of source / drain electrodes 58 and a plurality of gate electrodes 59 are formed, respectively.

After the source / drain electrodes 58 and the gate electrodes 59 are formed, all subsequent processes to complete production of the ROM device are in accordance with conventional techniques excluded from this description.

3 is a plan view of the ROM device, and FIG. 4 is a circuit diagram corresponding to a state in which the manufacture of the ROM device is completed. This circuit diagram shows an array of memory cells formed at the intersection between the diffusion region 36 and the gate region 46. For example, an intersection part embedded in a portion denoted by reference numeral 100 is a position where a memory cell in an off state is formed, and an intersection part embedded in a portion denoted by reference numeral 102 is a position where a memory cell in an on state is formed. The gate region 46 is provided as a plurality of word lines, and the diffusion region 36 is provided as a plurality of bit lines for accessing binary data stored in these memory cells. Access through these word lines and bit lines utilizes conventional techniques not described herein.

As mentioned above, ROM devices made in accordance with the present invention provide significant advantages over the prior art. First, since the SOI structure provides the insulating layer, that is, the first insulating layer 32 so as to insulate the source / drain region from the substrate, no leakage current occurs at the junction between the source / drain region and the substrate. Second, in the SOI structure, no breakdown voltage occurs at the junction between the source / drain region and the substrate. Thus, the ROM device of the present invention can increase its operating voltage.

As described above, the first semiconductor type is p-type and the second semiconductor type is n-type. However, in various other embodiments, the first semiconductor type may be n-type and the second semiconductor type may be p-type.

The present invention has been described based on preferred embodiments. However, the protection scope of the present invention is not limited by these examples.

Claims (30)

A first step of preparing a semiconductor substrate and forming a first insulating layer on the substrate; A second step of forming an intrinsic amorphous silicon layer on the first insulating layer; Removing a selected portion of the intrinsic amorphous silicon layer to form a plurality of substantially parallel spaced apart diffusion regions serving as bit lines facing in a first direction; A fourth step of performing an ion implantation process on the diffusion region by doping the first semiconductor type impurities into the diffusion region to adjust the threshold voltage of the diffusion region to a predetermined level; A fifth step of forming one first sidewall spacer on each sidewall of the diffusion region; A sixth step of forming a second insulating layer on the exposed surface of the first insulating layer, the diffusion region, and the first sidewall spacer; A seventh step of forming a conductive layer on the second insulating layer; A gate region defining positions for forming an array of memory cells so as to form a plurality of substantially parallel spaced gate regions which are directed in a second direction and overlapped with the bit lines, and serve as word lines; An eighth step of removing selected portions of the conductive layer which are overlapped portions of the plurality of channel regions located and the diffusion regions divided into the plurality of source / drain regions located between the channel regions; A ninth step of forming one second sidewall spacer on each sidewall of the gate region; Depositing a mask layer on exposed portions of the second insulating layer, the gate region and the second sidewall spacer, exposing the first position on the gate region to form a first group of memory cells selected to be permanently turned off; And selectively removing the mask portion while preventing the second position from being exposed on the gate region to form a second group of memory cells selected to be permanently turned on; In order to allow the doped channel region to be permanently turned off and the undoped channel region to be permanently turned on, an ion implantation process of doping an impurity of a second semiconductor type into the exposed channel region is performed. An eleventh step; Forming a third insulating layer to cover the exposed portions of the second insulating layer, the gate region, and the second sidewall spacer; A plurality of source / drain contact windows in which all source / drain regions are exposed so as to extend through the third and second insulating layers, and a gate contact window exposed at a selected number on the gate regions associated with the on-state memory cells; Forming a thirteenth step; And a fourteenth step of filling the source / drain contact window and the gate contact window with a conductive material to form a plurality of gate electrodes in the gate contact window and a plurality of source / drain electrodes in the source / drain contact window, respectively. Manufacturing method. The method of claim 1, And the first semiconductor type is p-type and the second semiconductor type is n-type. The method of claim 1, And the first semiconductor type is n-type and the second semiconductor type is p-type. The method of claim 1, And said first insulating layer is made of an oxide film. The method of claim 1, And said intrinsic amorphous silicon layer is formed by plasma enhanced chemical vapor deposition. The method of claim 1, And the first side wall spacer is formed with an oxide film. The method of claim 1, The first side wall spacer is formed of a nitride film. The method of claim 1, And the second insulating layer is formed of an oxide film. The method of claim 1, And the second insulating layer is formed of a nitride film. The method of claim 1, And the conductive layer is a polysilicon layer doped with an impurity. The method of claim 1, And the second direction is substantially perpendicular to the first direction. The method of claim 1, And the second side wall spacer is formed of a nitride film. The method of claim 1, And the second side wall spacer is formed of an oxide film. The method of claim 1, And said third insulating layer is a planarization layer of borophosphosilicate glass. The method of claim 1, A method of manufacturing a ROM device, wherein the conductive material is metal. Semiconductor substrates; A first insulating layer formed on the substrate; A plurality of diffusion regions formed on the first insulating layer and substantially spaced apart in parallel in the first direction to serve as bit lines; First side wall spacers formed on each sidewall of the diffusion region; A second insulating layer covering the first insulating layer, the diffusion region, and the first sidewall spacer; A gate region and a plurality of channel regions located below the gate region and positioned between the channel regions facing in a second direction and provided as a portion overlapping the bit line, that is, a word line, to define an array of memory cells; A plurality of gate regions formed on the second insulating layer to be substantially spaced apart in parallel so as to be divided into a plurality of source / drain regions, wherein the first selected channel region group forms a first memory cell group to be permanently turned off Dopants are doped to form a second memory cell group so that the second selected channel region group is permanently turned on; Second sidewall spacers formed on each sidewall of the gate region; A plurality of source / drain contact windows formed on the second insulating layer and the gate region to expose all the source / drain regions on the diffusion region, and a selected number of positions on the gate region associated with the memory cell in the on state; A third insulating layer having a plurality of gate contact windows for exposing them; A plurality of source / drain electrodes formed in the source / drain contact window in the third insulating layer; And And a plurality of gate electrodes formed on the gate contact window in the third insulating layer. The method of claim 16, And said first insulating layer is made of an oxide film. The method of claim 16, And said first insulating layer is made of a nitride film. The method of claim 16, The diffusion region is a ROM device, characterized in that consisting of a polysilicon layer doped with a plurality of impurities. The method of claim 16, And the first side wall spacer is formed of an oxide film. The method of claim 16, And the first side wall spacer is formed of a nitride film. The method of claim 16, And said second insulating layer is made of an oxide film. The method of claim 16, And said second insulating layer is made of a nitride film. The method of claim 16, And the gate region is a plurality of impurity doped polysilicon layers. The method of claim 16, And the second direction is substantially perpendicular to the first direction. The method of claim 16, And the second side wall spacer is formed of an oxide film. The method of claim 16, And the second side wall spacer is formed of a nitride film. The method of claim 16, And said third insulating layer comprises a planarization layer of borophosphosilicate glass. The method of claim 16, And the gate electrode is formed of a metal. The method of claim 16, And the source / drain electrode is formed of a metal.