KR19990016188A - Thin film transistor substrate for liquid crystal display - Google Patents

Abstract

The structure of a thin film transistor used in an in-plane switching (IPS) mode liquid crystal display device is formed in a shape having a U-shaped source electrode and an I-shaped drain electrode. This reduces the area of the silicon layer below the source / drain electrodes and reduces the light leakage current. In addition, while allowing a constant amount of current to flow while a voltage is applied, the parasitic capacitance is reduced by reducing the overlap between the drain electrode and the gate electrode, which generates the parasitic capacitance between the gate electrode and the drain electrode, thereby reducing the kickback voltage. Can be.

Description

Thin film transistor substrate for liquid crystal display

The present invention relates to a thin film transistor substrate of a liquid crystal display device.

The thin film transistor liquid crystal display using the recently developed in-plane switching (IPS) mode is characterized in that the voltage applied to the liquid crystal is applied laterally around the substrate, unlike the thin film transistor liquid crystal display using the twisted nematic liquid crystal. have. It is well known that the liquid crystal display of the IPS mode has much improved in view angle compared to the conventional twisted nematic liquid crystal display.

However, in the IPS mode, the aperture ratio is 2/3 lower than that of the twisted nematic liquid crystal display, and the contrast ratio is relatively low, such as 150: 1.

The IPS mode thin film transistor liquid crystal display device is mainly used for a monitor, and when used for a monitor, an absolute luminance of 200 cd / m 2 or more is required. Due to the low aperture ratio, IPS mode liquid crystal displays require a back light source that is four times brighter than a twisted nematic device. Unlike the note PC, the power consumption is not a problem because it is used for a monitor, but the generation of photo induced leakage current should be reduced for strong light incident on the thin film transistor substrate.

In addition, kick-back voltage caused by parasitic capacitance between the gate and drain causes problems such as flicker and afterimage. In general, an IPS mode liquid crystal display device is higher than a twisted nematic liquid crystal display device. Since the driving voltage is required, the kickback voltage is also increased, so the above problem is more prominent, and thus the solution of the above is required.

In the present invention, the optical leakage current is reduced and the kickback voltage is reduced in the IPS mode liquid crystal display.

1 is a plan view of a thin film transistor substrate of an in-plane switching (IPS) mode thin film transistor liquid crystal display device according to an exemplary embodiment of the present invention;

FIG. 2 is an enlarged view of a portion of the thin film transistor of FIG. 1;

3A and 4A illustrate the structure of a thin film transistor of a liquid crystal display according to the related art.

3B and 4B illustrate a structure of a thin film transistor of a liquid crystal display according to an exemplary embodiment of the present invention.

In order to solve the above problems, in the present invention, the structure of the thin film transistor used in the IPS mode liquid crystal display device is changed to a shape having a U-shaped source electrode and an I-shaped drain electrode.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a plan view of an IPS mode thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 2 is an enlarged view of a portion of the thin film transistor of FIG. 1.

As shown in Fig. 1 and Fig. 2, the horizontal gate line 1 and the vertical data line 2 are formed to cross each other, and at the intersection of each gate line 1 and the data line 2, respectively. Two common electrode lines 30 parallel to each other are formed horizontally inside the display unit of the pixel defined by the cross section. A common electrode 3 and a sub-pixel data line 4 connecting the two common electrode lines 30 are alternately formed in the vertical direction in parallel with the data line 2. The pixel electrode 4 is connected to two pixel electrode lines 40 overlapping the common electrode line 30 and formed horizontally, and one of the two pixel electrode lines 40 is connected to the drain electrode 7 of the thin film transistor. have.

Now, the structure of the thin film transistor will be described in detail.

The gate electrode of the thin film transistor is part of the gate line 1, and an amorphous silicon layer 5 is formed on the gate electrode 1. The source electrode 6 and the drain electrode 7 are formed on the amorphous silicon layer 5, but the drain electrode 7 is formed in an I-shape narrower than the conventional drain electrode, and the source electrode 6 ) Is shaped like a U and surrounds the drain electrode 7.

In addition, in the case of an etchback type thin film transistor, the amorphous silicon layer 5 should be formed to have a thickness of 2,000 Å or more, which is an amorphous silicon layer 5 when etching the n + amorphous silicon layer formed on the amorphous silicon layer. ) Is etched together. In the case of the etch-back type thin film transistor, since the amorphous silicon layer is formed thick, more light leakage current is generated.

As a method for reducing the light leakage current, there is a method of reducing the amount of light flowing into the amorphous silicon layer, or a distance from the leakage pass due to the incoming light, and the like. The light leakage current is reduced by reducing the area of the amorphous silicon layer overlapping the / drain electrode.

3A and 3B show the structure of the thin film transistor according to the prior art and the structure of the thin film transistor according to the embodiment of the present invention, respectively.

Since the center portion of the amorphous silicon layer is blocked by the gate electrode, the portion where the amorphous silicon layer receives light is a portion protruding out of the gate electrode. When the amorphous silicon layer receives light and generates a photo leakage current, the photo leakage current flows through the contacting source / drain electrodes. Therefore, by reducing the area of the electrode in contact with the amorphous silicon layer, the influence of the light leakage current can also be reduced.

3A and 3B, when the source / drain electrode structure according to the embodiment of the present invention (FIG. 3B), the area of the amorphous silicon layer 5 overlapping the source / drain electrodes 6 and 7 ( A ', B') is less than that according to the prior art (A, B), thereby reducing the light leakage current.

On the other hand, in order to secure a certain amount or more of the current flowing from the source electrode to the drain electrode, it is necessary to maintain the electrode width to a certain degree. This is because the current flowing when the voltage is applied is proportional to the electrode width to the distance between the electrodes, and thus there is a limit to reducing the electrode width. In the present invention, while reducing the width of the source electrode to reduce the Cgd while ensuring a constant current, the drain electrode is formed in a shape surrounding the source electrode.

The parasitic capacitance Cgd between the gate electrode and the drain electrode that generates the kickback voltage is calculated as follows. To illustrate this, the structure of the thin film transistor according to the prior art and the structure of the thin film transistor according to the embodiment of the present invention are illustrated in FIGS. 4A and 4B.

In the case of the thin film transistor according to the related art, the electrode width W is 20 μm and the inter-electrode distance L is 5 μm, and the length of the gate electrode and the drain electrode 7 overlapping with each other in consideration of stepper misalignment ( When C) is about 2.5 µm, the overlapping area is 2.5 µm × 20 µm (overlap length × electrode width) = 50 µm ² (FIG. 4A).

On the other hand, in the thin film transistor structure according to the present invention, when the drain electrode 7 is formed to have a minimum width of 4 μm, the overlapping area C ′ of the gate electrode and the drain electrode 7 may be 8 μm. Is 8 μm × 4 μm (overlap length × electrode width) = 32 μm ² , which is much smaller than that according to the prior art (FIG. 4B).

In the present invention, by using a thin film transistor structure having an I-shaped drain electrode and a U-shaped source electrode, the amount of light leakage current due to light incident from the rear light source is reduced, and the parasitic capacitance between the gate electrode and the drain electrode is reduced. By reducing the kickback voltage can be reduced.

Claims (7)

Multiple gate lines parallel to each other, A plurality of data lines crossing the gate lines and parallel to each other, A plurality of common electrodes formed in parallel with the data line inside the display unit of the pixel defined by the intersection of the gate line and the data line; A plurality of pixel electrodes formed in parallel with the common electrode between the common electrodes, A gate electrode formed adjacent to the intersection of the gate line and the data line and being a branch of the gate line, An amorphous silicon layer formed on the gate electrode, A drain electrode formed on the amorphous silicon layer and connected to the pixel electrode; And a source electrode formed on the amorphous silicon layer and surrounding the drain electrode. In claim 1, And two common electrode lines formed inside the display unit of the pixel and connected to the plurality of common electrodes, the two common electrode lines being parallel to the gate lines. In claim 2, And two pixel electrode lines formed to overlap the common electrode line and connected to the plurality of pixel electrode lines. The method according to any one of claims 1 to 3, The drain electrode is an I-shaped liquid crystal display device. In claim 4, The source electrode is a U-shaped liquid crystal display device. In claim 5, The width of the source electrode is between 2μm to 10μm liquid crystal display device. In claim 6, The width of the drain electrode is between 2μm and 10μm liquid crystal display device.