KR19990012752A - Nonvolatile Semiconductor Memory and Repair Method - Google Patents

Abstract

The present invention relates to a nonvolatile semiconductor memory capable of repairing a defective word line to a redundant word line and a repair method thereof, comprising: a plurality of word lines arranged in a row direction; A plurality of bit lines arranged respectively perpendicular to the word lines; A plurality of first electrodes connected to one of the bit lines, a second electrode connected to one of the source lines, and a control gate connected to one of the word lines; In the word line repair method of a nonvolatile semiconductor memory having memory cells, a redundant word is formed by using an adjacent word line that shares the source line in common with a word line including a defective memory cell among the memory cells. Repairing is performed to two redundant word lines corresponding to one of the lines.

Description

Nonvolatile Semiconductor Memory and Repair Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electrically erasable and programmable nonvolatile semiconductor memories, and more particularly to nonvolatile semiconductor memories and repair methods for repairing defects in memory cells.

In general, nonvolatile semiconductor memories such as flash EEPROMs are capable of erasing and programming data electrically, and are based on NOR and NAND types according to types of memory cells connected to bit lines. Divided by. A nonvolatile semiconductor memory having memory cells arranged in a NAND type has a disadvantage in that data can be input and output at high speed while being highly integrated. On the contrary, the nonvolatile semiconductor memory having the NOR-type memory cells has an advantage of being able to input and output data at high speed while being disadvantageous for high integration. An example of a stacked gate flash EEPROM that is widely used among such quinoa flash EEPROMs is disclosed in US Pat. No. 4,203,158 invented by Froman Bent Chkowsky. Here, data to be programmed in the stacked cell is stored by a Fowler-Nordheim Tunneling method, and data is erased by the same method even when erased. An example of another type of stacked gate flash EEPROM is disclosed in U.S. Patent No. 4,698,787, invented by Mukherjee, the cell structure of which is shown in FIG.

Referring to FIG. 1, a deeply doped impurity region source region 102 and a relatively shallow doped drain region 104 are formed in the semiconductor substrate 101. The drain region 104 is a region doped with a high concentration of N + impurities, and the source region 102 is a region doped with a low concentration of N− impurities. In addition, the source region 102 includes a high concentration impurity doping region 103 having the same concentration as that of the drain region 104. A channel region 105 is defined between the source region 102 and the drain region 104. The floating gate 107 is formed on the channel region 105 via the gate oxide film 106. The control gate 109 is formed on the floating gate 107 via an interlayer insulating film 108, for example, an oxide / nitride / oxide (ONO) film. On the other hand, the gate oxide film 106 is commonly referred to as a tunnel oxide film.

Referring to the general erasing, program, and read operations of the flash memory cell described above, the operation of erasing electrons stored in the floating gate is controlled by -10V to -15V in the control gate 109. 3V to 10V are applied to the source region 102 or the substrate. In another erase method, OV is applied to the control gate 109 and 10V to 15V are applied to the source region 102 or the semiconductor substrate 101. This means that electrons stored in the floating gate 106 are discharged through the tunnel oxide film 106 due to the voltage difference induced at both ends of the tunnel oxide film 106. This erase operation uses Fowler-Nordheim Tunneling, which lowers the threshold voltage of the memory cell to 1V to 2V. In contrast to the erase operation, the program of the memory cell applies 3V to 7V to the drain region 104, 7V to 15V to the control gate 109, and ground voltages to the source region 102 and the semiconductor substrate 101. Is applied. This is because some of the hot electrons generated in the channel are stored in the floating gate 107 by the electric field of the control gate 109, increasing the threshold voltage of the cell from 2V to 7V. Completed by channel hot electron injection. The read operation of the memory cell is an operation of reading the threshold voltage of the memory cell through a sense amplifier, applying 4V to 5V to the control gate 109 of the selected memory cell, applying 1V to the drain region 104, and The ground voltage is applied to the region 102, the semiconductor substrate 101, and the control gate 109 of the unselected memory cell. This voltage application does not generate a current through the selected memory cell when the selected memory cell is programmed to have a threshold voltage of 7V. However, when the selected memory cell is erased and has a threshold voltage of about 2V, current is discharged through the selected cell. The discharge current changes the voltage flowing into the bit line, and the changed voltage is sensed through a sense amplifier connected to the bit line.

However, when an over erased memory cell is generated in the normal read operation as described above, an over erasure problem occurs. That is, in the erase operation of memory cells connected to the same bit line as the selected memory cell and connected to each non-selected word line, electrons stored in the floating gate 109 are non-uniform in thickness or process. It may be excessively erased due to a defect or the like. Such erasure is a phenomenon in which the threshold voltage of the memory cell is lowered to 0V or less, and is generally referred to as over-erase. That is, even if a voltage of 0V is applied to the control gate 109, it means that it is turned on.

2 is a diagram illustrating a memory cell array of a conventional nonvolatile semiconductor memory device. Referring to FIG. 2, each bit line BL1 is connected to drains of the memory cells M11 to M14 arranged in the column direction, respectively. The remaining bit lines BL2 to BL5 are also connected to drains of the corresponding memory cells M21 to M24, M31 to M34, M41 to M44, and M51 to M54 by the same method. The word line WL1 is commonly connected to the gates of the memory cells M11, M21, M31, M41, and M51 arranged in the row direction. Sources of the adjacent memory cells, for example, memory cells M11 and M12, are commonly connected to a common source line CSL. The word lines WL1 to WL4 are connected to the word line decoder 101, and the bit lines BL1 to BL5 are connected to the column decoder / column selection transistor 102. The memory cells M11 to M14, M21 to M24, M31 to M34, M41 to M44, and M51 to M54 constitute a memory cell array MCA.

Next, the operation according to the prior art assumes that one of the memory cells M11 to M14, M21 to M24, M31 to M34, M41 to M44, and M51 to M54 is selected, and the adjacent memory cell M12 is over-erased. Will be explained.

First, there should be no current flowing through memory cells other than the selected memory cell M11 during a program or data reading operation. However, if the unselected memory cell M12 is over erased, current flows through the unselected memory cell M12, causing a failure. Therefore, in order to repair the defective memory cell M12, a repair method is provided in which a current flowing to the defective bit line BL1 is prevented and replaced by an redundant redundant bit line (not shown). However, even if the word line WL2 including the defective memory cell M12 is repaired to a redundant word line (not shown), current flows through the erased cell M12 to the common source line CSL even when the word line WL2 is disconnected or grounded. do.

In case of repairing the word line WL2 connected to the over erased memory cell M12, the repair method only prevents the decoded address from being applied to the word line WL2, so that the voltage is not applied to the word line WL2 during a program or read operation. It is not possible to prevent the current flowing through the excessively erased cell M12 because the ground voltage is applied.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to provide a nonvolatile semiconductor memory capable of repairing a defective word line to a redundant word line and a repair method thereof.

Another object of the present invention is to provide a nonvolatile semiconductor memory and a repair method capable of performing word line redundancy without malfunction even when an over-erased cell is generated.

It is still another object of the present invention to provide a nonvolatile semiconductor memory and a repair method thereof that can increase the reliability of a memory cell.

1 is a cross-sectional view of a general nonvolatile memory cell,

2 is a schematic circuit diagram of a nonvolatile memory cell array according to the prior art,

3 is a block diagram showing control circuits required for performing a word line repair according to the present invention;

4 is a detailed circuit diagram of the word line repair circuit shown in FIG. 3;

FIG. 5 is an output timing diagram for FIG. 4.

According to the technical idea for achieving the above object, a nonvolatile semiconductor memory comprises a plurality of word lines arranged in a row direction; A plurality of bit lines arranged respectively perpendicular to the word lines; A plurality of source lines each arranged in a row direction; A plurality of first electrodes connected to one bit line of the bit lines, a second electrode connected to one source line of the source lines, and a control gate connected to one word line of the word lines, respectively; Memory cells; A plurality of redundant word lines arranged in a row direction; And a first electrode connected to one bit line of the bit lines, a second electrode connected to one source line of the source lines, and a control gate connected to one word line of the redundant word lines. A plurality of redundant memory cells; A repair is performed to two corresponding word lines among the redundant word lines using a word line including a defective memory cell among the memory cells and an adjacent word line sharing the word line and the source line as one unit. And a word line redundant control unit for performing the operation.

On the other hand, a plurality of word lines arranged in the row direction, respectively; A plurality of bit lines arranged respectively perpendicular to the word lines; A plurality of first electrodes connected to one of the bit lines, a second electrode connected to one of the source lines, and a control gate connected to one of the word lines; In the word line repair method of a nonvolatile semiconductor memory having memory cells, a redundant word is formed by using an adjacent word line that shares the source line in common with a word line including a defective memory cell among the memory cells. Repairing is performed to two redundant word lines corresponding to one of the lines.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, it should be noted that like elements and parts in the drawings represent the same numerals wherever possible.

3 is a schematic block diagram of a memory cell array and a peripheral circuit of a nonvolatile semiconductor memory implemented according to an embodiment of the present invention. Referring to FIG. 3, source lines SL1 and SL2 of all memory cells M11 to M14, M21 to M24, M31 to M34, M41 to M44, and M51 to M54 are selectively selected by the source line selection transistors ST1 to ST4. Is applied. That is, the channels of the source line selection transistors ST1 and ST2 according to the present invention are connected in series between the common source line CSL and the source line SL1, and their gates are connected to the corresponding word lines WL1 and WL2, respectively. In the channel of the source line selection transistors ST3 and ST4, a channel is connected in series between the common source line CSL and the source line SL2, and their gates are connected to corresponding word lines WL3 and WL4, respectively.

The current flowing through the memory cell flows through the voltage coupling according to the capacitance between the control gate and the floating gate and the capacitance ratio between the floating gate and the substrate, whereas the source line select transistors ST1 to ST4 have only a control gate. Is a transistor. Therefore, the current applied to the memory cell is not limited because of the source line select transistors ST1 to ST4. That is, 3V to 15V are applied to the selected word line, for example, word line WL1 in the course of reading the program or data, and the gate of the source line select transistor ST1 is connected to the word line WL1 and thus does not affect the application of current. In addition, since the source line selection transistor ST1 is turned on by the voltage applied to the selected word line WL1 during a program or read operation, the ground voltage is applied.

In addition, when an over erased memory cell M12 occurs, word line repair may be performed due to the use of the source select transistors ST1 to ST4. That is, in the word line repair, a cell in which the current flowing to the bit line BL1 is excessively erased by source line select transistors ST1 and ST2 turned off in response to the ground level voltage applied to the repaired word lines WL1 and WL2. The path through which M12 discharges to source line SL1 is blocked. This is to prevent malfunctions in program and read operations. When performing word line repair using the source line selection transistors ST1 to ST4, two word lines sharing the source line SL must be repaired at the same time.

Meanwhile, the repair fuse circuit 302 stores an address for replacing an address applied to a word line to which a defective memory cell is connected with another. The redundancy select circuit 301 compares the address stored in the repair fuse circuit 302 with a low address applied from the outside. If the address values are identical to each other, the redundancy select circuit 301 outputs a signal that prevents the word line decoder / word line repair circuit 303 from selecting a defective word line pair. A voltage allowing the selection of the redundant word line pair DWL is applied to the redundant word line pair DWL.

4 is a detailed circuit diagram illustrating the word line repair circuit shown in FIG. 3 according to an embodiment of the present invention, and FIG. 5 is a diagram illustrating an output timing relationship of the circuit shown in FIG. 4.

4 and 5, the section T1 is a section for the setup, and is a state until the signal? SETUP is transitioned to the high level. The section T2 is a section for initialization. When the signal? SETUP transitions to a high level, the node N4 is set to a low level, and the node N3 is set to a high level. At this time, since the node N2 is set at the low level, the logic level state of the nodes N3 and N4 is maintained even when the signal? SETUP transitions to the high level. The interval T3 is a waiting time until the next signal comes after the signal? SETUP transitions to a low level.

On the other hand, when the pre-decoded address signals DRA0 to DRA2 are all at the high level, a block is selected in accordance with the output of the NAND gate 401 transitioning to the low level. That is, during the period T4 where the node N2 transitions to the high level, the logic state of the node N3 transitions from the high level to the low level, and the logic state of the node N4 transitions from the low level to the high level. The output of the inverter 407 which inverts the logic state of this node N4 is input to the input terminal of the level shifter 408. This level shifter 408 boosts the input voltage. For example, when OV is input through the input terminal of the level shifter 408, the output becomes OV as it is, and when 3V is input through the input terminal, a voltage of 3V to 15V is output. The two output terminals N5 and N6 of the level shifter 408 are terminals for outputting the same voltage, and two inverters are connected to the output terminals N5 and N6. The output terminals of these two inverters are connected to corresponding word lines WL1 and WL2, respectively. The word line repair circuit as described above is connected to the remaining word lines WL3, WL4,. This configuration is to apply the same level of voltage to the two word lines sharing the source line SL and to repair the two word lines. The gate of the PMOS transistor 409 and the NMOS transistor 410 having a channel connected in series between the node N7 and the ground power supply is connected to the output terminal N5 in common. A channel of the N-type MOS transistor 411 is connected in series between the node N7 and the word line WL1, and the gate of the transistor 411 is a node. Is connected to. Similarly, an inverter is connected to the output terminal N6 in the same manner.

The same voltage is applied to the output nodes N5 and N6 by the output of the inverter 407 of FIG. 4, and therefore, the voltages output through the two word lines WL1 and WL2 are the same. However, in order to control the two word lines WL1 and WL2, for example, when only the word line WL1 is operated, a read voltage for reading a program or data is applied only to the supply terminal N7, and only the word line WL2 is operated. In this case, only a supply voltage for reading a program voltage or data is applied to the supply terminal N8. Terminals Wow Each of the N-type transistors 411 and 414 connected to each other is to transfer the voltage to the word lines WL1 and WL2 when the ground voltage is applied to the supply terminals N7 and N8. This is to prevent the transfer of 0V because the transistors 409 and 412 are formed MOS transistors. The terminal Wow The signal applied to is the inverted signal of the signal provided to the supply terminals N7 and N8 respectively. That is, when the signal applied to the supply terminal N7 is a ground level voltage, the terminal The signal applied to the high level voltage and the terminal when the signal applied to the supply terminal N7 is a high level voltage. The signal applied to is the ground level voltage. Similarly, supply terminal N8 The same relationship applies.

A channel of the N-type MOS transistor 403 and a fuse 404 are connected between the terminal N3 of the data latch 405 and the ground power supply. Here, the logic level state of the node N3 until the fuse 404 is cut is set to a high level by the N-type transistor 406 turned on at initialization. However, after the fuse 404 is cut, since the path for discharging the voltage charged to the node N3 disappears, the initialization operation is performed regardless of what voltage is applied to the node N2, the gate terminal of the N-type MOS transistor 403. The high level state set in Fig. 5 is maintained to become waveform N3 'of FIG. Accordingly, since the node N4 is fixed to the low level state, the voltage applied to the input terminal of the level shifter 408 is applied with a high level so that the boost voltage is always applied to the nodes N5 and N6. Accordingly, the word lines WL1 and WL2 are always maintained at the ground voltage state by the N-type MOS transistor 410 turned on in response to the boost voltages applied to the nodes N5 and N6. In addition, the N-type transistors 411 and 414 are transistors that are turned on only when a ground voltage is applied to the supply terminals N7 and N8, and thus do not affect the ground voltage states of the word lines WL1 and WL2.

In order to perform the above-described word line repair, it is necessary to always repair the unit in two word line units that share the source line SL as if there are two nodes N5 and N6 controlled by the predecoded address signals DRA0 to DRA2. In addition, the period T5 represents the operation waiting state after the decoding is completed.

As described above, the present invention has an advantage of repairing a defective word line to a redundant word line among the word lines used in the nonvolatile semiconductor memory. In addition, the present invention has the advantage that the word line redundancy can be performed without malfunction even when an excessively erased cell is generated. In addition, the present invention also has the advantage of increasing the reliability of the memory cell.

Claims (8)

In a nonvolatile semiconductor memory: A plurality of word lines each arranged in a row direction; A plurality of bit lines arranged respectively perpendicular to the word lines; A plurality of source lines each arranged in a row direction; A plurality of first electrodes connected to one bit line of the bit lines, a second electrode connected to one source line of the source lines, and a control gate connected to one word line of the word lines, respectively; Memory cells; A plurality of redundant word lines arranged in a row direction; And a first electrode connected to one bit line of the bit lines, a second electrode connected to one source line of the source lines, and a control gate connected to one word line of the redundant word lines. A plurality of redundant memory cells; A repair is performed to two corresponding word lines among the redundant word lines using a word line including a defective memory cell among the memory cells and an adjacent word line sharing the word line and the source line as one unit. A nonvolatile semiconductor memory comprising: a word line redundant control unit. The nonvolatile semiconductor memory of claim 1, wherein the source line is shared in units of two memory cells among the memory cells arranged in the column direction. The word line redundant control unit of claim 2, wherein the word line redundant control unit A plurality of switching transistors having a channel connected in series for each of the shared source lines, and a gate connected to a corresponding one of the word lines; When a defective one of the memory cells is generated, a voltage of a first level is applied to a word line of the defective memory cell in response to a decoded low address and an adjacent word line sharing the word line and the source line. Nonvolatile semiconductor memory, characterized in that consisting of a repair control unit for applying. The nonvolatile semiconductor memory of claim 3, wherein the switching transistor is an enMOS transistor. The nonvolatile semiconductor memory of claim 4, wherein the first level is a ground level. The method of claim 3, wherein the repair control unit A data latch; A first transistor connected to one side of the data latch and configured to set an initial level value of the data latch in response to a setup signal; A first logic gate connected to the other side of the data latch and configured to set a logic value of the data latch in response to the decoded low address; A level shifter connected to one side of the data latch; And a plurality of inverters connected to an output terminal of the level shifter and configured to perform a switching operation by a control voltage required for various programs or read operations. The nonvolatile semiconductor memory of claim 6, wherein the first transistor is an N-type MOS transistor. A plurality of word lines each arranged in a row direction; A plurality of bit lines arranged respectively perpendicular to the word lines; A plurality of first electrodes connected to one of the bit lines, a second electrode connected to one of the source lines, and a control gate connected to one of the word lines; A word line repair method of a nonvolatile semiconductor memory having memory cells, comprising: Performing repairing to two corresponding redundant word lines among redundant word lines using one adjacent word line sharing the source line in common with a word line including a defective memory cell among the memory cells. How to feature.