KR0169413B1 - Erase verifying method of non-volatile semiconductor memory - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Nonvolatile Semiconductor Memory.

2. The technical problem to be solved by the invention

An improved erase verification method in a memory of a folded bit line structure is provided.

3. Summary of the Solution of the Invention.

A plurality of memory transistors constitute a single NAND cell string, and the memory transistors are arranged in a matrix form on word lines in a row direction and bit lines in a column direction to form a memory cell array, and the bit lines have a folded bit line structure. And an erase verification method of a nonvolatile semiconductor memory having a selection transistor and a reference cell to provide a reference voltage to the bit line, after the memory transistor in the memory cell array is erased. And applying a second voltage different from the first voltage to the source terminal of the ground select transistor in the selected NAND cell string to perform erase verification.

4. Important uses of the invention

It is suitably used for erasure verification of nonvolatile semiconductor memory.

Description

Erasing verification method of nonvolatile semiconductor memory

1 is a circuit diagram of a nonvolatile semiconductor memory applied to the prior art.

2 is an operation timing diagram relating to erasure verification of the circuit according to FIG.

3 is a circuit diagram of a nonvolatile semiconductor memory according to the present invention.

4 is an operation timing diagram relating to erasure verification of the circuit according to FIG.

5 is a detailed circuit diagram of a voltage generator for applying a ground voltage to the memory cell of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory such as a NAND type EEPROM, and more particularly to an improved erasure verification method capable of easily controlling the threshold voltage value of an erased memory cell in a memory having a folded bit line structure. .

In general, in a flash memory of a NAND structure having a cell array composed of string units in which a plurality of memory cells are connected in series among nonvolatile semiconductor memories, a circuit as shown in FIG. 1 has a typical folded bit line structure. In FIG. 1, the reference cell unit 100 includes a plurality of units including the reference cell selection transistors 2 and 3 and the reference cell 20, and the memory cell unit 200 includes the first and second string selection transistors 21 and 22 and a charge axis. Memory cell transistors 10 having an applied floating gate and ground select transistors 31. The page buffer 400 includes an inverter 401.402 and is connected between sense bit lines SBL and SBLB, and a high voltage protection unit 300 including high voltage prevention transistors 41 and 42 between the sense bit lines SBL and SBLB and bit lines BL and BLB. Is connected. In FIG. 1, the word lines WLO-n are connected to the control gates of the memory cell transistors 10, respectively, and the source terminals of the reference cell transistors 20 in the reference cell unit 100 are source terminals of the ground select transistors 31 in the memory cell unit 200. Are connected in common with each other to receive a ground voltage of a predetermined level. The memory cell transistors 10 are composed of a MOS transistor having a floating gate and a control gate, each of which stores charge, and forms a NAND cell structure by connecting in series to facilitate integration. In this field, a configuration in which the memory cell transistors 10 and the selection transistors are formed in one series connection structure is commonly referred to as a NAND cell unit or a memory cell string.

In FIG. 1, when the program operation for writing data to the memory cell transistor in the memory cell string is completed or the erase operation for erasing the written data is completed, the charge is present or absent in the floating gate of the cell transistor 10. That is, when a programmed memory cell (data 0, ie, an off cell) operates as an enhancement transistor having a threshold voltage of, for example, about 1 volt, the memory cell may be, for example, erased. It operates as a depletion transistor with a threshold voltage of about -3 volts. Conversely, when a programmed memory cell (data 1, ie on-cell) operates as a transistor of a depletion mode with a threshold voltage of, for example, about -3 volts, the memory cell when erasing is completed is For example, it operates as an enhancement transistor having a threshold voltage of about 1 volt.

A typical erase of memory cell transistor 10 of FIG. 1 is to apply a first voltage, for example 0 volts, to a control gate of transistor 10 and apply a high voltage, for example 20 volts or more, to a bulk layer that is the substrate of a memory chip. Is achieved. Accordingly, the threshold voltage of the selected cell transistor 10 at the time of erasing is changed to a value of about -3 volts. Therefore, the erasure verification is a threshold voltage verification operation for confirming whether or not erase is normally performed and all erase cells have a threshold voltage value of about -3 volts (assuming the above), and the threshold voltage value of the erased cell. If this is not the set value, it includes a level optimization operation that adjusts it back to the set value (eg -3 volts in some cases).

As such, it can be seen that the erasure verification is necessary to confirm whether all of the erased memory cell transistors operate as transistors of a preset mouse (enhanced or depletion mode) after completion of the erase operation. The semiconductor memory device becomes one of important operations among the various operations of the semiconductor memory.

The conventional erase verification method will be described below to help a more thorough understanding of the present invention with reference to the configuration of the main part of the memory of FIG. 1 and FIG. 2 showing the operation timing of FIG.

In Fig. 1, the method of performing erase verification is very similar to the normal read operation of a general NAND type memory. First, an erase word is applied to a corresponding bit line depending on whether an erase state of a cell selected by an enabled word line and a string select transistor is present. The levels of voltages that are developed are different. In this case, when the cell is on cell (assuming that it is an erased cell), the corresponding bit line is developed to almost ground level. On the contrary, when the cell is off cell, for example, the corresponding bit line is maintained at almost the level Vcc of the power supply voltage. Referring to FIG. 2, the reference cell selection signal signals 2C and 2D having logic level high and low, respectively, are applied to the reference cell selection signal terminals RSL1 and RSL2 of FIG. 1, respectively, at the beginning of the period T1. When the string select signals 2E and 2F having the? Are respectively applied to the string select signal terminals SSL1 and SSL2 of FIG. 1, the reference cell 20 of the reference cell unit 100 is electrically connected to the bit line BLB, and the memory of the memory cell unit 200 is controlled. The cell string is electrically connected to the bit line BL. That is, by applying the signals, the right reference cell string of the reference cell unit 100 is selected and the left memory cell string of the memory cell unit 200 is selected in the first diagram. If the logic levels of the above signals are reversed in FIG. In this state, 0 volt is applied to the word line connected to the control gate of the memory cell to be erased and verified, and a high voltage Vread is applied to the remaining word lines. FIG. 2 shows that the signal 2A is applied to the word line WL0 of FIG. 1 and the signal 2B is provided to the remaining word lines WL1-n to verify the first memory cell 10 of the left string of FIG. Accordingly, the same voltage level as waveform 2I of FIG. 2 appears in the bit line BL of FIG. 1, and the voltage level similar to waveform 2J of FIG. 2 appears in the corresponding bit line BLB. The occurrence of such a voltage level is expressed in the above description as a term of development. In FIG. 2, referring to the waveforms, the voltage level of the bit line BLB is developed to a reference level Ref which is an intermediate level between a power supply voltage level and a ground level, and the voltage level of the bit line BL is equal to or less than the reference level. We can see that it is developed by. In this case, the memory cell 10 is normally erased to operate as a transistor of a depletion mode having a threshold voltage of about -3 volts. In addition, the reference level is a level represented by the turn-on of the reference cell transistor 20, and in design, the reference level on the bit line by the reference cell is an intermediate level between the bit line potential appearing during programming and erasing of the memory cell transistor. It is set in advance according to. Therefore, when the signals 2K and 2L of FIG. 2 are applied to the latch and latch bar terminals LA and LAB of FIG. 1, the voltage level equal to the waveform 2M of FIG. 2 appears on the sense bit line SBL of the page buffer 400, and its corresponding The sense bit line SBLB shows the same voltage level as waveform 2N in FIG. Accordingly, the page buffer 400 senses the potential difference respectively developed during the period T2 of FIG. The above-described waveforms in FIG. 2 are the levels that appear when the erase of the selected memory cell is normal, but if the level of the erased bit line is higher than the reference level in the interval T2 (the threshold voltage of the erased cell does not reach the set value). If not, the operation of erasure verification fails. In this case, the erasing operation is started again in the section after the section T2.

As described above, it can be seen that the conventional erase verify operation is performed by comparing the fixed reference level on the bit line developed by the reference cell with the level on the bit line developed by the selected memory cell. When the erased level for the selected memory cell is somewhat insufficient, and the developed level is near the reference level, the sensing margin of the page buffer 400 is narrowed at read time. If a cell that is not sufficiently erased at the time of erasing is found to be a normal cell in erasure verification, there is a problem that it is difficult to ensure the reliability of data in the passbook read operation. This problem can be found in the technical arrangement in FIG. That is, a conventional technical configuration in which the source terminal of the reference cell transistor 20 and the source terminal of the ground select transistor 31 in the memory cell unit 200 are commonly connected to apply a ground voltage of a predetermined level is common. Since the level cannot be easily controlled externally, the sensing margin of the page buffer is made the same at the time of erasure verification and read. Preferably, the erasure verification narrows the sensing margin so that only the erased cells are passed through the erasure verification, and it is necessary to ensure sufficient sensing margin during readout.

Accordingly, it is an object of the present invention to provide an improved erasure verification method for a nonvolatile semiconductor memory which can solve the above-mentioned conventional problems.

Another object of the present invention is to provide a method capable of more reliably performing erase verification of a semiconductor memory device to ensure read operation stably.

According to the method of the present invention for achieving the above object, a plurality of memory transistors constitute a single NAND cell string, the memory transistors are arranged in a matrix form on the word line in the row direction and the bit line in the column direction of the memory A method of erasing and verifying a nonvolatile semiconductor memory, wherein the bit array has a folded bit line structure and has a selection transistor and a reference cell to provide a reference voltage to the bit line. After the memory transistor is erased, a predetermined first voltage is applied to the source terminal of the reference cell, and a second voltage different from the first voltage is applied to the source terminal of the ground select transistor in the selected NAND cell string. Characterized in that to perform erasure verification. Here, the second voltage is set higher than the first voltage, and when the first voltage has a level of 0 volts, the second voltage is set to a bias voltage level. When erase verification is performed by the above method, even if the threshold voltage of the erased memory transistor is in the vicinity of the set level, the erase verification is found to fail and re-erase is performed in subsequent cycles, thereby ensuring a reliable read operation. This is guaranteed.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 3 is a circuit diagram of a semiconductor memory according to the present invention. FIG. 4 is an operation timing diagram related to erasure verification of the circuit according to FIG. 3, and FIG. 5 is a specific diagram of a voltage generator for applying a ground voltage to the memory cell of FIG. It is a circuit diagram.

Referring to FIG. 3, the connection and structure of the reference cell unit 100, the memory cell unit 200, the high voltage protection unit 300, and the page buffer 400 are illustrated. The reference cell unit 100 includes a plurality of units including the reference cell selection transistors 2 and 3 and the reference cell 20, and the memory cell unit 200 includes the first and second string selection transistors 21 and 22 and a floating gate for charge accumulation. Memory cell transistors 10 and ground select transistors 31. The page buffer 400 is composed of inverters 401 and 402 and is connected between sense bit lines SBL and SBLB, and the high voltage protection consists of high voltage prevention transistors 41 and 42 between the sense bit lines SBL and SBLB and bit lines, BL and BLB. Part 300 is connected. In FIG. 3, the word lines WLO-n are respectively connected to the control gates of the memory cell transistors 10.

Here, the configuration of FIG. 3 is similar to that of FIG. 1, but the source terminals of the reference cell transistors 20 in the reference cell unit 100 are distinguished from the source terminals of the ground select transistors 31 in the memory cell unit 200, respectively, so as to generate the first and second voltages. The structure is independently received through the ground line VGL1,2. That is, the characteristic of the erase verification according to the present invention is that the threshold of the erased memory transistor is removed by separating the reference cell and the ground line of the ground select transistor of the memory cell string without connecting them in common in order to increase the sensing margin at the read time. Even when the voltage is in the vicinity of the set level, the erasure verification is found to fail.

4 shows an operation timing diagram relating to the erasure verification of the circuit according to FIG. The characteristic of the externally applied signal shown in FIG. 4 is that the first voltage VGL1 and the second voltage VGL2, such as waveforms 4h and 4i, are applied to the ground line of the reference cell and the ground line of the NAND cell, respectively. FIG. 5 shows a specific circuit diagram of the voltage generator for applying a ground voltage to the memory cell of FIG. In FIG. 5, the second voltage generator 500 includes an inverter 510, a PMOS transistor 501, 503, 509, and an NMOS transistor 502, 504, 506, 507, and the switch unit 520 includes an inverter 521, an NMOS transistor 522, 523. It includes. In the circuit of FIG. 5, the bias voltage is output through the transistor 522 when the erase operation is verified by the operation of the switch unit 520, and 0 volt is output through the transistor 523 when the normal reading is performed, which indicates the logic of the control signal PIEVF. It can be seen that it is achieved by changing.

Hereinafter, the overall operation will be described with reference to the third, fourth, and fifth degrees as necessary. First, erasing of memory cells before erasure verification is generally accomplished by applying an erase voltage to the bulk (sub-straight). Accordingly, the threshold voltage of the memory cell erased by the F-N tunneling principle is lowered (assuming the erase is on the cell), and erase verification is started in this state. That is, verification is the operation of determining how much the threshold voltage of the memory cell has changed to the set value. According to the threshold of the erased cell, the memory cell string changes the degree of development of the pre-charged bit line level after the word line is enabled.

Referring to FIG. 4, reference cell selection signal signals 4c and 4d having logic level high and low, respectively, are applied to reference cell selection signal terminals RSL1 and RSL2 of FIG. 3, respectively, at the beginning of the period T11. When the string selection signals 4e and 4f having the voltage are respectively applied to the string selection signal terminals SSL1 and SSL2 of FIG. 3, the reference cell 20 of the reference cell unit 100 is electrically connected to the bit line BLB and the memory of the memory cell unit 200 is applied. The cell string is electrically connected to the bit line BL. That is, by applying the signals, the right reference cell string of the reference cell unit 100 is selected and the left memory cell string of the memory cell unit 200 is selected in FIG. 3. If the logic levels of the signals are reversed in Fig. 4, they are selected in contrast to the above description. In this state, 0 volt is applied to the word line connected to the control gate of the memory cell to be erased and verified, and a high voltage Vread is applied to the remaining word lines. 4 shows applying signal 4a to the word line WLO of FIG. 3 and providing signal 4b to the remaining word lines WL1-n to verify the first memory cell 10 of the left string of FIG. Accordingly, the voltage level equal to the waveform 4j of FIG. 4 appears in the bit line BL of FIG. 3, and the voltage level equal to the waveform 4k of FIG. 4 appears in the corresponding bit line BLB.

In this case, when the first voltage VGL1 and the second voltage VGL2 such as waveforms 4h and 4i are separately applied to the ground line of the reference cell and the ground line of the NAND cell, the erase verification of the memory cell that is not sufficiently erased is performed. It turns out to be a certain failure. That is, when an erase cell is selected and erased by a memory cell that does not have a threshold of sufficient level (below a certain negative voltage, for example, a voltage of -2 volts or less) in an erase operation, the bit line BL electrically connected to the memory cell is selected. The level is higher than the conventional case by the second voltage. This is a characteristic technique according to the present invention, and only during erasure verification, the bit line voltage of the memory cell is intentionally increased by external control to perform more reliable verification. Thus, a cell that has not been sufficiently erased leads to a certain verification failure and the cell that is found to fail in a subsequent erase operation cycle is completely erased.

On the other hand, in the case of a completely erased memory cell, even if the second voltage is applied to the ground line of the memory cell, its bit line level is set lower than the reference level of the reference bit line connected to the reference cell, so that it is successful in erasure verification. It turns out.

According to the present invention as described above, since the erase verification is performed at a narrower sensing margin, the sensing margin increases during the normal read operation, thereby increasing the reliability of the data.

Claims (5)

A plurality of memory transistors constitute a single NAND cell string, and the memory transistors are arranged in a matrix form on word lines in a row direction and bit lines in a column direction to form a memory cell array, and the bit lines have a folded bit line structure. An erase verification method of a ball volatile semiconductor memory having a selection transistor and a reference cell to provide a reference voltage to the bit line, the method comprising: after the memory transistor in the memory cell array is erased, And applying a second voltage different from the first voltage to the source terminal of the ground select transistor in the selected NAND cell string to perform erase verification. The method of claim 1, wherein the second voltage is higher than the first voltage. The method of claim 1, wherein the second voltage is set higher than the first voltage, and the second voltage is a bias voltage level when the first voltage has a level of 0 volts. A method of providing a voltage to a ground line during erasure verification of a nonvolatile NAND flash memory device having a folded bit line structure, wherein the reference cell ground line and the selected NAND cell ground line of the memory device are circuit-separated from each other. And applying first and second voltages to the respective ground lines. The method of claim 4, wherein the second voltage is set higher than the first voltage when the erase verification is performed, and the second voltage is a bias voltage level when the first voltage has a level of 0 volts. .