KR19990011440A - Interface unit accessible to all CPUs - Google Patents

Abstract

The present invention relates to an interface device accessible to all CPUs. In particular, the present invention is designed to allow access to Intel's CPU and Motorola's CPU interface, and includes / CS as a chip select signal, / WR as a data write signal, and data. Inputting the read signal / RD and the data bus mode / BUS_NODE signal accesses the combination control unit 10 which outputs the / DTACK signal, which is a signal used to interface the Motorola CPU, and the I ² C_ bus interface. It is seolge to be and, I ² C bus uses a serial data line when using the interface of the I ² C_SDA with, and I ² C_SCL used as a serial clock line when using the interface of the I ² C bus, and lower 7 bits of dATA to use for the data signal: and [60], and the signal input I ² C interface automatically increase control unit 20 that, with the combination control unit 10 / outputted from p_wr, / p_rd signal, the I ² C inter The device automatically increasing I ² C_rd an I ² of C_wr, data read signal data write signal output from the controller 20, the chip select signal is I ² C_cs and data address signal of writing the last data signal receiving I ^2, type C_addr signal / WR_En [] and a multiplexer 30 that outputs a final data read signal / RD_En [] to enable peripheral devices to be used in various CPU interface environments to increase their utilization and to a predetermined internal register. The effect is that you do not need a separate control circuit to access it.

Description

Interface unit accessible to all CPUs

The present invention relates to an interface device accessible to all CPUs, and in particular, to provide access to all CPUs, a predetermined device is provided so that all CPUs can be accessed without consuming peripheral devices.

In general, accessing Intel's widely used peripherals, such as INTEL, MOTOROLA, and Philips' CPUs, requires the interface of a device with different characteristics.

Fig. 1A is an input / output timing diagram showing a write signal state of an Intel CPU interface, Fig. 1B is an input / output timing diagram showing a read signal state of an Intel CPU interface, and Fig. 2A is a Motorola Fig. Fig. 2 (b) is an input / output timing diagram showing a read signal state of a Motorola CPU interface, and Fig. 3 is an input / output timing diagram of a Philips I2C-bus CPU interface.

That is, in the above-described configuration, the CPUs of INTEL and MOTOROLA are the most widely used standard interface devices, and the control signals are shown in Figs. 1 (a), (b) and 2 (a), (b). As shown in Fig. 2), similar timing relationships are shown.

The biggest difference between Intel's CPU and Motorola's CPU is that Intel's CPU provides read and write as separate signals, while Motorola's CPU provides a single signal, while the Motorola CPU delivers data from the other device. The / DTACK signal must be generated.

However, in order to access a conventional Intel CPU, a Motorola CPU, and a PHILIPS I ² C_ bus as described above, a predetermined peripheral device is used. In the case of an Intel CPU, a separate upper device is used. There is a problem in that data must be transmitted, and a separate signal is not directly connected to the counterpart device.

An object of the present invention is to solve the above-mentioned conventional problems, and in particular, to provide access to all CPU interfaces without having to provide a separate device for accessing a specific CPU.

In order to achieve the above object, the interface device accessible to all CPUs of the present invention is designed to be accessible to Intel's CPU and Motorola's CPU interface, and the chip select signal / CS and the data write signal / WR And a combination control unit for outputting a / RDACK signal, which is a signal used when interfacing the Motorola CPU, when / RD which is a data read signal and a / BUS_MODE signal which is a data bus mode; I C_ ² is designed to be accessible to the bus interface and, I ² and I ² C_SDA using a serial data line when using the interface of the C bus, used as a serial clock line when using the interface of the I ² C bus, I ² C_SCL, I ² C interface auto-increment control unit to which DATA [6: 0] signal used as the lower 7-bit data signal is input, / p_wr and / p_rd signals output from the combination control unit, and I ² and C interface automatically increase the I ² C_wr, data read signal with a data write signal output from the control unit I ² C_rd, the I ² C_cs and, in (I), wherein the final data writing signal receives the ² C_addr signal data address signal chip select signal And a multiplexer for outputting a / WR_En [] signal and a / RD_En [] signal as a final data read signal.

The interface devices accessible to all the CPUs of the present invention automatically increase / CS, / WR, / RD, / BUS_MODE signals, ADDR [6: 0], DATA [7] signals, and I ² C interfaces input to the combination control unit. When I ² C_SDA, I ² C_SCL, and DATA [6: 0] signals input to the control unit are input to the multiplexer, the / WR_En [] signal and / RD_En [] signal are outputted so that the peripheral device can be connected to various CPU interface environments. It can be applied to increase the utilization, and there is an effect that does not need a separate control circuit to access a predetermined internal register.

1 (a) is an input / output timing chart showing a write signal state of a general Intel CPU interface;

1 (b) is an input / output timing diagram showing a read signal state of a general Intel CPU interface;

2 (a) is an input / output timing diagram showing a write signal state of a typical Motorola CPU interface.

2 (b) is an input / output timing diagram showing a state of a read signal of a typical Motorola CPU interface;

Fig. 3 is an input / output timing diagram in addition to a general Philips I ² C_bus CPU interface.

Figure 4 is a functional block diagram showing the operating state of the interface device accessible to all the CPU of the present invention.

* Explanation of symbols for main parts of the drawings

10: combination control unit

20: I ² C_ bus interface auto increment control

30: multiplexing unit

Hereinafter, with reference to the accompanying drawings, the configuration and operation of the embodiment according to the technical concept of the interface device accessible to all the CPU of the present invention in detail as follows.

Example

The interface device accessible to all CPUs of the present invention is designed to be accessible to Intel's CPU and Motorola's CPU interface, and the chip select signal / CS, the data write signal / WR, and the data read signal / RD When the / BUS_MODE signal of the data bus mode is inputted, the combination control unit 10 which outputs the / DTACK signal which is a signal used when the Motorola CPU is interfaced, and the I ² C_ bus interface are designed to be accessible. and, I used as I ² C_SDA and I ² C_SCL, a data signal of lower 7 bits used as a serial clock line when using the interface of the I ² C bus to ² using a serial data line when using the interface of the C bus, I ² C interface automatic increase control unit 20 to which the DATA [6: 0] signal is input, the / p_wr and / p_rd signals output from the combination control unit 10, and the I ² C interface automatic increase control The data write signal I ² C_wr, the data read signal I ² C_rd, the chip select signal I ² C_cs, and the data address signal I ² C_addr are outputted from the unit 20. This embodiment includes a WR_En [] and a multiplexer 30 for outputting a / RD_En [] signal, which is a final data read signal.

Hereinafter, the operation of the device having the above configuration will be described in detail with reference to the accompanying drawings.

As mentioned above, / CS is used when the chip is operated to access data when it is low, and when it is not active when it is high, and it is used when it is active when it is high Is disabled, the / WR signal uses the / DS signal that is active-low on the Motorola bus interface, and the operation is active when it is active low, and the use is prohibited.The RD / WR signal is used when the motor bus is active. When used as a signal, / RD which operates the / WR signal when active low, and interfaces the CPU of Intel when it is low, and / BUS_MODE signal that interfaces the CPU of Motorola when the signal is high is input to the combination control unit 10.

In addition, it is used as a serial data line when I ² C_ bus is interfaced, and a full resistance is attached to prevent malfunctions from outside the chip based on the I ² C specification (SYSTEM PERFORMANCE ELALUATlON COOPERATIVE). When not in use, I ² C_SDA signal is processed as a voltage and I ² C_ bus is used as a serial clock line when interfacing.In accordance with the I ² C specification, it attaches a full resistance by preventing malfunctions from outside the chip. I ² C interface automatically uses I ² C_SLA signal, which handles voltage when not in use, and DATA [6: 0], which uses lower 7 bits of data as the slave address when I ² C_ bus is interfaced. Input to the increase control unit 20.

Further, a signal input to the combination control section 10, a signal input to the I ² C interface and the auto increment control section 20, ADDR [6: 0], which is an address bus, and DATA [7, which is higher bit data, are input. ] Signal is input to the multiplexer 30.

Also, this signal is used when the Motorola CPU is interfaced. The signal informs the CPU that data is transmitted according to the control signal of the CPU. The combination controller 10 outputs a malfunctioning / DTACK signal when it is active low. .

In addition, the combination controller 10 receives the data write signal / p_wr signal and the data read signal / p_rd signal from the combination controller 10 and the I ² C interface automatic increase control unit 20 to the multiplexer 30. The data write signal / I ² C_wr, the data read signal / I ² C_rd, the data select signal I ² C_c, and the data address I ² C_addr signal are input.

In addition, the signal input to the multiplexer 30 outputs the / WR_En [] signal, which is the data write signal, and the / RD_En [] data read signal, which are finally output.

As described above, an interface device accessible to all CPUs of the present invention, in particular, enables peripheral devices to be applied to various CPU interface environments to increase their utilization, and requires a separate control circuit to access a predetermined internal register. You do not have to do the effect.

Claims (10)

Designed to allow access to Intel's CPU and Motorola's CPU interfaces, inputting the chip select signal / CS, the data write signal / WR, the data read signal / RD, and the data bus mode / BUS_MODE signal It is designed to be able to access I ² C_ bus interface and combination control part that outputs / DTACK signal that is used when Motorola CPU is interfaced, and when using I ² C bus interface as serial data line. using screen is I ² C_SDA and, I ² using screen to direct the clock line when using the interface of the C bus I ² C_SCL and, dATA to use for the data signals of lower 7 bits: I ² which is [6: 0] signal input C interface automatic increase control unit, / p_wr, / p_rd signal output from the combination control unit, I ² C_wr, data read signal which is a data write signal output from the I ² C interface automatic increase control unit Input I ² C_rd, chip select signal I ² C_cs, data address signal I ² C_addr signal, and output the final data write signal / WR_En [] and the final data read signal / RD_En []. Interface device accessible to all the CPU, characterized in that the configuration including a multiplexer. The interface device as claimed in claim 1, wherein the / CS signal of the combination controller is accessible when data is accessed when the chip is low, and is prohibited when the chip is used when the chip is low. The CPU of claim 1, wherein the / WR signal of the combination control unit is operated in an active low state and is prohibited from being used in a high state, and is used as an active low / DS signal in a Motorola bus interface. 2 possible interface devices. The method of claim 1, wherein the / RD signal of the combination control unit operates in an active low state, is prohibited from being used when it is high, and uses an RD // WR signal when the Motorola bus interface is used. Interface device with access to all CPUs, operating with / WR signals when active low. The interface device of claim 1, wherein the / BUS_MODE signal of the combination controller interfaces with the CPU of Intel when the signal is low, and the Motorola CPU when the signal is high. The signal of claim 1, wherein the / DTACK signal output from the combination control unit is a signal used when the Motorola CPU is interfaced, and is a signal informing the CPU that data is transmitted according to a control signal of the CPU. Interface device accessible to all the CPU, characterized in that. According to claim 1, I ² C_SDA signal of the I ² C interface automatically increase control unit, I ² C to interface the bus uses a serial data line, based on the I ² C specification for preventing malfunction from the outside of the chip Interface device for access to all CPUs, characterized by a pull-up resistor and voltage handling when not in use. The I ² C_SCL signal of the I ² C interface auto-increment control unit is used as a serial clock line when interfacing the I ² C bus, and prevents a malfunction from occurring outside the chip based on the I ² C specification. Interface device accessible to all CPUs, characterized by a pull-up resistor for use and voltage handling when not in use. The method of claim 1, wherein the DATA [6: 0] signal of the I ² C interface auto-increment controller uses lower DATA [6: 0] as the slave address of the chip when the I ² C bus is interfaced. Interface device that can access all CPUs. The interface device according to claim 1, wherein the ADDR [6: 0] signal input to the multiplexer is used as an address bus.