KR19990010419A - Error detection device and checking method of error in digital system - Google Patents

Abstract

The present invention relates to an error detection device and an error occurrence checking method in a digital system, wherein the error detection device of the present invention is a clock that is currently using the respective error occurrence signals (ER07..0 to ERn7..0) inputted. Error detector 0 to error detector n (U0 to U1) for synchronizing to CLK to generate an actual error signal (ER_SYN0 (7..0) to ER_SYNn (7..0));

The actual error signals ER_SYN0 (7..0) to ER_SYNn (7..0) are classified according to the type of error based on the structure of the hardware device, inputted, and latched and stored according to a clock. Classification stores n (U3 to U4) for each error;

An error information output buffer U6 to which an output signal ER_INFO0 to ER_INFOn from the error classification storage 0 to error classification storage n (U3 to U4) is input;

The value of any one of the output signals ER_INFO0 to ER_INFOn is compared to the value of '0' for each of the output signals ER_INFO0 to ER_INFOn that are input to the error information output buffer U6 and simultaneously input. If appears

An error detection and interrupt generator U5 for promptly generating an interrupt signal INT to inform the microcomputer of an error occurrence;

When the interrupt signal INT is received, an address ADRn..0, AS or RD signal is detected to detect that an error has occurred and to access information about the error to the address decoder and the error information transmission controller U2. Micom;

Decode the address signal ADRn..0 to generate an ER_INFO_SELn..0 signal for selecting one error classification and storage among the error classification and storage 0 to error classification and storage n (U3 to U4). An address decoder and error information transmission controller U2;

An external error processing apparatus for receiving error information according to a communication protocol pre-selected from the micom to inform the user of the error;

A nonvolatile memory for storing the error information for each type;

A main microprocessor that executes an error processing program by accessing a predetermined region of the nonvolatile memory, which is previously promised, when the microcommunicator knows that an error has occurred from the micom;

In order to protect the nonvolatile memory, an arbiter is provided to prevent simultaneous access to a specific area of the nonvolatile memory.

Description

Error detection device and checking method of error in digital system

The present invention relates to an error detection device and an error occurrence checking method of a digital system, and in particular, a computer system that provides a system user with the ability to take immediate action by detecting and managing hardware errors or defects occurring in a computer or other system. An error detection apparatus and an error occurrence checking method are provided.

In a general computer system or a system with complicated electronic circuits, several hardware devices (boards) work together as one system.

In this case, each circuit executes each cycle, and when an error occurs due to a fault, it is not easy to find the cause, and it does not provide detailed defect information on it, which costs a lot of repairs and repairs.

In the conventional system, when an error occurs while the system is operating, the microprocessor or the controller is notified by an interrupt method and an exception is handled in the program to notify the system administrator to the console monitor or alarm.

In other words, if a specific hardware defect occurs during operation, only the result is not known, and thus there is no device dedicated to it.

Therefore, the error cause is traced to some error state or the light emitting diode is turned on according to the situation where a specific hardware defect occurs, and repair and recovery measures are taken.

This error handling method can be dealt with in a relatively simple device or system, but in a system composed of complex and integrated hardware, it is difficult to find the cause and find a defect and it is not easy to take systematic measures.

In the prior art, when an error occurs, it is common to store a status register or the like and notify the microprocessor to process it in a service routine.

Therefore, if an error occurs in the microprocessor itself or a double fault error that cannot be performed even by the service routine is no longer possible, it is difficult to grasp the detailed error element by simply indicating the status light emitting diode. It was.

Of course, it was difficult to immediately report an error because the status register was handled by a battery backup to check whether there was a previous error after reset or reboot.

Therefore, the present invention is to solve the above problems, when a specific hardware defect occurs, by setting up a dedicated device having a function for detecting an error, a control device for collecting more detailed error, and dedicated to the processing By providing a function of notifying error information by connecting to a device such as a main central processing unit or an external console, the purpose of the present invention is to provide an error processing device of a computer system that clarifies the cause of an error and quickly recovers. do.

1 is a schematic block diagram of an error detection apparatus according to the present invention;

Figure 2 is a detailed block diagram of the error detection and transmission module of the error detection apparatus according to the present invention.

In order to achieve the above object, the error detecting apparatus of the present invention synchronizes each of the input error generating signals ER07..0 to ERn7..0 with the clock CLK currently being used to produce the actual error signal ER_SYN07. Error detector 0 to error detector n (U0 to U1) for generating .0 to ER_SYNn7..0); The classification error storage unit 0 to the classification storage unit n, in which the actual error signals ER_SYN07..0 to ER_SYNn7..0 are input and classified according to the error type based on the structure of the hardware device, and are latched and stored according to a clock. (U3 to U4); An error information output buffer U6 to which an output signal ER_INFO0 to ER_INFOn from the error classification storage 0 to error classification storage n (U3 to U4) is input; The output information ER_INFO0 to ER_INFOn, which is input to the error information output buffer U6 and is input, is compared with a value of '0', and as a result of the comparison, any one of the output signals ER_INFO0 to ER_INFOn is compared. If any one value is '1', an error detection and interrupt generator (U5) for immediately generating an interrupt signal (INT) to inform the microcomputer of an error occurrence; When the interrupt signal INT is received, an address ADRn..0, AS or RD signal is detected to detect that an error has occurred and to access information about the error to the address decoder and the error information transmission controller U2. Micom; Decode the address signal ADRn..0 to generate an ER_INFO_SELn..0 signal for selecting an error classification and storage device among the error classification and storage devices 0 (U3 to U4). An address decoder and error information transmission controller U2; An external error processing apparatus for receiving error information according to a communication protocol pre-selected from the micom to inform the user of the error; A nonvolatile memory in which the error information is stored for each type; and an interrupt that the microcomputer detects that an error has occurred from the micom; A microprocessor; In order to protect the nonvolatile memory, an arbiter is provided to prevent simultaneous access to a specific area of the nonvolatile memory.

In addition, the error occurrence confirmation method of the present invention is a digital system comprising an error detector, a classification and storage for each error, an error detection and interrupt generator, an error information output buffer, an address decoder and an error information transmission controller,

A first step of inputting the error-specific classification and output signals of the storage unit to the error information output buffer; A second step of determining whether all information values input to the error information output buffer are '0' in the first step; A third step of determining that an error has not occurred if all the information values are '0' in the second step, and determining that an error has occurred if any one of all the information values is '1'; And a fourth step of notifying the occurrence of an error by immediately sending an interrupt to the microcomputer if an error occurs as a result of the determination in the third step.

In the present invention, if a separate controller has a problem, including the above-described error of the processor itself, the controller not only stores the generated error but also informs the interrupt controller and immediately reads the status register, which is an external console device. The system must be configured for immediate reporting, writing to nonvolatile memory, and informing the processor so that expected and detailed signals can be preset.

Therefore, if an error occurs, this is to notify the external system administrator or processor in any case to quickly repair or repair the system.

In a general hardware device, when an error occurs, the error signals are physically set in advance, and these signals are stored in a status register or connected to an external user by driving a light emitting diode.

However, in the present invention, the contents can be stored in the external nonvolatile memory as desired by the user. Also, by using a microcomputer, the contents can be connected to the external control device so as to analyze the detailed defect or error information and recover early. did.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

The apparatus for the present invention is largely composed of two block modules and one nonvolatile memory, each of which is composed of detailed blocks.

An error processing apparatus of a computer system according to the present invention will be described with reference to the main block diagram of FIG. 1 and the detailed circuit diagram of FIG.

First, in FIG. 1, a block indicated by a dotted line is an area for the present invention, and other parts correspond to additional blocks for providing a function of the present invention.

The description of the operation of the present invention has been described with reference to the dotted block.

When each signal is input to the error detector 0 to the error detector n (U0 to U1) according to the number of errors of the error occurrence signals ER07..0 to ERn7..0, the first synchronization is performed to the clock CLK currently in use. Let's do it.

That is, the error detectors U0 to U1 are synchronized with a means for filtering out a signal such as noise to output only actual error signals to generate ER_SYN07..0 to ER_SYNn7..0 signals.

Based on the structure of the original hardware device, these signals are classified by error type and input into error classification storage 0 through error storage n (U3 through U4), respectively, and are latched and stored according to a clock.

The signal thus stored is input to the error information output buffer U6 as output signals ER-INFO0 to ER-INFOn together with the storage.

At this time, if no error occurs, all are inputted as '0'. The signal is input to the error information output buffer U6 and to the error detection and interrupt generator U5.

Thereafter, the error detection and interrupt generator U5 compares these signals with a value of '0' and if any of them appear as '1', immediately generates an interrupt signal INT and transmits the signal to the microcomputer of FIG. Inform.

Of course, the interrupt is generated by only the first error signal and is cleared by the interrupt clear signal INT_CLR * described later.

Upon receiving this interrupt signal (INT), the microcomputer detects that an error has occurred and generates address (ADRn..0), AS, and RD signals to access information about the error to the address decoder and the error information transmission controller (U2). do.

Then, the address decoder and error information transmission controller U2 decodes the address signal and selects an ER_INFO_SELn for selecting a specific error classification and storage among the error classification and storage 0 to error classification and storage n (U3 to U4). Generates a ..0 signal.

This selection signal is used as a control signal for selecting the input signals ER_INFO0 to ER_INFOn of the error information output buffer to externally output an 8-bit data signal ER_DATA7..0.

Of course, the case where the U3, U4 is an 8-bit storage.

You can set this size as you like, but it's convenient to match your data size.

In the same way, the microcomputer reads the error data stored by type in all the error classification and storage units U3 to U4, and then generates signals ADRn..0, AS, and WR to clear the interrupt.

Then, an interrupt clear signal INT_CLR * is generated by the address decoder and the error information transfer controller U2 and input to the error detection and interrupt generator U5 to immediately stop the interrupt generation.

This prevents you from doing other exceptions while reading the error information first, so you can pinpoint the cause of the error.

The reset signal RST and the CLR * signal perform a function of clearing the occurrence of non-critical errors.

A non-critical error is an error that the system causes to know the components of the system during the self-diagnosis function of the system.

The reset signal RST and the CLR * signal are also decoded by a signal generated by the microcomputer.

Therefore, when the CLR * signal or the RST signal is generated, the error information for each type stored in the classification and error storage units U3 and U4 is erased to receive a new error.

In addition, since the CLR * signal is continuously generated until the signal for stopping CLR * signal generation (already assigned to an address) is transmitted from the microcomputer, the CLR * signal may be used to ignore an error occurring during initialization after power-on.

The error generated in this way may be notified to the user by transmitting error information according to a communication protocol previously selected by the microcomputer of FIG.

In addition, the error information is also stored in the nonvolatile memory and the main microprocessor is notified of an interrupt such as an interrupt. The main microprocessor then accesses a predetermined area of the non-volatile memory, which is promised, and executes a program for error processing.

In this case, the arbiter of FIG. 1 prevents simultaneous access to the nonvolatile memory to protect the nonvolatile memory.

As such, when an error occurs during system initialization, the error is classified and stored according to its type and notified to the external error processing device by the microcomputer, and at the same time, the main microprocessor provides a function to enable exception handling. Is the basic concept.

When an error occurs in a computer or other electronic device, it provides a function that is easy to use as a means of identifying the cause.

It can improve the service quality of the product by speeding up repair or recovery, and it can reduce the cost by easily finding the cause when the error occurs during the manufacturing process or during the process test, and can increase the competitiveness by being differentiated from similar products. .

In addition, the basic functions of the present invention can be easily applied to the design of computers and control equipment.

Claims (5)

N error detectors for generating an actual error signal by synchronizing each input error generating signal with a clock being used; N error classifiers and storage units for storing the actual error signals according to the structure of a hardware device, inputted by classification into error types, and latched and stored according to a clock; An error information output buffer to which an output signal from the classification and storage unit for each error is input; An error detection and interrupt generator that receives the output signal from the classification and storage unit for each error, generates an interrupt signal according to the value, and transmits the interrupt signal to the microcomputer; A microcomputer that detects that an error has occurred when receiving the interrupt signal and generates an address signal, an AS and an RD signal to access information about the error to the address decoder and the error information transmission controller; An address decoder and an error information transmission controller for decoding the address signal to generate a signal for selecting one of the error classification and the storage among the error classification and storage; An external error processing apparatus for receiving error information according to a communication protocol pre-selected from the micom to inform the user of the error; A nonvolatile memory for storing the error information for each type; A main microprocessor that executes an error processing program by accessing a predetermined region of the nonvolatile memory, which is previously promised, when the microcomputer detects that an error has occurred from the micom; And an arbiter for preventing simultaneous access to a specific area of the nonvolatile memory to protect the nonvolatile memory. The method of claim 1, wherein the address decoder and the error information transmission controller U2 generates an interrupt clear signal when the microcomputer generates a signal for clearing the interrupt, thereby causing the error detection and interrupt generator to stop generating the interrupt. Device for error detection in a digital system, characterized in that it does not allow the microcomputer to do other exceptional work while reading the error related information. The method of claim 1, wherein the address decoder and the error information transmission controller generate a reset signal and a CLR * signal decoded by a signal generated by the microcomputer, so that the error classification and storage can receive a new error. Error detection device in a digital system, characterized in that for deleting all the type of error information stored in the classification and storage. 4. The error detection apparatus of claim 3, wherein the CLR * signal is continuously generated until a signal assigned to an address is transmitted to stop the generation of the CLR * signal in the micom. A digital system comprising an error detector, an error classification and storage device, an error detection and interrupt generator, an error information output buffer, an address decoder, and an error information transmission controller, wherein the error signal is outputted from the error classification and storage device. A first step of inputting to an output buffer; A second step of determining whether all information values input to the error information output buffer are '0' in the first step; A third step of determining that an error has not occurred if all the information values are '0' in the second step, and determining that an error has occurred if any one of all the information values is '1'; And a fourth step of notifying the occurrence of an error by immediately sending an interrupt to the microcomputer if an error occurs as a result of the determination in the third step.