KR19990006217A - LCD module driving circuit - Google Patents

Abstract

The present invention relates to a liquid crystal module driving circuit for XGA for generating a pattern display signal for performing an AGING test and a panel test of the liquid crystal module.

The present invention provides a power supply voltage generator, a clock generator for generating a clock signal to generate a drive signal, a clock signal from the clock generator, and a vertical and horizontal synchronization signal and a data enable signal and an input. A drive signal generator for generating an enable signal, a drive switching connector for applying an internal voltage for driving the drive circuit, and an output signal of the drive signal generator are input, and an output signal is outputted by the output of the select switch. An output unit for selecting and outputting an output unit, an output terminal connected to an output signal of the output unit to a substrate of an interface circuit for driving LCM, a first check unit for checking a normal operation of the substrate and applying a predetermined signal to the output terminal Depending on whether the drive switch is operating or not, the voltage of 5V for IC driving and 12V for relay switching is applied to the interface board. The XGA driving circuit includes a second checker outputting the output terminal and a circuit protection unit allowing only one input when two inputs are applied to the internal and external inputs.

Description

LCD module driving circuit

The present invention relates to a driving circuit for driving a TFT LCM, and more particularly, to an XGA driving circuit used in an module assembly inline (ASS'YIN LINE) for performing an aging test and a panel test for measuring the reliability of an LCM. will be.

In general, the driving circuit is mounted on a pallet on a belt conveyor to flow into the aging chamber, and then 50 to 50 hours for 6 to 6 1/2 hours while lighting the black pattern or the black / white pattern on the panel. The test is carried out at 60 ° C.

An object of the present invention is to provide a driving circuit for XGA, which is a kind of pattern generator which is essential in such a test.

1 is a block diagram of an XGA drive circuit according to the present invention;

FIG. 2 is a detailed view inside the XGA driving circuit of FIG. 1; FIG.

Explanation of symbols for the main parts of the drawings

1: drive signal generator 2: drive circuit protection unit

3: output terminal 10: power supply voltage generator

20: clock generator 30: counter

40: data enable signal generator

50: horizontal sync signal generator 60: vertical sync signal generator

70: enable signal generator 80: power supply

90: data bus section 100: buffer section

110: first check unit 120: second check unit

130: first circuit protection unit 140: second circuit protection unit

The XGA driver circuit for achieving the above object of the present invention includes a power supply voltage generator of 5V and 3.3V, a clock generator for generating a clock signal to generate a drive signal, and a clock signal from the clock generator. A drive signal generator for generating vertical and horizontal synchronization signals, data enable signals, and enable signals as inputs; a first connector for drive switching for applying an internal voltage (5V) for driving the drive circuit; The output signal (VS, HS, DE, ENABL) of the drive signal generator is input, and the output unit selects and outputs an input signal by the output of the select switch SW, and the output signal of the output unit performs LCM driving. The output terminal connected to the substrate of the interface circuit and the signal from the output terminal are checked to apply a predetermined signal to the output terminal indicating whether the substrate is in normal operation. One check unit, a second check unit for outputting a voltage of 5V for IC driving to the interface board and a 12V voltage for relay switching to the output terminal according to whether the drive switch is operated, and two inputs for internal and external inputs When applied, it constitutes an XGA drive circuit including a circuit protector which allows only one input.

The operation of the XGA driving circuit having the above configuration will be briefly described. The driving switch is turned on to apply a voltage of 5 V for driving the IC to the driving circuit, and the select switch is driven according to the model of the LCM module. When the driving voltage is applied, the clock generator generates a clock having a frequency for driving the module for the XGA. Subsequently, after counting a clock for driving XGA, a horizontal synchronization signal is generated using the counted output, and a data enable signal is generated using the data enable generator. Next, counting is performed using the data enable signal as a clock signal for generating a vertical synchronization signal, and then a vertical synchronization signal is generated using the counting output. The enable generator generates the enable signal using the generated data enable signal and the vertical synchronization signal. The generated horizontal synchronizing signal, the vertical synchronizing signal, the enable signal and the clock signal are applied to the output unit, and then the input signal is selectively applied to the output terminal connected to the interface circuit for driving the LCM according to the output of the select switch. In addition, the vertical synchronization signal output of the output stage and the input power supply voltage are tested to check whether the driving circuit operates normally, and the result of the check is applied to the output stage. Thereafter, the output terminal applies the input signal to the interface circuit.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal module driving circuit for aging test according to an embodiment of the present invention. The aging test liquid crystal module driving circuit according to the embodiment of the present invention is a driving circuit for the aging test of the XGA class liquid crystal module having a resolution of 1024 × 768, a 65 MHz clock signal CLK and a data enable signal 512 CLK DE And a horizontal synchronization signal VS of 768H.

The aging test liquid crystal module driving circuit of the present invention includes a power supply voltage generator 10, a clock signal generator 20 for generating a clock signal to generate a drive signal, vertical and horizontal synchronization signals, and a data enable signal. A drive signal generator 1 for generating a signal, a first switch CN1 for applying an internal voltage for driving the drive circuit, and a cell switch SW for selecting an output signal according to an LCM model. ) And a data bus 90 for inputting the output signals VS, HS, DE, ENABL of the drive signal generator 1, and selecting and outputting the input signals by the output of the select switch SW. ), An output terminal CN2 connected to a substrate of an interface circuit for driving an LCM, a buffer 100 for transmitting the output of the data bus to the output terminal CN2, and a normal operation of the substrate to check a result of the output terminal. First body to output to (CN2) A second check unit 120 for outputting a voltage of 5V for IC driving and a voltage of 12V for relay switching to the output terminal CN2 to the interface board according to the operation of the control unit 110 and the driving switch; In order to protect the driving circuit when two inputs are applied to the external input, the driving circuit protection unit 2 is provided to allow only one input.

In addition, the driving signal generator 1 may include a counter 30 for counting a clock signal and generating a predetermined output signal, and a data input for generating a data enable signal by receiving the output of the counter 30. A vertical signal generator 40, a horizontal synchronization generator 50 for generating a horizontal synchronization signal by receiving the output of the counter 30, and a data enable signal are applied to generate a vertical synchronization signal. The enable signal generator 70 for generating an enable signal by inputting the output signal of the data enable signal generator 40 and the vertical sync signal generator; Each part for generating the power supply unit 80 for applying the power from the power generator 10 is configured.

In addition, the drive circuit protection part 2 is comprised from the 1st circuit protection part 130 for 5V, and the 2nd circuit protection part 140 for 12V.

On the other hand, the output unit 3 inputs the data buffer unit 90 for selecting and outputting an input signal by the select switch SW, and the output signal of the clock signal CLK and the data buffer unit 90 as input. It consists of a buffer unit 100 for applying a signal to the output terminal (CN2).

2 is a detailed circuit diagram of a liquid crystal module driving circuit according to an embodiment of the present invention.

1 and 2, the power supply voltage generator 10 inputs a 12V voltage applied from the outside to generate a 5V power supply voltage, a regulator RG11 including a heat sink, a capacitor C11-C14, and a diode ( A regulator (RG12), a capacitor (C15-C16), a variable resistor (R11) including a heat sink for generating a 3.3V power supply voltage by inputting a 5V power supply voltage generating means 11 constituted by D11) and a 12V voltage applied from the outside. ) And a 3.3V power supply voltage generating means 12 composed of a resistor R12.

The first connector CN1 for driving switching for applying an internal voltage, which is an output voltage of the power generator 10, to drive the driving circuit is provided. The select switch SW for selecting an output signal according to the LCM model includes the first and second switches S1 and S2 connected to the resistors SR1 and SR2 connected in parallel with the output voltage of the power generator 10. It is configured by connecting one end and connecting the other end to the ground potential. That is, the select switch SW2 is configured to turn on the first or second switches S1 and S2 according to the LCM module to be driven. Outputs a signal to select the LCM model.

The clock generator 20 inputs a 5V power supply voltage generated from the power supply voltage generator 10 to generate a XGA clock signal, for example, a 132.5 MHz clock signal CLK, and a 5V power supply voltage is applied thereto. Oscillator OSC21 and inverters IN21 and IN22.

The first counter unit 30, the data enable generator 40, the horizontal sync signal generator 50, the vertical sync signal generator 60, the enable signal generator 70, and the power supply unit 80 The furnace driving signal generator 1 is constituted.

A detailed circuit of the drive signal generator 1 will be described.

The 12-state binary ripple counter CNT31 that counts the clock signal CLK from the clock generator 20, and the sixth, eighth, and ninth outputs Ω6, Ω8, and Ω9 of the outputs of the counter CNT31. The first NAND gate NA31 that receives the outputs of 32 CLK, 128CLK and 512CLK, and the output signal of the first NAND gate NA31 are data input signals, and the preset terminal PR and the clear terminal CL ) Is connected to the power supply potential 5V, and the first D flip-flop FF31, which uses the output signal CLK of the clock generator 20 as the clock signal, and the inverted output (/ Ω) of the first D flip-flop FF31. ) Is connected to the reset terminal of the counter CNT331 to configure the counter unit 30.

The second NAND gate NA41, which receives the signals of 32CLK and 128CLK of the sixth and eighth outputs Ω6 and Ω8, and the outputs of the second NAND gate NA41 are output from the counter CNT31. 2D flip-flop (FF41), which is a signal and the preset terminal PR and the clear terminal CL are connected to a power supply potential 5V, and the output signal CLK of the generator 20 is a clock signal CR. ) And the output of the second D flip-flop FF41 as a preset signal PR, the data signal terminal D and the clock signal terminal CR are grounded, and the output of the first D flip-flop FF31. The data enable signal generator 40 is configured by a fifth D flip-flop FF42 for inputting the signal as a clear signal CL.

Among the outputs of the counter CNT31, the data of the third NAND gate NA51 and the output of the third NAND gate NA51 are input to 4CLK and 64CLK signals of the third and seventh outputs Ω3 and Ω7. A 3D flip-flop FF51 having an input and an output signal CLK of the clock generator 20 as a clock signal CK, and a preset terminal and a clear terminal connected to a power supply potential, and the 3D flip-flop ( The output Ω of FF51 is a preset input, the clock terminal and the input terminal are connected to the ground potential, and the output signal Ω of the 3D flip-flop FF51 is input as a clear signal CL. The 4D flip-flop FF34 constitutes a horizontal synchronizing signal generator 50.

The vertical synchronous signal generator 60 inputs a data enable signal DE, which is an output signal from the data enable signal generator 40, to output a vertical synchronous signal VS of 768H and a predetermined output signal VSYNC. Is to cause. A 12-state binary ripple counter CNT61 for inputting and counting the data enable signal DE from the data enable signal generator 30 and second and third of 12-bit outputs of the counter CNT61. A fourth NAND gate NA61 for inputting the output Ω2 and Ω3 signals, and a first end gate for inputting signals of the second and third outputs Ω2 and Ω3 among the 12-bit outputs of the counter CNT61. NA61), a second end gate NA62 that receives the sixth and ninth outputs Ω6 and Ω9 among the 12-bit outputs of the counter CNT61, and the first and second end gates AN61 and AN62. And a fifth NAND gate NA62 having the tenth output Ω10 of the output of the counter and the 12-bit output of the counter CNT61, and the second, third and tenth of the 12-bit output of the counter CNT61. And a sixth NAND gate NA63 for inputting the outputs Ω2, Ω3, and Ω10.

In addition, the horizontal synchronous signal generator 60 inputs an inverter IN61 for inverting the data enable signal DE from the data enable generator 40 and an output signal of the fourth NAND gate NA61. And the data enable signal inverted through the inverter IN61 using the 6D flip-flop FF61 having the inverted data enable signal as the clock signal and the output of the fifth NAND gate NA62 as the input signal. The data enable signal DE inverted through the inverter INV61 using the 7D flip-flop FF62 having the signal DE as a clock signal and the output of the sixth NAND gate NA63 as an input signal. The 8D flip-flop FF63, which is a clock signal, and the output Ω of the 8D flip-flop FF63 as a preset input, and the data input D and the clock CR are connected to a ground potential. And a ninth D flip flop FF64 having the output Ω of the seventh D flip flop FF62 as a clear input CL. All.

In addition, the inverted output (/ Ω) of the seventh D flip-flop FF62 is input as a reset signal of the counter CNT61. In addition, the output signal Ω of the 7D flip-flop FF62 is input as the clear signal CL, and the inverted output (/ Ω) of the 6D flip-flop FF61 is input as the preset signal PR and the data signal. (D) and a 10D flip-flop (FF65) connecting the clock signal CR to ground.

Meanwhile, the enable signal generator 70 generating the enable signal ENAB uses the output Ω of the ninth D flip-flop FF64 as a first input, and the data of the data enable generator 40 is generated. A third end gate AND3 having the enable signal DE as a second input is configured.

A resistor R81, an inverter IN81, a diode D81, and a capacitor C81 are connected to a power source applied as an output of the power generator 10 to form a power supply unit 80 to form a gate of each IC. Prevent overvoltage from flowing into the voltage input of the stage.

An output unit 3 comprising a data bus 90 and a buffer unit 100 for transmitting the output signals VS, HS, DE, ENABL and the clock signal CLK of the driving signal generator 1 to an interface circuit. ), The data bus 90 inputs the output signals VS, HS DE, ENABL of the drive signal generator 1, and selects and outputs an input signal by the output of the select switch SW. . That is, when the first switch S1 is turned on, the vertical synchronization signal and the horizontal synchronization signal are output through the output terminal. When the second switch S2 is turned on, the enable signal ENABL is outputted to the output terminal. Output through

The buffer unit 100 is connected to an output terminal of the data bus unit 90 to prevent a reverse load and to output a stable signal, and applies each output signal of the driving circuit to the output terminal CN2.

The first check unit 110 outputs the fourth end gate AND4 and the fourth end gate AND4 that perform a logical multiplication by inputting a 5V input signal and a vertical synchronization signal of the driving circuit by connecting the driving switch. Is connected to the base terminal, the collector is connected to the external power supply 12B, and the transistor (TR1) with the emitter connected to ground, resistor (R111) and capacitor (C111) is composed of the normal operation of the power supply voltage and the driving circuit. Check and input as the 12th terminal of the output terminal CN2.

The second checker 120 is an inverter IN121 for inputting a 5V input signal and an external signal source 5B by connecting a drive switch, and an output of the inverter IN121 as a base input, and an external voltage source to the collector. An external voltage on signal is generated using transistor TR1 and resistors R121 and R122 connected to 5B and grounded to the emitter terminal, and input to the eleventh terminal of the output terminal. In addition, 5V by the drive switch connection is used as the gate input, and the external power supply 12B is connected to the drain terminal, and the relay on signal is supplied by using the third transistor TR3 and the resistors R123-R124 whose source terminals are connected to ground. It generates and outputs to the tenth terminal of the output terminal (CN2).

The driving circuit protection unit 2 is to protect the circuit by blocking one of them when the same voltage is applied from the outside and the inside at the same time, and the internal 12V voltage through the connector CN4 and the connector CN5. First protection means 130 composed of a relay RL131, a comparator COM131 and a transistor TR5, and a plurality of resistors for cutting off the internal 12V voltage and outputting the external 12V voltage when the voltage is applied simultaneously, and 5V. It consists of a relay RL141, a comparator COM141 and a second protective means 140 composed of a plurality of resistors and a resistor for outputting an external 5B power supply voltage when an internal voltage and a 5B external voltage are simultaneously applied. .

Referring to the operation of the XGA driving circuit having the above-described circuit configuration, the power supply voltage generator 10 having an external voltage of 12V as an input outputs a voltage of 5V and a voltage of 3.3V for the operation of the driving circuit. . At this time, the 5V power supply voltage generator 11 of the power supply voltage generator 10 generates a power supply voltage of 5V by emitting a 7V voltage as heat using a heat sink. In the same way, the 3.3V power supply voltage generator 12 emits 8.5V of heat as heat through the heat sink and outputs a 3.3V power supply voltage.

The first connector CN1 operates as a driving switch, and applies a power supply voltage of 5V into the driving circuit in the on state for driving. The select switch SW turns on the first or second switches S1 and S2 of the select switch SW2 according to the module of the LCM to be driven.

The clock generator 20 receiving the power supply voltage 5V operates the oscillator OSC21 for driving the XGA driving circuit to generate a clock signal CLK having a 132.5 MHz frequency.

The clock signal CLK is applied as a clock signal of the counter unit 30 of the drive signal generator 1 through the inverter IN21, and the output signal of the inverter IN21 is passed through the inverter IN22, and then the data in The signal is applied to the enable signal generator 40 and the horizontal synchronizing signal generator 50 to input a clock for generating the horizontal synchronizing signal HS and the data enable signal DE necessary for operating the driving circuit.

Subsequently, an operation for generating the horizontal synchronization signal HS and the data enable signal DE is performed. That is, the 5V power applied to the drive signal generator 1 passes through the power supply 80 and the counter 30, the data enable signal generator 40, the horizontal sync signal generator 50, and the vertical sync. It is applied to the signal generator 60.

The binary ripple counter CNT31 of the counter 30 counts the input clock signal CLK to generate outputs Ω 1-Ω 2. When the output of the first NAND gate NA31 which inputs the outputs Ω6, Ω8, and Ω10 of the counter CNT31 is input to the first D flip-flop FF31, the preset PR and the clear input CL are input. Since the state is 5V, the output Ω of the first D flip-flop FF31 is output as a signal of 672 CLK. The inverting output (/ Ω) of the 1D flip-flop FF31 is applied to the reset signal RST of the counter CNT31 so that the counter CNT31 counts up to 672CLK. In addition, the first D flip-flop FF31 output Ω of 672CLK includes the fifth D flip-flop FF42 of the data enable signal generator 40 and the fourth D flip-flop FF52 of the horizontal sync signal generator 50. It is input to the clear signal CL.

When the output of the second NAND gate NA41 which inputs the sixth and eighth outputs Ω6 and Ω8 of the counter CNT31 is applied to the second D flip-flop FF41, the preset PR and the clear input are applied. Since CL is 5V, the 2D flip-flop FF41 outputs a signal of 160 CLK. Since the output of the 2D flip-flop FF41 is applied to the preset terminal PR of the 5D flip-flop FF42, the 5D flip-flop FF42 generates an output signal DE of 512CLK.

In addition, an output of the third NAND gate NA51 that receives the third and seventh outputs Ω3 and Ω7 of the counter CNT31 is applied to the third D flip-flop FF33. Since the preset PR clear input CL of the 3D flip-flop FF51 is 5V, the input signal from the input third NAND gate NA51 is applied to the preset PR of the 4D flip-flop FF52. do. The 4D flip-flop FF52 is a horizontal synchronization signal of 1024 H by the clear signal CL inputted from the first D flip-flop FF31 and the preset signal PR inputted from the 3D flip-flop FF33. HS).

In order to generate the vertical synchronization signal VS, the data enable signal DE is applied as a clock signal of the counter CNT61 in the vertical synchronization signal generator 60 to which the counter CN61 is output. To generate Ω12). The fourth NAND gate NA61 having the second and third outputs Ω2 and Ω3 of the counter CN61 applies the output of 6H to the data input terminal of the 6D flip-flop FF61. Since 5V is applied as the preset and clear signal CL, the signal of the fourth NAND gate NA61 is output to the output terminal in the 6D flip-flop FF61, and the inverted data of the 6D flip-flop FF61 is applied. The output signal / is applied as the preset signal of the 10D flip-flop FF65.

The 6H output of the first NAND gate NA61 which inputs the second and third outputs Ω2 and Ω3 of the counter CNT61 is the first input signal, and the sixth and ninth of the counter CNT61. The 288H output of the second NAND gate AN62 having the outputs 46 and 9 as an input is used as the second input signal, and the 512H output Ω10 of the counter CN61 is used as the third input signal. NA62). The 806H output (Ω) of the fifth NAND gate NA62 is applied as the clear signal CL of the 10D flip-flop FF65, and the inverted output (/ Ω) is applied as the reset signal of the counter CN61. Only count up to 806H. In the 10D flip-flop FF65, the 800H vertical synchronization signal VS is output by the input 6H preset signal and the 806H clear signal CL.

An output of 38H of the sixth NAND gate that receives the second, third, and sixth outputs Ω2, Ω3, and V6 of the counter CN61 is applied to the data input of the 8D flip-flop FF63, and is free. Since the 5V signal is applied to the set and clear inputs CL, the output Ω of the 8D flip-flop FF63 is changed by the input. The 38H output Ω of the 8D flip-flop FF63 is applied as the preset signal of the 9D flip-flop FF64, and the output signal of 768H is applied according to the clear signal of 806H applied from the 7D flip-flop FF62. VSYC).

The enable signal generation unit 70 including the output signal VSYC and the third enable gate AND3 that performs the logical multiplication by using the data enable signal DE is input to the two input signals VSYC DE. The AND is performed to generate the enable signal ENABL.

In the output unit 3 which receives the output signals HS, VS, ENABL of the drive signal generator 1, the data bus 90 drives the switches S1, S2 of the select switch SW. Outputs the input signal according to the state. That is, when the first switch of the select switch SW2 is turned on, the horizontal synchronization signal HS and the horizontal synchronization signal VS are applied to the buffer unit 100. When the second switch of the select switch SW2 is turned on, the enable signal ENABL of the enable generator 70 is applied to the buffer unit 100.

The vertical synchronization signal VS is applied to the first buffer BU101 of the buffer unit 100, the horizontal synchronization signal HS or the enable signal ENABLE is applied to the second buffer BU102, and the third buffer. The clock signal CLK is input to BU103. At this time, the buffer unit 100 is connected to the ninth, eighth, and fifth terminals of the output terminal CN2 for applying the signals VS, HS, ENABL and the clock signal CLK applied from the data bus to the interface circuit. On the other hand, the vertical synchronization signal VS is applied to the fourth end gate AND4 of the first check unit.

The fourth end gate AND4 of the first checker 110 performs a logical multiplication of the 5V signal and the vertical synchronizing signal VS, which are the output CN24 of the output terminal CN2, to the base of the transistor TR1. That is, the transistor TR1 is turned on only when the driving switch SW1 is turned on and a normal 5V signal is applied and the driving circuit performs a normal operation to output an accurate vertical synchronization signal. A 0 V signal is input to the terminal 12. By this signal, the interface circuit for driving the LCM recognizes the operation of the normal driving circuit, and the horizontal and vertical synchronization signals HS and VS generated by the driving circuit and the data enable signal DE are applied to the LCM module. The LCM module is operated by the driving circuit.

On the other hand, if it is not normal, a 12V signal is input to the terminal 12 of the output terminal CN2. Accordingly, an external input signal input to the interface circuit is applied to the LCM module.

When the first checker CN1 for driving switching is turned on and the normal signal is supplied, the second checker 120 turns off the transistor TR2 and turns on the transistor T32 so that each transistor TR2 is turned on. Signals of the IC driving voltages 5V and 0V are output from the collector terminal of TR3 to the eleventh and tenth terminals 11 and 10 of the connector CN2. When the first connector CN1 is turned off, a signal of 0 V and a relay driving voltage 12 V is applied to the terminals 11 and 10 of the connector CN2.

Therefore, in the interface circuit, the same operation as that of the first check unit 110 is performed. When the driving circuit is normally operated, the output signal of the driving circuit is applied to the LCM module.

In the liquid crystal module driving circuit of the present invention, when the external 12B and internal 12V voltages are simultaneously applied through the circuit code unit 90, the transistor Ω91 for driving the relay RL91 is driven by the output of the comparator COM91. If the external 12B is selected to protect the circuit, and the external 5B and the internal 5V are applied, the relay RL92 driving transistor Ω91 is driven by the output of the comparator COM92 so that the external 5B is selected. Will be protected.

According to the XGA driving circuit having the configuration according to the present invention, the driving switch is turned on to apply a voltage of 5 V for driving the IC to the driving circuit, and the select switch is driven according to the model of the LCM module. Subsequently, after counting a clock for driving XGA, a horizontal synchronization signal is generated using the counted output, and a data enable signal is generated using the data enable generator. Subsequently, the vertical enable signal is generated using the data enable signal as a clock signal for generating the vertical sync signal. The enable generator generates the enable signal using the generated data enable signal and the vertical synchronization signal. After the output signal of the driving signal generator is applied to the output unit, the input signal is selectively applied to the output terminal connected to the interface circuit for driving the LCM according to the output of the select switch. In addition, the vertical synchronization signal output of the output stage and the input power supply voltage are tested to check whether the driving circuit operates normally, and the result of the check is applied to the output stage.

Accordingly, a driving circuit for driving the XGA class liquid crystal module is formed, and the signal generated by the driving circuit is applied to the interface circuit using the output terminal for the interface to drive the liquid crystal module.

Claims (23)

In the liquid crystal module driving circuit for XGA, which is a pattern generator for performing an aging test and a panel test of the liquid crystal module, A voltage generator for supplying a voltage to the drive circuit; A clock generator for generating a clock signal to generate a driving signal; A drive signal generator for inputting a clock signal from the clock generator to generate vertical and horizontal synchronization signals, a data enable signal, and an enable signal; An output unit for inputting output signals VS, HS, DE, and ENABL of the driving signal generator, and selecting and outputting an input signal by an output of a select switch; An output terminal connected to an output signal of the output unit to a substrate of an interface circuit for driving an LCM; A first check unit which checks a normal operation of the substrate in the output signal of the output unit and applies a predetermined signal to the output terminal; A second check part which outputs a voltage of 5V for IC driving and a voltage of 12V for relay driving to the output terminal according to whether the driving switch is operated; An XGA-class liquid crystal module driving circuit comprising a circuit protection unit for protecting the driving circuit. 2. The liquid crystal module driving circuit according to claim 1, wherein the power generating unit generates a 5V voltage source and a 3.3V voltage for driving a driving circuit. The power generator of claim 2, wherein the power generator generates voltages of 5V and 3.3V. 5V power supply voltage generating means comprising a first regulator including a heat sink, first and second capacitors, and a first diode for inputting a 12V voltage applied from the outside to generate a 5V power supply voltage; A 3.3V power supply voltage generating means comprising a second regulator including a heat sink, a third to fifth capacitor, a first variable resistor and a second resistor for inputting a 12V voltage applied from the outside to generate a 3.3V power supply voltage. A liquid crystal module driving circuit characterized in that. 2. The liquid crystal module driving circuit according to claim 1, further comprising a select switch for outputting a control signal for selectively outputting the input signal of the output terminal according to the type of the module to drive the input signal. The method of claim 1, wherein the driving signal generator A counter unit for counting a clock signal to generate a predetermined output signal; A data enable signal generator for receiving the output of the counter to generate a data enable signal; A horizontal synchronization generator for generating a horizontal synchronization signal by receiving the output of the counter; A vertical sync generator for receiving the data enable signal and generating a vertical sync signal; And an enable signal generator configured to generate an enable signal by inputting output signals of the data enable signal generator and the vertical sync signal generator. The method of claim 5, wherein the counter unit A first counter counting a clock signal from the clock generator; A first NAND gate which receives the sixth, eighth and ninth output signals of the first counter; A first D flip-flop having an output signal of the first NAND gate as a data input signal, a preset terminal and a clear terminal connected to a power supply potential, and an output signal of a clock generator being a clock signal; And outputting the first D flip-flop to a reset terminal of the first counter to reset the first counter part. The method of claim 5, wherein the data enable generation unit A second NAND gate having a sixth and eighth output signal as an input among the outputs of the first counter; A second D flip-flop having an output of the second NAND gate as a data signal, a preset terminal and a clear terminal connected to a power supply potential, and an output signal of a clock generator as a clock signal; And a fifth 5D flip-flop for inputting the output of the 2D flip-flop as a preset signal, the data signal terminal and the clock signal terminal being grounded, and inputting the output of the 1D flip-flop as a clear signal. Driving circuit. The method of claim 5, wherein the horizontal synchronization generating unit A third NAND gate which receives the third and seventh output signals of the first counter; A third D flip-flop having an output of the third NAND gate as a data input, an output signal of the clock generator as a clock signal, and a preset terminal and a clear terminal connected to a power supply potential; The output of the 3D flip-flop is a preset input, the clock terminal and the input terminal is connected to the ground potential, characterized in that consisting of a 4D flip-flop to input the output signal of the 3D flip-flop as a clear signal Liquid crystal module driving circuit. The method of claim 5, wherein the vertical synchronization signal generator And a data enable signal, which is an output signal from the data enable signal generator, to generate a vertical synchronization signal of 768H and a predetermined output signal. The method of claim 9, wherein the vertical synchronization signal generating unit A second counter for inputting and counting an output signal from the data enable signal generator; A fourth NAND gate for inputting second and third output signals of the second counter; A first end gate for inputting second and third output signals of the 12-bit output of the second counter; A second end gate configured as a sixth and ninth output signal inputs among the 12-bit outputs of the second counter; A fifth NAND gate having an input of a tenth output signal of an output of the first and second end gates and a 12-bit output of the second counter; A sixth NAND gate configured to input second, third and tenth output signals of the second counter; A fifth inverter for inverting the output signal from the data enable generator; A sixth flip-flop having an output of the fourth NAND gate as an input signal and a reversed data enable signal as a clock signal; A seventh flip-flop that uses the output of the fifth NAND gate as an input signal and uses the data enable signal inverted through the fifth inverter as a clock signal; An eighth flip-flop that uses the output of the sixth NAND gate as an input signal and uses the data enable signal inverted through the fifth inverter as a clock signal; A ninth flip flop for outputting the eighth flip flop as a preset input, a data input and a clock connected to a ground potential, and a seventh flip flop for outputting the seventh flip flop; Input the inverted output of the 7D flip-flop as the reset signal of the second counter, input the output signal of the 7D flip-flop as the clear signal, input the inverted output of the 6D flip-flop as the preset signal, and A liquid crystal module drive circuit comprising a 10D flip-flop connected to a clock signal to ground. The enable signal generator of claim 5, wherein the enable signal generator generates the enable signal. And a third end gate having the output of the ninth flip-flop as a first input and the data enable signal of the data enable generator as a second input. The liquid crystal module driving circuit according to claim 1, wherein the driving circuit protection unit comprises a first circuit protection unit for 12V and a second circuit protection unit for 5V. The method of claim 12, wherein the first circuit protection unit At the same time, when the same voltage is applied from the outside and the inside, it is to protect the circuit by blocking one of them.If the internal 12V voltage is simultaneously applied through the first connector and the internal 12V voltage is applied simultaneously, And a relay, a comparator, a fifth transistor, and a plurality of resistors, for blocking and outputting an external 12V voltage. The method of claim 12, wherein the second circuit protection unit A liquid crystal module driving circuit comprising a relay, a comparator and a sixth transistor and a plurality of resistors for outputting an external 5B power supply voltage when 5V internal voltage and 5B external voltage are simultaneously applied. The display apparatus of claim 1, wherein the output unit comprises: a data buffer unit configured to select and output an input signal according to a selection signal of a select switch; A liquid crystal module driving circuit comprising: a buffer unit for applying a clock signal and an output signal of the data buffer unit as inputs and applying an input signal to an output terminal. 16. The liquid crystal module driving circuit according to claim 4 or 15, wherein the selection signal of the select switch is determined by the type of the module to be driven and selects and outputs an input signal of the data bus. The method of claim 1, wherein the first check unit A fourth end gate performing an AND operation on the input signal of 5V by the connection of the driving switch and the vertical synchronizing signal of the driving circuit as an input; A first transistor connecting an output of the fourth end gate to the base terminal, a collector connected to an external power supply of 12B, and an emitter connected to ground; A liquid crystal module driving circuit comprising a fifth resistor and a fourth capacitor for checking a normal operation of a power supply voltage and a driving circuit, and inputting a predetermined signal to the twelfth terminal of an output terminal. 18. The liquid crystal module driving circuit of claim 17, wherein the predetermined signal is generated as a signal of 0V only when a normal 5V signal is applied and the driving circuit performs a normal operation to output an accurate vertical synchronization signal. in. The method of claim 1, wherein the second check unit A sixth inverter that uses a 5V input signal and a 5B external signal source by connecting a drive switch, and an output of the sixth inverter as a base input, connects an external voltage source of 5B to the collector, and grounds the emitter terminal. The second transistor, Using the eighth and ninth resistors, a predetermined first signal is generated and output to the eleventh terminal of the output terminal; A third transistor having 5V as a gate input and connecting an external power supply of 12B to the drain terminal and having a source terminal connected to ground; And a predetermined second signal is generated using the tenth through twelfth resistors and output to the tenth terminal of the output terminal. 20. The method of claim 19, wherein the predetermined first and second signals are When the normal 5V is supplied, the second transistor is turned off and the third transistor is turned on, so it is output to the 11th and 10th terminals of the output terminal with signals of IC driving voltage 5V and 0V from the collector terminal of each transistor. And, when there is no input signal of 5V, generated as a first signal of 0V and a second signal of 12V for relay driving voltage. 2. The liquid crystal module driving circuit according to claim 1, wherein the output unit has a function of transmitting an output signal of the first and second check units and a signal generated inside the driving circuit to an interface circuit. The method of claim 1, wherein the clock generator A liquid crystal module driving circuit for generating a XGA clock signal by inputting a 5V power supply voltage generated from the power supply voltage generator, comprising an oscillator to which a 5V power supply voltage is applied and two inverters. The liquid crystal module driving circuit of claim 1, wherein the clock generator generates a clock signal having a frequency of 65 MHz for driving the XGA class.