KR19990006013A - Row Decoder with Hierarchical Wordline Structure - Google Patents

Abstract

The present invention reduces the bridge rate due to process problems by reducing the main word line spacing and reducing the power supply voltage of the decoder higher than the conventional spacing, while maintaining the potential of the sub-word line sufficiently. To provide a row decoder of a line structure.

To this end, the present invention provides a decoding unit for selecting a predetermined word line in response to an input of a decoding address, and a plurality of sub-word lines connected in parallel to the output lines of the decoding unit, the output signal and the word line boosting signal. And a sub-word line clearing unit for controlling the driving of the sub-word line driver in order to clear a non-selected sub-word line among the plurality of sub-word lines. As a single main word line is used, the spacing of the main word lines is doubled compared to the conventional method of using a pair of main word lines, thereby significantly reducing the probability of malfunction due to process problems. It is possible to increase the yield by improving the operation at a low power supply voltage.

Description

Row Decoder with Hierarchical Word Line Structure

The present invention relates to a row decoder of a hierarchical word line structure, and more particularly, to reduce the spacing of the main word lines of the row decoder of the hierarchical word line structure by about two times as compared to the row decoder of the conventional structure. The present invention relates to a row decoder having a hierarchical word line structure to reduce the probability of a malfunction occurring due to this.

In general, since a word line in a memory cell array is a gate of a cell transistor, the word line has a large capacitance value and has a relatively high resistance of polysilicon, thereby causing a large signal delay. To solve this problem, a simple division of word lines is performed to insert and drive more row decoders and word line drivers. In this case, an additional decoder increases the chip area.

Therefore, after the 1M DRAM era, a convenient polysilicon is used as the gate material, and low-resistance aluminum is placed in parallel and the word line poly is stitched every 64 to 128 cells. Word line strapping structure that connects Line Poly) and aluminum wiring is widely used.

However, when it reaches 64M or 256M, it is very difficult to place aluminum (metal 1) on all word lines from the process point of view, and even if placed, the aluminum wire becomes very thin, so the effect of reducing wiring delay is not so great.

In order to solve this problem, hierarchical word line structure has been adopted since 64M class. The concept of the hierarchical word line structure is to divide the word line into appropriate lengths to make a sub-word line (SWL). One row decoder and a word line driver drive these sub-word lines SWL.

A row decoder employing the concept of the conventional hierarchical word line structure will now be described with reference to FIG. 1.

The row decoder of the conventional hierarchical word line structure shown in FIG. 1 includes a plurality of sub-words divided at regular intervals into a pair of complementary main word lines MWLB and MWLB which are output lines of the main row decoder 10. Line drivers 12, 14-n are connected to drive the corresponding sub-word line SWL.

Here, the main row decoder 10 typically includes a PMOS transistor MP1 and a plurality of NMOS transistors MN1, MN2, and MN3 connected in series between a power supply voltage terminal Vcc and a ground voltage terminal. The PMOS transistor MP1 is connected in parallel and the gate is composed of a PMOS transistor MP2 connected to the output side of the inverter IV1 connected to the drain (ie, the output node) of the PMOS transistor MP1. A precharge signal pre is applied to the gate of the PMOS transistor MP1, and a decoding signal (ai, aj) from an address decoding circuit (not shown) is applied to the gates of the plurality of NMOS transistors MN1, MN2, and MN3. and a) are applied respectively.

The sub-word line driver 12 refers to a driver that drives the sub-word lines SWL1 <0> and SWL1 <1> of low addresses 0 and 1 in the first sub-array. The line driver 14 means a driver for driving the sub-word lines SWL1 &lt; 2 &gt; and SWL1 &lt; 3 &gt; at row addresses 2 and 3 in the first sub-array. The driver drives the sub-word lines SWLN <2> and SWLN <3> at row addresses 2 and 3 in the n-th sub-array.

In addition, since the internal circuit configurations of the sub-word line drivers 12, 14 to n are the same, the sub-word line SWL1 &lt; 0 &gt; is driven in the sub-word line driver 12 here. Only the configuration of the driver will be described.

A driver for driving the sub-word line SWL1 &lt; 0 &gt; is connected between the main word line MWL and the first node A and an NMOS transistor for access to which a power supply voltage Vcc is applied as a gate. A pull-up connected between the SM1 and the boosting signal (px1 + &lt; 0 &gt;) line and the sub-word line (SWL1 &lt; 0 &gt; a pull-down connected between the NMOS transistor SM2 and the sub-word line SWL1 &lt; 0 &gt; and the ground voltage Vss, and a gate connected to the inverted main word line MWLB. Is constituted by the NMOS transistor SM3.

The operation of the driver for driving the conventional sub-word line SWL1 &lt; 0 &gt; according to the above-described configuration will be described below.

When the voltage of the main word line MWL is high, the gate voltage of the NMOS transistor SM1 is also high, so when the voltage of the first node A rises and reaches Vcc-Vtn, the NMOS transistor SM1 is turned off and the first voltage is reached. The node A becomes an isolated node having a voltage of Vcc-Vtn and is disconnected from both the outside and the connection point. After the predetermined time is delayed in this state, if the high voltage of the word line boosting signal px1 + &lt; 0 &gt; is applied to the drain of the NMOS transistor SM2, the gate voltage is Vcc-Vtn, so the sub-word line SWL1 &lt; 0>) begins to rise. When the voltage of the sub-word line SWL1 &lt; 0 &gt; increases, the potential of the first node A also increases due to the overlap capacitance between the gate and source of the NMOS transistor SM2, so that the voltage rises. (Self-Bootstrapping). Therefore, since the potential of the first node A rises above Vcc + 2Vt (Vt is a threshold voltage), all of the Vcc + Vtn voltages are transferred to the sub-word line SWL1 <0>. At this time, the NMOS transistor SM1 remains turned off because the gate voltage is tied to Vcc.

However, if the above-described conventional circuit operates at a low power supply voltage, the potential to be precharged to the first node A is low, so that bootstrap phenomenon does not sufficiently occur. Thus, the sub-word line SWL1 <0> The potential of the word line boosting signal px1 + &lt; 0 &gt; This results in a disastrous event where no full potential transfer occurs when reading the cell's data, or when the data is stored back in the cell, making it impossible to store the full potential.

In addition, the row decoder of the conventional hierarchical word line structure described above shows that adjacent main word lines MWL and MWLB of this structure always have opposite polarities. When a portion (e.g., my or my portion) is attached by a defect, there is a current flow between the two main word lines, which increases the standby current. In this case, recovery by the normal repair method is impossible.

Accordingly, the present invention has been made to solve the above-described conventional problems, and the main word line interval is alleviated more than the conventional interval, and the power supply voltage of the decoder is made higher, thereby reducing the bridge ratio due to process problems and sub The object is to provide a row decoder of a hierarchical word line structure in which the potential of the word line is sufficiently maintained.

According to a preferred embodiment of the present invention to achieve the above object, an inverter for inverting the output signal of the main row decoder, the internal power supply voltage is set higher than the external power supply voltage; An inverter element connected between the output line of the inverter and the corresponding sub-word line to invert the output signal of the inverter, and a clear driving element for leveling the potential of the unselected sub-word line among the plurality of sub-word lines A plurality of sub-word line drivers each having a plurality of sub-word lines connected to the output lines of the inverter in parallel to a high voltage state according to the output signal and the word line boosting signal of the inverter; A row decoder having a hierarchical word line structure including a sub-word line clearing unit for controlling driving of a corresponding sub-word line driver to clear an unselected sub-word line among the plurality of sub-word lines is provided.

1 is a circuit diagram of a row decoder of a general hierarchical word line structure;

FIG. 2 is a diagram adopted to describe a problem caused by a bridge between adjacent main word lines in the row decoder illustrated in FIG. 1;

3 is a circuit diagram of a row decoder of a hierarchical word line structure according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10: main row decoder, 12, 14, 16, 18, 20, 22 (K-1) n, Kn, n: sub-word line driver, 50: sub-word line clear section

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a circuit diagram of a row decoder of a hierarchical word line structure according to an exemplary embodiment of the present invention. The same components as those described in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

An embodiment of the present invention is connected to an output terminal of the main row decoder 10 and inverts the output signal of the main row decoder 10 in parallel with an inverter IV3 and an output line of the inverter IV3 in parallel. The plurality of sub-word lines SWL1 <0> to SWLN <3> according to the output signal of the inverter IV3 and the word line boosting signals px + 1 <0> to px + N <3>. Sub-words to clear unselected sub-word lines among the plurality of sub-word line drivers 16 to Kn and the plurality of sub-word lines SWL1 &lt; 0 &gt; SWLN &lt; 3 &gt; And a sub-word line clear section 50 for controlling the driving of the line driver.

Here, the power supply voltage Vpp of the main row decoder 10 is a power supply voltage made higher than an external power supply voltage, and the output line of the inverter IV3 is wired with a metal layer and passes through a cell array. It is a word line (MWL).

Each of the sub-word line drivers 16 to Kn includes an output line (ie, a main word line MWL) of the inverter IV3 and a corresponding sub-word line SWL1 <0> to SWLN <3>. And an inverter element connected between any one of the lines inverting the output signal of the inverter IV3 and a potential of an unselected sub-word line according to a signal from the sub-word line clearing section 50, at a ground level. It consists of a clear drive element.

In the embodiment of the present invention, since the internal circuit design of each of the sub-word line drivers 16 to Kn is the same, only the configuration in the sub-word line driver 16 will be described.

The inverter element in the sub-word line driver 16 is composed of a pull-up PMOS transistor MP3 and a pull-down NMOS transistor MN4. ) And the gate of the NMOS transistor MN4 are commonly connected to the main word line MWL, and a word line boosting signal px1 + &lt; 0 &gt; is applied to a source of the PMOS transistor MP3 and the PMOS transistor MN4 has a gate. The drain of the transistor MP3 is connected to the drain of the NMOS transistor MN4 while being connected to the cell via the sub word line SWL1 &lt; 0 &gt;, and the source of the NMOS transistor MN4 is grounded.

The well of the PMOS transistor MP3 may be connected to the internal power supply voltage Vpp or to a source.

On the other hand, the clear driving element in the sub-word line driver 16 has an NMOS type having a drain connected to the sub-word line SWL1 &lt; 0 &gt; and a source grounded so as to be connected in parallel with the NMOS transistor MN4. As the transistor MN5, the threshold voltage of the NMOS transistor MN5 is preferably 0.3 V or less.

In addition, the sub-word line clearing unit 50 in the embodiment of the present invention is disposed outside the cell array, and a plurality of word line clear signals ((s) so as to control all the sub-word line drivers 16 to Kn in common). For example, wlc <0>, wlc <1>, wlc <2>, wlc <3> are outputted, and the lines of the word line clear signal wlc <0> are all sub-word lines SWL1 <0. NMOS transistors (i.e., sub-) in the sub-word line drivers 16 to Kn so that the potentials of SWL2 <0>, SWL3 <0>, SWLN <0> can be grounded. In the word line driver 16, it is connected to the gate of the NMOS transistor MN5.

In addition, the lines of the other word line clear signals wlc <1>, wlc <2>, and wlc <3> may also ground the potentials of all the sub-word lines corresponding to the above-described word line clear signals ( Of course, it is connected similarly to the line of wlc <0>).

Next, the operation of the row decoder of the hierarchical word line structure according to the embodiment of the present invention configured as described above will be described.

First, when decoding of the addresses (ai, aj, ak) is performed in the main row decoder 10, the main row decoder 10 outputs a high level signal, and the output signal outputs the inverter IV3. As the signal becomes a low level signal, the main word line MWL becomes a low level state.

Accordingly, the pull-up PMOS transistors MP3 ... in the plurality of sub-word drivers 16 to Kn hierarchically connected to the main word line MWL are turned on, and at this time, the respective pull-up PMOSs are turned on. Each sub-word line ((SWL1 <0> to SWLN <3>) is applied by a high level word line boosting signal px1 + <0> to pxN + <3> applied from the source of the type transistor MP3, ... ) Voltage becomes a high level state.

At the same time, the sub-word line clearing section 50 outputs word line clear signals wlc &lt; 0 &gt;, wlc &lt; 1 &gt;, wrc &lt; 2 &gt; and wlc &lt; 3 &gt; Since the sub-word line drivers 16 to Kn are controlled to maintain the high level potential, only the sub-word line of the selected address is activated.

That is, for example, when only a sub-word line of address 0 needs to be activated, the sub-word line clear unit 50 sets the line of the word line clear signal wlc &lt; The lines of the clear signals wlc &lt; 1 &gt;, wlc &lt; 2 &gt; and wlc &lt;

Accordingly, among the clear drive elements in each of the sub-word line drivers 16 to Kn, the clear connected to the sub-word lines SWL1 &lt; 0 &gt;, SWL2 &lt; 0 &gt;, SWL3 &lt; 0 &gt; Since only the driving elements MN5 ... are turned off and other clear driving elements are turned on, only the sub-word line at address 0 maintains the high level potential and the potential of the sub-word line at another address is ground level. Become

Of course, an operation similar to that described above is also performed when activating sub-word lines of other addresses.

According to the present invention as described above, since only a single main word line is used, the spacing of the main word lines is doubled compared to the conventional method of using a pair of main word lines, resulting in a bridge rate due to process problems. This significantly lowers not only the malfunction rate is significantly reduced, but also improves the operation at low power supply voltage, thereby increasing the yield.

In addition, this invention is not limited only to the above-mentioned embodiment, It can implement by modifying and modifying within the range which does not deviate from the summary of this invention.

Claims (15)

A decoding unit for selecting a predetermined word line in response to an input of a decoding address; A plurality of sub-word line drivers for bringing a plurality of sub-word lines connected to the output lines of the decoding unit in parallel to each other in a high voltage state according to the output signal and the word line boosting signal; And a sub-word line clearing unit controlling driving of a corresponding sub-word line driver to clear an unselected sub-word line among the plurality of sub-word lines. 2. The row decoder of claim 1, wherein a power supply voltage of the main row decoder is an internal power supply voltage that is made higher than an external power supply voltage. The row decoder of claim 1, wherein the output line of the decoding unit is a single main word line. 4. The row decoder of claim 3, wherein the main word lines are wired in a metal layer and pass over a cell array. 2. The apparatus of claim 1, wherein each of the sub-word line drivers is connected between an output line of the decoding unit and a corresponding sub-word line to invert an output signal of the decoding unit, and from the sub-word line clearing unit. A row decoder having a hierarchical word line structure, comprising: a clear driving element for leveling the potential of a sub-word line unselected by a signal of?; 6. The row decoder of claim 5, wherein the inverter device comprises a pull-up transistor and a pull-down transistor. 8. The row decoder of claim 6, wherein the row decoder is a PMOS transistor of the pull-up transistor. 8. The row decoder of claim 7, wherein the well of the PMOS transistor is connected to the internal power supply voltage. 8. The row decoder of claim 7, wherein the wells of the PMOS transistors are connected in source. 7. The row decoder of claim 6, wherein the pull-down transistor is an NMOS transistor. 7. The row decoder of claim 6, wherein the clear driving device is connected in parallel with the pull-down transistor. 7. The row decoder of claim 6, wherein the clear driving device comprises a MOS transistor. 13. The row decoder of claim 12, wherein the MOS transistor is an NMOS transistor. The row decoder of claim 13, wherein the threshold voltage of the NMOS transistor is 0.3V or less. The row decoder of claim 1, wherein the sub-word line clear unit is disposed outside a cell array.