KR19990005906A - Contact hole formation method of semiconductor device - Google Patents

Abstract

1. Technical field to which the invention described in the claims belongs

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming contact holes in semiconductor devices, and more particularly, to a method for forming self-aligned contact holes.

2. Technical problem that the invention tries to solve

In the self-aligned contact hole forming process, a large amount of polymer is used to control the etch selectivity, and it is also intended to solve the difficulty of controlling the etch prevention due to the excessive use of the polymer.

3. Summary of the solution of the invention

In the self-aligned contact hole forming process, an isotropic etching process having a high etching selectivity is performed.

4. Important uses of the invention

Semiconductor device manufacturing method

Description

Contact hole formation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact hole in a semiconductor device, and more particularly, to a method of forming a self-aligned contact hole.

In general, as the degree of integration of semiconductor devices increases, the minimum design limit of devices has drastically decreased. Therefore, the formation of fine patterns smaller than the limits of the exposure equipment has been required. However, in the case of the contact hole pattern, even if the fine contact hole of 0.1 μm or less is formed, a problem arises in that the contact resistance is increased because the contact area is too narrow in terms of the electrical characteristics of the device. Self-aligned contact hole forming technology has been proposed to solve the above problems. In particular, in the case of the nitride barrier self-aligned contact hole structure, self-alignment can be achieved with an increase in process steps compared to conventional contact forming techniques. However, the self-aligned contact hole forming technique uses a large amount of polymer (Polymer) in order to obtain a high selectivity for the nitride film, thereby causing a problem of controlling the etch stop due to the polymer at the same time.

Accordingly, the present invention provides a method for forming a contact hole in a semiconductor device, in which a small contact hole is formed to solve the above problem, and then an isotropic etching with a high selectivity to an oxide film formed on both sides of the contact hole is performed to increase the area of the contact hole. The purpose is to provide.

The present invention for achieving the above object is a step of forming a conductive layer pattern by sequentially forming a conductive layer and an insulating film on a semiconductor substrate, from the step of forming an insulating film spacer on the conductive layer pattern side, and Forming a hole in which a portion of the substrate is exposed through dry inclination etching after forming the interlayer insulating film from the step; and etching the interlayer insulating film in which the hole is formed by an isotropic etching process from the step by a predetermined depth to form a contact hole of a desired size Characterized in that it comprises a step of forming.

1A to 1D are cross-sectional views of a device for explaining a method for forming a contact hole in a semiconductor device according to the present invention.

2A to 2D are contact hole photographs of a semiconductor device according to the present invention.

Explanation of symbols for main parts of the drawings

1 semiconductor substrate 2 conductive layer

3: insulating film 4: insulating film spacer

5 interlayer insulating film 6 photosensitive film

7: first contact hole 8: second contact hole

Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.

1A to 1D are cross-sectional views of devices for explaining a method for forming contact holes in a semiconductor device according to the present invention.

FIG. 1A illustrates that the conductive layer 2 and the insulating layer 3 are sequentially formed on the semiconductor substrate 1, and then the insulating layer 3 and the conductive layer 2 are patterned to be spaced apart from each other, and then the patterned insulating layer 3 is formed. ) And the insulating film spacers 4 are formed on both sides of the conductive layer 2, and the insulating film 3 and the insulating film spacers 4 are formed of an undoped silicon oxide film.

1B is a cross-sectional view of the photoresist layer 6 patterned to form contact holes after the interlayer insulation layer 5 and the photoresist layer 6 are formed on the entire upper surface, and the interlayer insulation layer 5 is a doped silicon oxide layer. (Doped Silicon Oxide).

FIG. 1C is a cross-sectional view of a state in which the photosensitive film 6 is removed after the first contact hole 7 is formed to expose the semiconductor substrate 1 by an inclined etching process using the photosensitive film 6 as a mask. The process forms a gradient in which the ratio of the diameter of the upper part of the first contact hole 7 to the diameter of the lower part is 2: 1 or more by using the high density plasma method. In addition, a gas containing carbon and fluorine is used as a reaction gas in the gradient etching process. In addition, the dry etching of the high-density plasma method uses an ICP (Inductively Coupled Plasma) method, the reaction gas is injected at a mixed gas of C ₃ F ₈ and CO, but the mixing ratio of C ₃ F ₈ to CO is 1: 0.5 to 1: 1.5, and the mixed gas is injected in an amount of 30 to 150 SCCM. The high density plasma etching of the ICP method is performed at a temperature of 220 to 290 ° C., the ICP high frequency power is applied at 1600 to 2800 watts, and the bias high frequency power is applied at 600 to 1800 watts.

FIG. 1D is a cross-sectional view of a second contact hole 8 having a desired size by performing an isotropic etching process having a high etching selectivity with respect to the insulating film 3 and the insulating film spacer 4. Silver is carried out by a wet etching method using phosphoric acid and SC-1 as an etchant, wherein the temperature of the two etchant is from room temperature to 200 ℃. In particular, when wet etching using SC-1 as an etchant using a mixed solution of NH ₄ OH, fruit water and pure water, the mixing ratio of the fruit water to NH ₄ OH is 1: 1 to 1:10, the SC-1 etchant The amount of pure water to the total amount of is adjusted to 40 to 90% to adjust the etching selectivity of the insulating film 3 and the insulating film spacer 4 to a desired predetermined value.

In addition, during the isotropic etching process, the temperature of the wafer is adjusted to a temperature range of room temperature to 500 ° C. to adjust the etching selectivity for the insulating film 3 and the insulating film spacer 4 to a desired predetermined value. In addition, the isotropic etching process may be performed using any one of a plasma chamber of a microwave down stream method, an ICP method, an ECR method, a TCP method, and a HELICON method.

2A to 2D are contact hole photographs of a semiconductor device according to the present invention.

2A and 2B are electron micrographs of the above-described process step of FIG. 1C.

2C to 2D are electron micrographs of the above-described process step of FIG. 1D.

As described above, the self-aligned etching process according to the present invention can form contact holes of a desired size more efficiently and easily in the conventional self-aligned etching process.

Claims (10)

Forming a conductive layer pattern by sequentially forming a conductive layer and an insulating film on the semiconductor substrate, forming an insulating film spacer on the side of the conductive layer pattern from the step, and forming an interlayer insulating film from the step, followed by dry tilting Forming a hole through which the part of the substrate is exposed through etching, and forming a contact hole having a desired size by etching a predetermined depth from the interlayer insulating layer where the hole is formed by an isotropic etching process. A method for forming a contact hole in a semiconductor device. The method of claim 1, wherein the insulating film and the insulating film spacer are formed of an undoped silicon oxide film. The method of claim 1, wherein the interlayer insulating film is formed of a doped silicon oxide film. The method of claim 1, wherein the dry gradient etching process uses an etching gas containing carbon and fluorine gas. The method of claim 1, wherein the dry gradient etching process uses a high density plasma etching method. The method of claim 1, wherein the isotropic etching process is performed by a wet etching method using either phosphoric acid solution or SC-1 as an etchant. 7. The method of claim 6, wherein the phosphoric acid content is 30 to 99% during wet etching using the phosphoric acid solution as an etchant. The method of claim 6, wherein the wet solution using a mixed solution of NH ₄ OH, fruit water and pure water in the wet etching using the SC-1, the mixing ratio of the fruit water to the NH ₄ OH is 1: 1 to 1:10, The amount of pure water relative to the total amount of the SC-1 etchant is 40 to 90%. 7. The method of claim 6, wherein the temperature of the etchant is from room temperature to 200 ℃. The method of claim 1, wherein the wafer has a temperature of about 500 ° C. in the isotropic etching process.