KR19990004396A - Test pattern of semiconductor device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

It relates to a test pattern of a semiconductor device.

2. The technical problem to be solved by the invention

Test patterns that can simultaneously check for misalignment and design rules that can occur during the transistor formation process in all semiconductor devices that use transistors, such as FLASH EEPROM There is no difficulty in rapid defect analysis.

3. Summary of Solution to Invention

Forming a test pattern with four symmetrical transistors in the scribe line of the wafer to simultaneously monitor the misalignment and design rules of the semiconductor device unit cell.

4. Important uses of the invention

Test pattern formation process of a semiconductor device.

Description

Test pattern of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to test patterns of semiconductor devices, and in particular to simultaneously monitoring misalignment and design rules that may occur in the transistor formation process of all semiconductor devices using transistors. It is about test patterns that can be done.

Generally, a semiconductor device analyzes and repairs defects by using an electrical signal of a transistor.In case of an abnormality in a transistor, there is no test pattern that simultaneously inspects misalignment and design rules in terms of process-related aspects, so that a problem of rapid failure analysis and repair occurs. There is difficulty in failure analysis.

Accordingly, an object of the present invention is to form a test pattern for simultaneously inspecting misalignment and design rules of transistors at a wafer level, and to monitor early to detect defective devices quickly, and to facilitate defect analysis when a repair problem occurs.

The test pattern of the semiconductor device according to the present invention for achieving the above object, to form a plurality of unit patterns consisting of four transistors crosswise around the drain region on the empty space of the wafer, The size is configured differently.

1 is a test pattern layout diagram of a semiconductor device according to the present invention;

FIG. 2 is a cross-sectional view of a test pattern of the semiconductor device taken along the line AA of FIG. 1. FIG.

Explanation of symbols for the main parts of the drawings

10 silicon substrate 11 drain

12: source 13: gate

14: first polysilicon layer 15: second polysilicon layer

16: third polysilicon layer

The present invention will be described in detail with reference to the accompanying drawings.

1 is a test pattern layout diagram of a semiconductor device according to the present invention.

Test patterns having the configuration as shown in FIG. 1 are formed in a scribe line of the wafer at the wafer level. The layout of FIG. 1 is a unit pattern, in which two identical transistors T _X1 and T _X2 are formed in the X-axis direction, and two identical transistors T _Y1 and T _{Y2 in the} Y-axis direction. To form four transistors in a cross shape. Therefore, misalignment and design rules can be monitored simultaneously. That is, when a voltage is applied between the source 12 and drain 11 of the same two transistors (T _X1, T _X2) of the X-axis direction measurement of the current (current), the two transistors (T _X1, T _X2) The current should be the same, but in case of failure due to misalignment in the manufacturing process, the current values of T _X1 and T _X2 will be measured differently. Two transistors T _Y1 and T _{Y2 in the} Y-axis direction can also be inspected for misalignment in the manufacturing process in the same manner.

In addition, the above-mentioned unit pattern is formed in the vacant space of the wafer, and the size of the transistors T _X1 , T _X2 , T _Y1 , and T _Y2 is different for each unit pattern, so that the transistor size has good transistor characteristics Can be found. Therefore, unit patterns constituting the cross-shaped transistors T _X1 , T _X2 , T _Y1 , and T _Y2 are formed around the drain 11, and each unit pattern in which the size of the transistor is changed in an empty position of the wafer is formed. By arranging, it is possible to simultaneously monitor the misalignment and design rules in the manufacturing process as described above.

FIG. 2 is a cross-sectional view of a test pattern of the semiconductor device taken along the line AA of FIG. 1.

In particular, the cross-sectional view shown in FIG. 2 shows an example of a transistor used in an actual FLASH EEPROM device. That is, by implanting ions on the silicon substrate 10 to form the source 12 region and the drain region 11 of the LDD structure, the first polysilicon layer 14, the second polysilicon layer 15 and the first 3 illustrates a test pattern including transistors that sequentially deposit the polysilicon layer 16 to form a split gate.

The present invention is applicable to all integrated circuits forming the transistor.

As described above, according to the present invention, unlike a conventional method of repairing a fuse by removing a fuse in the semiconductor device manufacturing process, a method of repairing by comparing the current of a transistor is repaired. Simultaneous inspection allows quick failure analysis.

Claims (1)

A test pattern of a semiconductor device, characterized in that a plurality of unit patterns are formed on the empty space of a wafer with four transistors in a cross shape around the drain region, and the transistors are configured in different sizes.