KR19990001235U - TFT liquid crystal display element - Google Patents

Abstract

The present invention relates to a TFT liquid crystal display device and a TFT liquid crystal display device driving method in which a level shift voltage that varies depending on a signal delay of a gate line (12) is reduced when a selection period is changed to a non-selection period. The TFT liquid crystal display device of the related art has a structure of the TFT 10 and the storage capacitance 20 for each pixel and can not compensate for the difference in the drop voltage different between the pixels due to the signal delay of the gate line so that a screen flicker occurs The picture quality has dropped. In the present invention, the storage capacitance of a pixel remote from the gate pad 21 is made smaller than the storage capacitance of a pixel near the gate pad 21, or the parasitic capacitance between the gate source of the pixel remote from the gate pad 21 C _GS is larger than a pixel near the gate pad 21 to compensate for the level shift voltage due to the signal delay of the gate line 12. [ Also, the voltage applied to the pixel in the same group is made different according to the position away from the gate pad, and the residual DC applied to the pixel is minimized to improve the image quality. The effect of the present invention is well demonstrated in a medium to large-sized TFT liquid crystal display device having a screen larger than 13 ''.

Description

TFT liquid crystal display element

1 is a sectional view of a TFT liquid crystal display element;

Sectional view of the second-degree TFT

Third, the equivalent circuit of the pixel of the TFT liquid crystal display element

Process diagram of the TFT substrate of the fourth degree

5 is a plan view of the electrode pad of the TFT liquid crystal cell

6 shows a driving waveform of the TFT liquid crystal display element

The signal delay of the gate line according to the position of the seventh degree pixel

8 shows a level shift voltage measurement of the TFT liquid crystal display element.

The electro-optic transmission curve of the TFT liquid crystal display element according to the position of the ninth-degree pixel

The electro-optical transmission curve of the TFT liquid crystal display element according to the signal delay of the gate line when a positive DC voltage of 10 degrees was applied

The electro-optical transmission curve of the TFT liquid crystal display element according to the signal delay of the gate line when the negative DC voltage was applied to the eleventh stage

12 is a plan view of the electrode of the storage capacitance of the TFT liquid crystal display element of the present invention

13 is a plan view of the TFT electrode of the TFT liquid crystal display element of the present invention

Structure of the 14th Backlight

15th plan view of scatter plate

Description of the Related Art [0002]

1: Polarizing plate 2: Scattering plate

3: lower glass substrate 4: upper glass substrate

5: liquid crystal 6: common electrode

7: pixel electrode 10: TFT

11: gate electrode 12: gate line

13: source electrode 14: drain electrode

15: Common electrode of storage capacitance 16: Amorphous silicon film

17: n ⁺ film 18, 18 ': gate insulating film

19: etching stop film 20: storage capacitance

21: gate line pad 22: signal line pad

30: Fluorescent light 31: Climbing desert

32: scattering plate 33: reflector

34: Waveguide 35: Side reflection film

36: diffusion plate 37: scattering film

38: scattering substrate

The present invention relates to a method of driving a TFT liquid crystal display element and a TFT liquid crystal display element in which a difference in level shift voltage caused by a degree of signal delay of a gate line (12) is reduced when a selection period is changed to a non- .

1 is a sectional view of a TFT liquid crystal display element. The gate electrode 11 of the TFT in each pixel is connected to the gate line 12 and the source electrode 13 to the signal line and the drain electrode 14 to the pixel electrode 7. There is a liquid crystal layer between the common electrode 6 and the pixel electrode. 2 is a cross-sectional view of the TFT pixel of the glass substrate 3 below. FIG. 4 is a process drawing of an ES (Etch Stopper) type TFT. The process sequence for fabricating the TFT is as follows.

(1): On the glass substrate 3, the gate wirings 11 and 12 and the common electrode 15 having the maintaining electric capacity are made of a metal having a low resistivity such as MoW and Al.

(2): a gate insulating film (SiO _x , SiN _x ) 18, 18 ', an amorphous silicon film 16 and an etch stop film 19 are coated.

(3): Etch the etching stop film.

(4): The n ⁺ film 17 is coated.

(5): The n ⁺ film 17, the amorphous silicon film 16, and the gate insulating film 18 'are etched.

(6): A pixel electrode is formed.

(7): A source electrode 13 and a drain electrode 14 are formed of a metal such as Mo / Al / Mo. N ⁺ etching is performed in the process of etching the source electrode and the drain electrode. After this process, a passivation layer such as SiO _x or SiN _x is formed.

FIG. 6 is an example of driving waveforms of the column inversion driving method. During the selection period, a voltage higher than the signal line is applied to the gate electrode connected to the gate line, and the resistance of the channel (n-channel) between the drain electrode and the source electrode is reduced, so that a voltage caught by the signal line is caught by the pixel electrode. During the non-selection period, a voltage lower than the signal line is applied to the gate electrode connected to the gate line, and the drain electrode and the source electrode are electrically disconnected, so that the voltage across the liquid crystal layer is maintained during the selection period. Voltage is applied to the liquid crystal layer of each pixel through a signal line while sequentially scanning the gate line. When the root mean square (rms) voltage applied to the liquid crystal layer between the pixel electrode and the common electrode is adjusted, linearly polarized light passing through the polarizer 1 passes through the liquid crystal layer 5 and changes its polarization state. Is selectively transmitted to display information as the brightness of the pixel. The polarity of the voltage applied to the liquid crystal layer is changed every frame to prevent the electrochemical reaction of the liquid crystal molecules by adjusting the waveform of the voltage applied to the signal line and the common electrode. The storage capacitance C _s is made in parallel with the capacitance C _{LC of the} liquid crystal so that the voltage across the liquid crystal during the non-selection period is well maintained during the non-selection period. The TFT liquid crystal display device can be divided into a common method and a previous gate according to the method of making the storage capacitor 20. In the front-end gate method, the capacitance formed by the gate insulating films 18 and 18 'between the pixel electrode and the gate line at the previous stage is used as the storage capacitance. In the common method, a common electrode having a different storage capacity is formed between the pixel electrodes The electric capacity formed by the gate insulating films 18 and 18 'between the electrodes and the pixel electrodes is written as a conservative electric capacity.

Since each pixel of the TFT liquid crystal display element is independently driven, if an equivalent circuit is drawn for one pixel, it is the same as the third aspect. 3 (A) and 3 (B) are equivalent circuits of unit pixels in the selection period and the non-selection period, respectively. Since the resistance R _ON of the channel between the source electrode and the drain electrode of the TFT is small during the selection period, the influence of the parasitic capacitance between the electrodes of the TFT can be neglected, so that the equivalent circuit of the pixel of the TFT liquid crystal display element is a typical RC circuit to be. During the selection period, the time constant of the RC circuit must be much shorter than the selection period (T _S ) in order for the capacitance of the pixel (C _LC + C _S ) to fully take up the voltage of the signal line.

R _ON (C _LC + C _S ) T _S (1)

In the non-selection period, the resistance between the source electrode and the drain electrode of the TFT is very large, so that the parasitic capacitance between the electrodes of the TFT can not be ignored. The voltage change of the scanning line and the signal line affects the pixel voltage through the parasitic capacitance between the electrodes of the TFT. In order for the voltage applied to the pixel to be maintained during the non-selection period during the selection period, the time constant of the circuit formed by the signal line and the pixel electrode in the non-selection period must be much larger than the period (T _F ) of one frame.

R _OFF (C _LC + C _S ) T _F (2)

The parasitic capacitance of the portion where the electrodes of the TFT 10 overlap each other causes signal distortion and signal delay. The parasitic capacitance between the gate electrode and the source electrode is represented by C _GS , the parasitic capacitance between the gate electrode and the drain electrode is represented by C _GD , and the parasitic capacitance between the source electrode and the drain electrode is represented by C _SD . The voltage change when the gate line is switched from the selection period to the non-selection period makes the voltage across the liquid crystal layer different through the parasitic capacitance C _GD between the TFT gate and the drain. When the voltage change of the gate line is? V _g , the voltage change? V of the liquid crystal layer in the equivalent circuit of (B) of FIG. 3 is obtained as follows.

(3)

Since the pixel voltage is lowered regardless of the polarity of the voltage applied to the pixel, the DC voltage is applied to the liquid crystal layer if it is not compensated. If ΔV is large, it causes a flicker of the screen, and a residual image may be generated due to the DC voltage received by the liquid crystal layer, thereby deteriorating the image quality. Driving methods have been proposed to control the voltage polarity of the signal line so that the signal distortion often occurs more than 60 Hz in order to prevent the image quality from deteriorating due to the signal distortion. A column inversion driving method in which the polarity is reversed for each liquid crystal layer of the pixels of the adjacent gate lines and a column inversion driving method in which the polarity of the liquid crystal layer of the adjacent signal lines is reversed, This is a dot inversion driving method. ΔV varies depending on the voltage applied to the pixel. The maximum difference ΔV is a very important parameter for designing the TFT substrate, and is about 0.3 to 0.5 V at present. (4), C _LC (MAX) and C _LC (MIN) are the electric capacitance of the liquid crystal layer when the largest voltage and the smallest voltage are applied to the liquid crystal layer.

(4)

However, even when the same voltage is applied due to the signal delay of the gate line, ΔV differs for each pixel. 5 shows a pad of an electrode of the TFT liquid crystal cell. A gate driving IC is attached to the gate pad 21, and a source driving IC is attached to the signal line pad 22 to drive the TFT. Since the gate line forms an electric capacitance with the surrounding signal line and the pixel electrode and with the common electrode, if the pulse pad is applied to the gate pad at the top of FIG. 7, the waveform of the gate line at the portion A, which is relatively close to the gate pad, The signal delay occurs, and the waveform of the gate line at the portion C far from the gate pad is delayed much. The gate pads A, B, and C in FIG. 7 are the voltage waveforms of the gate lines in the gate pad, A, B, and C regions in FIG. 5, respectively. FIG. 9 is an electro-optic transmission curve of pixels in A, B, and C in FIG. 5 when the common electrode is grounded, the AC square wave is applied to the signal line, and the gate line is sequentially driven without correcting the falling voltage. It can be seen that the electro-optic transmission curve is different due to the signal delay. As shown in FIGS. 10 and 11, the electrooptical transmission curves are plotted while applying a DC voltage to the signal line as shown in FIG. FIG. 10 is an electro-optical transmission curve when a voltage applied to a signal line is a positive voltage with respect to a voltage applied to the common electrode, and FIG. 11 is a graph showing the relationship between a voltage applied to the signal line and a voltage Lt; / RTI > transmission curve. In FIG. 10 and FIG. 11, the curve D is an electro-optical transmission curve in the case where there is no drop voltage? V when a DC voltage is applied to the gate line. The difference in voltage between the curve D and the other curve at the same transmittance represents the drop voltage? V. The voltage change? V _g of the gate line is the same with the signal delay as the distance from the gate pad increases. However, since the rate of voltage change per unit time is low, the electrons in the channel escape to the signal line when the gate line is unselected.

However, in the conventional TFT liquid crystal display device, the structure of the pixel is the same in all the screens, and the difference in the drop voltage different from pixel to pixel due to the signal delay of the gate line can not be compensated and residual DC is applied to the liquid crystal layer, ) Or an afterimage, resulting in poor image quality.

In the present invention, the storage capacitance 20 of the pixel remote from the gate pad 21 is made smaller than the storage capacitance of the pixel nearest the gate pad 21, or between the gate source of the pixel remote from the gate pad 21 The parasitic capacitance C _GS is made larger than the pixel near the gate pad 21 to compensate for the level shift voltage due to the signal delay of the gate line 12. [

12 shows the structure of the electrode of the storage capacitor 20 of the TFT liquid crystal display element of the present invention. A, B, and C are the electrodes of the storage capacitors at A, B, and C indicating the pixel position in the fifth view. The storage capacitance of the pixel A closer to the gate pad 21 is increased and the storage capacitance of the pixel C far from the gate pad is decreased. When the drop voltage ΔV is obtained from equation (3), the pixel far from the gate pad has a small storage voltage, so that the drop voltage is large. However, the drop voltage caused by the signal delay of the gate line is small have. In addition, since the pixel near the gate pad has a large storage capacitance, the voltage drop in Equation (3) is small, but the voltage drop caused by the signal delay is large because the signal delay of the gate line is small. Therefore, if the pattern of the common electrode of the storage capacitance is made as in the twelfth aspect, the drop voltage can be made constant irrespective of the position of the pixel, so that the image quality can be improved. In the case where the storage capacitance is a front-end gate, the shape of the gate line may be made uniform as the common electrode of the storage capacitance of FIG. 13 by making the width smaller as the distance from the gate pad is made, .

FIG. 13 is a plan view of a TFT electrode which does not change the storage capacitance but instead compensates the signal delay of the gate line by adjusting the parasitic capacitance of the TFT. (3), the pixel C far from the gate pad has a large parasitic capacitance (C _GD ), so that the falling voltage is large but the falling voltage generated by the signal delay of the gate line is far from the gate pad They are small and can compensate for each other. Since the parasitic capacitance (C _GD ) of the pixel near the gate pad is small, the falling voltage of the equation (3) is small. However, since the signal delay of the gate line is small, the falling voltage caused by the signal delay is large and compensation is made. Accordingly, as shown in FIG. 13, since the falling voltage can be made constant irrespective of the position of the pixel, the image quality can be improved. 13A shows the parasitic capacitance C _GD for adjusting the width of the channel, and FIG. 13B shows the parasitic capacitance C _GD by adjusting the overlapping portion between the gate electrode and the drain electrode.

If the voltage of the signal line corresponding to the in-phase group can be different, a voltage compensated for the drop voltage caused by the signal delay of the gate line can be applied to drive without residual DC. For example, a tenth to help each voltage to be the transmittance in claim 11 correspond to the _{20% V A (+),} V B (+), V C (+) and _{V A (-), V B} (-), If V _C (-), the voltage applied to the pixel is given to the pixel position differently from A, B, and C, so that the voltage compensated for the drop voltage caused by the signal delay of the gate line is applied.

In the case of compensating the drop voltage due to the signal delay of the gate line by adjusting the magnitude of the storage capacitance, if the aperture ratio varies depending on the position and the brightness and the change of the screen are large, the transmittance of the backlight is adjusted according to the position, . In the backlight for a liquid crystal display device, a climbing desiccant 31 of a fluorescent lamp surrounds the fluorescent lamp 30 and is attached to the optical waveguide 34 as shown in FIG. A scattering plate 32 and a reflection plate 33 are attached to the bottom of the optical waveguide 34 and a diffusion plate 36 is attached to the top and a side reflection film 35 is attached to the corner. Like the translucent plastic resin, the diffusion plate 36 diffuses light in various directions to even out light entering the liquid crystal display element. The material of the optical waveguide is mainly acrylic resin and is guided by utilizing the total reflection property of light. The 15 degrees in plan view of the diffuser, to spread the light to print the scattering film 37 is a large refractive index such as Al ₂ O ₃ and Ti ₂ O ₃ in the dispersion board 38 in various directions. By adjusting the printing area of the scattering film per unit area, the brightness of the light passing through the liquid crystal display element can be controlled. The portion of the pixel having a small aperture ratio can have a larger area ratio of the scattering film per unit area, so that much light can be emitted ahead of other portions.

It is possible to compensate for the level shift voltage due to the signal delay of the gate line 12 according to the present invention to reduce the screen flicker and the residual image due to the residual DC. The present invention is suitable for a TFT liquid crystal display device used for a monitor, because the effect is remarkably exhibited in a middle- or large-sized TFT liquid crystal display device having a screen larger than 13 ".

Claims (5)

In a TFT liquid crystal display element in which a TFT is placed between a signal line and a pixel electrode 7 to apply a voltage to the liquid crystal layer 5, in the case where the storage capacitance 20 of a pixel in a region where the signal delay of the gate line is long, The difference in the level shift voltage of the same group due to the signal delay of the gate line 12 is reduced because the delay is smaller than the storage capacitance of the pixel in the short region. The TFT liquid crystal display of claim 1, wherein a size of the storage capacitor is adjusted by adjusting a pattern of the common electrode (15) of the storage capacitor. The TFT liquid crystal display of claim 1, wherein a gate electrode pattern is adjusted to adjust a magnitude of a storage capacitance. A parasitic capacitance C between a gate electrode 11 and a drain electrode 14 of a pixel in a region where a signal delay of a gate line is long, _{GD is set} to be larger than parasitic capacitance C _GD between the gate electrode and the drain electrode of the pixel in the region where the signal delay is short and the difference in the drop voltage of the same gradation due to the signal delay of the gate line is reduced. A TFT liquid crystal display element which applies a voltage between a signal line and a pixel electrode to apply a voltage to a liquid crystal layer by applying a TFT between the signal line and the pixel electrode is different from that of the TFT liquid crystal display element in which the voltage of the signal line of the same group is different, Way