KR19980082737A - Smitt trigger circuit with static protection - Google Patents

Abstract

The present invention includes an input circuit portion, a switching circuit portion, an output circuit portion. A power supply voltage or a ground voltage is applied to a transistor of a switching circuit portion having a smaller transistor size compared to an input circuit portion and an output circuit portion through an inverter.

Description

Smitt trigger circuit with static protection

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a meter trigger circuit, and more particularly, to a mit trigger circuit having an electrostatic protection function.

As semiconductor integrated circuits have been miniaturized by the development of process technology, the problem of damage to devices due to static electricity is becoming important.

In general, the smit trigger circuit implemented as a CMOS circuit on a semiconductor chip is composed of an input circuit section, a switching circuit section, and an output circuit section. And there is a risk of first damage by the static electricity flowing through the ground terminal.

Accordingly, an object of the present invention is to provide a mit trigger circuit having an electrostatic protection function.

In order to achieve the above object, the meter trigger circuit of the present invention includes a first transistor having a first size having a current path connected between a power supply terminal and a first node, a gate connected to an input terminal, and the first node and the first node. A current path is connected between the two nodes, a gate is connected to the input terminal, and a second transistor having the first size, a current path is connected between the second node and the third node, and a gate is connected to the input terminal. And a third transistor having the first size, and a fourth transistor having a first path connected to a current path between the third node and a ground terminal and having a gate connected to the input terminal. Further, in the present invention, a current transistor is connected between the first node and the fourth node, a gate is connected to the second node, and a fifth transistor having a second size, and is connected between the power terminal and the fourth node. A first inverter configured to supply a ground potential to the fourth node, a sixth transistor having a current path connected between the third node and a fifth node, a gate connected to the second node, and having the second size; And a second inverter connected between the ground terminal and the fifth node to supply a power potential to the fifth node. In the present invention, a current path is connected between the power supply terminal and the output terminal, a gate is connected to the second node, and a seventh transistor having a third size, and a current path is connected between the output terminal and the ground terminal. And an eighth transistor having a gate connected to the second node and having the third size.

1 is a view showing a configuration of a mit trigger circuit having a static electricity protection function according to the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 shows a configuration of a Schmitt trigger circuit having an electrostatic protection function according to the present invention. In FIG. 1, the circuit includes an input circuit unit 20 that generates an input signal A applied to the input terminal 10 as an inverted signal B having a predetermined slope in response to a switching signal, and the inverted signal B. In response, the switching circuit section 30 provides a switching signal to the input circuit section, and an output circuit section 40 which inverts an inverted signal and outputs the output signal to the output terminal 50.

The input circuit unit 20 includes a first transistor MP1 having a medium size, a current path connected between the power supply terminal 60 and the first node N1, a gate connected to the input terminal 10, and the first node. A second transistor MP2 having a medium size, a current path connected between N1 and a second node N2, and a gate connected to the input terminal 10, the second node N2, and a third node. A current path is connected between N3, a gate is connected to the input terminal 10, and a current path is formed between the third transistor MN1 having an intermediate size, the third node N3, and the ground terminal 70. A fourth transistor MN2 having a medium size and a gate connected to the input terminal 10 is connected.

The switching circuit unit 30 includes a fifth transistor MP3 having a smallest size and having a current path connected between the first node N1 and a fourth node N4 and a gate connected to the second node N2. ), A first inverter INV1 and a third node N3 connected between the power supply terminal 60 and the fourth node N4 to supply a ground potential VSSP to the fourth node N4. A sixth transistor MN3 having the smallest size, a ground terminal 70, and the fifth node (5) having a smallest size and a current path connected between the second node N5 and a gate connected to the second node N2. It is composed of a second inverter (INV2) connected between the N5) for supplying a power potential (VDDP) to the fifth node (N5).

The output circuit unit 40 includes a seventh transistor MP4 having a largest size and a current path connected between the power supply terminal 60 and the output terminal 50 and a gate connected to the second node N2. A current path is connected between the output terminal 50 and the ground terminal 70, and a gate is connected to the second node N2, and the eighth transistor MN4 has the largest size.

The operation of the present invention configured as described above is as follows.

When a pulsed positive or negative high voltage is applied to the power supply terminal 60 or the ground terminal 70, the transistors are relatively larger than the transistors of the input circuit section 20 or the output circuit section 40 having a relatively large transistor size. When a power supply terminal or a ground terminal is directly connected to the transistors of the switching circuit unit 30 having a small size, an impact is applied to the device, which may damage the device.

However, in the present invention, by supplying the power supply voltage or ground voltage through the inverter, when a high voltage caused by static electricity is applied to the ground terminal or the power supply terminal through the inverter to protect the transistors of the switching circuit unit from the electrical shock caused by static electricity You can do it.

Therefore, in the present invention, as described above, the transistor can be protected by absorbing or bypassing an electric shock caused by static electricity applied to a circuit portion having a relatively small size of the transistor by the inverter, so that a circuit resistant to static electricity can be implemented. It is possible to improve the reliability.

Claims (4)

A first transistor having a first size and a current path connected between the power supply terminal and the first node and a gate connected to the input terminal; A second transistor having a first size and a current path connected between the first node and a second node and having a gate connected to the input terminal; A third transistor having a first size and a current path connected between the second node and a third node and having a gate connected to the input terminal; A fourth transistor having a first size and a current path connected between the third node and a ground terminal and having a gate connected to the input terminal; A fifth transistor having a second size and a current path connected between the first node and a fourth node, a gate connected to the second node; A first inverter connected between the power supply terminal and the fourth node to supply a ground potential to the fourth node; A sixth transistor having a second size and a current path connected between the third node and a fifth node and a gate connected to the second node; A second inverter connected between the ground terminal and the fifth node to supply a power potential to the fifth node; A seventh transistor having a third size having a current path connected between the power supply terminal and an output terminal and a gate connected to the second node; And And an eighth transistor having a third size and a current path connected between the output terminal and the ground terminal, and a gate connected to the second node. 2. The Schmitt trigger circuit of claim 1 wherein the second size is smaller than the first and third sizes. 2. The Schmitt trigger circuit of claim 1 wherein the first, second, fifth, and seventh transistors are PMOS transistors. 2. The Schmitt trigger circuit of claim 1 wherein the third, fourth, sixth, and eighth transistors are NMOS transistors.