KR19980082684A - Fast switching circuit using differential split level inverter - Google Patents

Abstract

The present invention provides a display device comprising: first reference voltage generating means for outputting a predetermined voltage between a supply voltage and a ground voltage level according to an input signal; Second reference voltage generating means having the same configuration as the first reference voltage generating means and outputting a predetermined voltage between a supply voltage and a ground voltage according to an inverted signal of the input signal; And a differential split level inverter for outputting a positive output and a negative output of the input signal according to each output of the first reference voltage generating means and the second reference voltage generating means, wherein the first and second reference voltages are generated. Means for limiting the swing width of the input signal so that the differential split level inverter has a fast switching time.

Description

Fast switching circuit using differential split level inverter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed switching circuit of a semiconductor device, and more particularly, to high speed switching using a differential split level inverter that limits the swing width of an input stage to improve switching speed. It is about a circuit.

As is well known, the conventional switching circuit uses a circuit which passes through several stages of CMOS inverters, so that an input signal is output as a positive output signal and a negative output signal. Here, in the CMOS inverter, one side of the PMOS transistor is connected to the power supply voltage Vdd, the gate side is connected to the input side together with the gate of the NMOS transistor, and the other side is connected to one side of the NMOS transistor. It is a conventional inverter circuit connected to the output side and the other side of the NMOS transistor is connected to the ground (GND). The PMOS transistor pulls up the output voltage level, and the NMOS transistor pulls down the output voltage level.

1 is a typical CMOS inverter switching circuit diagram. Referring to the drawings, the conventional CMOS inverter switching circuit is composed of a chain of CMOS inverters (111, 112, 113, 126, 127), the input of the input node 11 has an odd number of (three) inverters (111, 112, 113) The sub output is outputted to the output node 14b through the output terminal, and the positive output is outputted to the output node 14 through the even number of inverters 126 and 127.

At this time, when a signal is inputted to the input node 11 so that the output node 14b and the output node 14 each switch to drive the circuit of the next stage, the output signal delay of the inverters 113 and 127 connected to the respective output terminals is general. It depends on the delay time of CMOS inverter. Therefore, a switching circuit composed of a chain of CMOS inverters has a disadvantage in that the delay time of the circuit increases as the inverter is added.

An object of the present invention is to provide a high speed switching circuit using a differential split level inverter that limits the swing width of an input stage to improve switching speed.

1 is a conventional CMOS inverter switching circuit diagram,

2 is a high speed switching circuit diagram using a differential split level inverter according to an embodiment of the present invention;

3A to 3D are timing diagrams showing simulation results of FIGS. 1 and 3;

* Explanation of symbols for the main parts of the drawings

223, 225, 233, 235, 246, 248: NMOS transistors

247 and 249: PMOS transistors

220, 230: first and second reference voltage generator

240: differential split level inverter

The present invention for achieving the above object, the first reference voltage generating means for outputting a predetermined voltage between the supply voltage and the ground voltage level in accordance with the input signal; Second reference voltage generating means having the same configuration as the first reference voltage generating means and outputting a predetermined voltage between a supply voltage and a ground voltage according to an inverted signal of the input signal; And a differential split level inverter for outputting a positive output and a negative output of the input signal according to each output of the first reference voltage generating means and the second reference voltage generating means, wherein the first and second reference voltages are generated. Means for limiting the swing width of the input signal so that the differential split level inverter has a fast switching time.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

2 is a high speed switching circuit diagram using a differential split level inverter according to an embodiment of the present invention. Referring to the drawings, the high-speed switching circuit according to an embodiment of the present invention, the first reference voltage generator for outputting a predetermined voltage between the supply voltage (Vdd) and the ground voltage according to the input signal input from the input node 21 230 and a second configuration having the same configuration as that of the first reference voltage generator 230, and outputting a predetermined voltage between the supply voltage and the ground voltage according to the inverted signal of the input signal by the inverter 211. A reference voltage generator 220 and a differential split level inverter 240 for outputting a positive output and a negative output of the input signal according to each output of the first reference voltage generator and the second reference voltage generator; do.

In detail, the first and second reference voltage generators 220 and 230 may be diode-connected with the PMOS transistors 222 and 232 to which an input signal is applied to the gate, and the source and gate are connected to each other. NMOS transistors 224 and 234 and NMOS transistors connected to an output terminal (node 23 and node 23b) through NMOS transistors 223 and 233 and to which the output terminal (node 23 and node 23b) is applied as a gate. Connected to ground power supply terminal GND through NMOS transistors 225 and 235 diode-connected in parallel with 224 and 234, and supply voltage / 2 to an output terminal (node 23, node 23b) according to the level of the input signal. Or selectively outputs any one of a predetermined voltage between the supply voltage / 2 and the ground voltage. The differential split level inverter 240 is connected between the output terminal (node 23b) and the final negative output terminal (node 24b) of the first reference voltage generator 220, and supplies the supply voltage / 2 + Vth (gate) from the outside to the gate. It is connected between the NMOS transistor 248 to which the third reference voltage, which is the threshold voltage value), and the output terminal (node 23) and the constant output terminal (node 24) of the second reference voltage generator 230 are connected. The NMOS transistor 246 receives the third reference voltage, the PMOS transistor 246 connected between the constant output terminal (node 24) and the supply power supply terminal and receives the output of the first reference voltage generator 230 as a gate. 247 and a PMOS transistor 24b connected between the sub-output terminal (node 24b) and the supply power supply terminal and receiving the output of the second reference voltage generator 220 as a gate.

It looks at the operation of the present invention having the configuration as described above.

If input node 21 is high, node 22b is low. If the node 22b signal is low, the NMOS transistor 224 is turned off, the PMOS transistor 222 is turned on, and the node 27 is higher than the threshold voltage of the NMOS transistor 223. Therefore, the NMOS transistor 223 is also turned on.

At this time, since the voltage applied to the node 23 passes through the PMOS transistor 222 and the NMOS transistor 223 from the power supply voltage, it has a value obtained by subtracting the threshold voltage of the NMOS transistor 223 from the power supply voltage level, but of the NMOS transistor 225. Since the gate and the drain are connected to the node 23, the NMOS transistor 225 is also turned on so that the value of the node 23 has an intermediate value between the power supply voltage and the ground.

Similarly, since the input node 21 is high, the PMOS transistor 232 and the NMOS transistor 233 are turned off. The NMOS transistor 234 connected to the ground is turned on so that the node 23b has a low value, but since the node 23 has a half value of the supply voltage, the NMOS transistor 234 is connected to the PMOS transistor 249 and the NMOS transistor 248 at the supply voltage. Node 23b has a value slightly larger than the ground value due to the leakage current of the path.

If the voltage level of the reference voltage is equal to the sum of the power supply voltage and the threshold voltage (Vtn) of the NMOS transistor, the NMOS transistor 246 and the NMOS transistor 248 are applied with a voltage higher than the threshold voltage to the gate. It is always turned on.

In the figure, when the input node 21 signal is low, the opposite case to that of the high case follows. As such, the swing widths of nodes 23 and 23b are limited to values between about 0.5V higher than ground and about half the supply voltage.

When the input node 21 signal is switched, switching by the limited swing width of node 23 and node 23b is applied as input to differential split-level inverter 240. At this time, the switching speed is faster than when the full swing of the CMOS inverter (Fig. 1) is received as an input.

The PMOS transistors 222 and NMOS transistors 223, 224, and 225 serve as intermediate level inverters that lower the input signal to an intermediate level, and the NMOS transistors 246 and 248 and the PMOS transistors 247 and 249 are differential splits. It acts as a level inverter.

3A to 3D are timing diagrams comparing the operation of a conventional CMOS inverter switching circuit with a high speed switching circuit using a differential split level inverter according to the present invention. Referring to FIG. 3A, the signal of the input node 21 and the reference voltage, the signals of the node 22b (FIG. 2) and the node 12b (FIG. 1) are compared. The node 22b signal and the node 12b signal have the same result.

3B illustrates a case in which a full swing voltage is applied to the node 13 and the node 13b (FIG. 1) and a swing voltage limited in half to the node 23 and the node 23b (FIG. 2).

3C and 3D are comparison timing diagrams for the output signals at the output node 14 to which the full swing voltage is applied and at the output node 24 to which the swing voltage is limited in half. Referring to the figure, it can be seen that the speed of the output voltage at node 24 is faster.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

The present invention as described above improves the switching speed by limiting the swing width of the input stage, thereby providing a switching circuit capable of high-speed operation.

Claims (9)

First reference voltage generating means for outputting a predetermined voltage between a supply voltage and a ground voltage according to an input signal; Second reference voltage generating means having the same configuration as the first reference voltage generating means and outputting a predetermined voltage between a supply voltage and a ground voltage according to an inverted signal of the input signal; And A differential split level inverter for outputting a positive output and a negative output of the input signal according to each output of the first reference voltage generating means and the second reference voltage generating means, And said first and second reference voltage generating means limit the swing width of said input signal so that said differential split level inverter has a high switching time. The method of claim 1, And the first and second reference voltage generating means selectively output any one of a supply voltage / 2 or a predetermined voltage between the supply voltage / 2 and the ground voltage according to the input signal. The method of claim 1, wherein the first and second reference voltage generating means A third power transistor is connected to an output terminal through a second MOS transistor connected to a first MOS transistor to which the input signal is applied to the gate, and a third MOS transistor and the third to which the output signal is applied to the gate. A high speed switching circuit, characterized in that connected to the ground power supply terminal via a fourth MOS transistor diode-connected in parallel with the MOS transistor. 4. The fast switching circuit of claim 3, wherein the first MOS transistor is a PMOS transistor. 4. The high speed switching circuit of claim 3, wherein the second to fourth morph transistors are en-MOS transistors. The inverter of claim 3, wherein the differential split level inverter A first MOS transistor connected between the first reference voltage generating means and the constant output terminal for outputting the constant output, and receiving a third reference voltage from an external gate; A second MOS transistor connected between the second reference voltage generating means and the negative output terminal for outputting the negative output, and receiving the third reference voltage from an external gate; A third MOS transistor connected between the constant output terminal and the supply power supply terminal and receiving an output of the first reference voltage generating means through a gate; And And a fourth morph transistor connected between the sub-output terminal and the power supply terminal and receiving an output of the second reference voltage generating means as a gate. The method of claim 5, And the third reference voltage is a value obtained by adding supply voltage / 2 to threshold voltages of the first and second MOS transistors. The method of claim 5, And the first and second morph transistors are en-mo transistors. The method of claim 7, wherein And the third and fourth morph transistors are PMOS transistors.