KR19980078067A - Method of manufacturing thin film transistor of semiconductor device - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs.

Semiconductor device manufacturing method.

2. The technical problem to be solved by the invention.

SUMMARY A method of forming a thin film transistor of a memory device capable of forming a long offset length between a drain and a channel in a process of forming a memory device of a semiconductor device is provided.

3. Summary of the solution of the invention.

After forming the bottom polysilicon gate in the process of forming the bottom gate type thin film transistor, a method of forming a memory device of a semiconductor device may be proposed in which a source line is formed long through a single mask process to improve the conventional problem.

4. Important uses of the invention.

Used in memory device manufacturing process of semiconductor device during semiconductor device manufacturing process.

Description

Thin Film Transistor Degaussing Method of Semiconductor Device

The present invention relates to a manufacturing process of a semiconductor device, and relates to a static-random-access-memory (SRAM) manufacturing process of a semiconductor manufacturing process. In particular, the present invention relates to a method of manufacturing a driving thin film transistor of an SRAM cell. Typically, an SRAM cell consists of two moving transistors, two pull-down N-channel (pull down) driving transistors, and two pull-up P-channel load transistors.

In accordance with the current trend, as semiconductor devices become highly integrated in manufacturing integrated circuits, there are various problems in the semiconductor device manufacturing process. Using a resistor that can reduce 40% of the area of the pull-up transistor to the pull-up device as the cell area is reduced, there is a difficulty in storing information. A thin film transistor is used as a pull-up device.

Hereinafter, a method of forming a thin film transistor using a conventional pull-up thin film transistor manufacturing process will be described in detail with reference to FIG. 1.

1A shows an equivalent circuit of an SRAM cell using a P-channel MOS thin film transistor as a pull-up device. 1B shows a mask process diagram of a thin film MOS transistor. 1C is a sectional view of a P-channel MOS thin film transistor.

As shown in Fig. 1B, a polysilicon film for bottom gate formation is formed on the interlayer insulating film 11 for insulation of the devices. At this time, the polysilicon film is highly pinged with pentavalent impurities to increase conductivity. A gate pattern is formed using a gate forming mask (not shown), and a gate oxide film 13 is formed over the entire structure. Subsequently, the polysilicon 14, 15, 16 for a channel is formed. A drain of the fallup transistor is formed using a drain contact mask for forming a thin film fallup transistor.

As shown in Fig. 1C, an over-overlap (b) of the source region and the vcc portion is formed to increase the on current of the transistor. The on current Ion of the transistor is increased through the offset region of the undoped channel 15 formed on the insulating film between the channel gate 12 and the drain gate 12 region, and the off current Ioff of the transistor is increased. To lower. When the on current of the thin film transistors used as the pull-up elements Q1 and Q2 is large and the off current is small, the thin film transistor performs a role as a load of the SRAM cell, but a problem due to high integration occurs.

As described above, the SRAM using the thin film transistor manufactured according to the prior art has problems such as increase in VCC resistance and difficulty in securing offset length due to high integration, and deterioration in characteristics due to diode formation at the drain region. Development of a manufacturing method has become necessary.

SUMMARY OF THE INVENTION The present invention devised to solve the above problems provides a method of manufacturing a thin film transistor which can improve the conventional problem since the overlap portion between vcc and the gate is increased by adding a mask process after the bottom poly gate is formed. For that purpose.

1A is an equivalent circuit of an SRAM cell using a P-channel MOS thin film transistor as a pull-up element.

1B is a mask process diagram of a thin film MOS transistor.

1C is a cross-sectional view of a P-channel MOS thin film transistor.

2A to 2D are cross-sectional views of a thin film transistor of a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings.

21: interlayer insulation film.

22: polysilicon gate.

23: gate oxide film.

24: source, drain.

25: Offset area.

26: channel.

27: photoresist pattern.

In order to achieve the above object, the present invention comprises the steps of forming a conductive film for the gate on the interlayer insulating film for the isolation of the elements; Forming a first photoresist pattern on the gate conductive film to form a first pattern by a patterning process; Forming a second photoresist pattern on the first pattern, and patterning the second pattern, wherein forming a second pattern by etching each of the exposed interlayer insulating film and the gate conductive film; Forming a gate oxide film over the entire structure; Forming a polysilicon film for the channel over the entire structure; And forming a source and a drain by an ion implantation process.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A to 2D are cross-sectional views of a thin film transistor of a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 2A, a polysilicon gate 22 doped with a pentavalent impurity for forming a MOS transistor is formed on the insulating film 21 for insulating the devices. A gate pattern 22 including a channel gate and a drain gate is formed by using a mask that separates the MOS transistor regions.

Next, as shown in FIG. 2B, after the photoresist film is entirely formed, the photoresist pattern 27 is formed on the poly gate pattern 22 by a photolithography process, and the photoresist pattern on the poly gate pattern is a poly gate. The pattern 27 is formed so that a part of the pattern is exposed.

Next, as shown in FIG. 2C, the anisotropic partial dry etching of the interlayer insulating layer 21 is performed using the photoresist pattern 27 as an etch barrier, and the channel gate 22 and the drain gate 22 are etched. Anisotropic partial dry etching is performed using the above photoresist pattern 27 as an etching barrier, and the remaining photoresist pattern 27 is removed.

Next, as shown in FIG. 2D, the gate oxide layer 23 of the thin film transistor for insulating the gate is formed on the entire structure, and the photoresist layer is formed on the entire structure to form the drain gate 22 through the photolithography process. The gate oxide film 23 on the part is partially etched. Subsequently, channel polys 24, 25 and 26 are formed on the entire structure. Trivalent impurities are ion implanted into the source and drain regions using a source and drain formation mask to form a source and a drain.

The above-described feature of the present invention is to partially etch the exposed interlayer insulating film 21 between the poly gates and partially etch the drain gate and the channel gate by adding one mask process after the bottom poly gate pattern 22 is formed. Is in. As a result, the VCC resistance can be reduced by securing a wider source region a`, and the margin for noise can be increased due to the increase in the overlap region b` between the VCC region and the channel gate. In addition, the offset d ′ between the channel gate and the drain gate can be increased as desired, thereby reducing the off current. In addition, partial etching of the drain gate may increase current characteristics of the thin film transistor due to an increase in the effective area of the PN diode.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the spirit of the present invention. It will be evident to those who have knowledge of.

According to the present invention as described above, the VCC resistance can be decreased by increasing the source region, and the on-current of the device can be increased by increasing the overlap region of the source and channel gates, the drain offset and the effective area of the PN diode are increased. Provided is a method of forming a bottom gate type thin film transistor capable of providing the same.

Claims (3)

Forming a gate conductive film on the interlayer insulating film for insulating the devices; Forming a first pattern by forming a first photoresist pattern on the conductive film for the gate, and forming a first pattern by a patterning process; Forming a second photoresist pattern on the first pattern, and patterning the second pattern, wherein forming a second pattern by etching each of the exposed interlayer insulating film and the gate conductive film; Forming a gate oxide film over the entire structure; Forming a polysilicon film for the channel over the entire structure; And A thin film transistor manufacturing method of a semiconductor device comprising the step of forming a source and a drain by the ion implantation process The method of claim 1, The second pattern is The method of manufacturing a thin film transistor of a semiconductor device, characterized in that the conductive film is insulated after forming each island. The method of claim 2, The polysilicon film for the channel And one of the conductive films formed on the gate coral film and insulated from the islands is formed directly on the conductive film.