KR19980076703A - Semiconductor Memory Device Having Word Line Voltage Generation Circuit - Google Patents

Abstract

The present invention relates to a semiconductor memory device, comprising: a cell array having a plurality of memory cells for storing predetermined information; A plurality of word lines extending in a row direction; A plurality of bit lines extending in the column direction; A voltage generation circuit configured to receive a supply power from an external source and generate a first power supply voltage; A voltage generation circuit configured to receive the supply power and generate a second power supply voltage; A pumping circuit configured to receive the second power supply voltage and output a high voltage in response to a control signal; A detection circuit for receiving the first power supply voltage and the high voltage and comparing the two voltages; A level conversion circuit which receives a signal from the detection circuit and converts the signal into a level of the second power supply voltage to output the control signal; And a row select circuit for selecting one of the rows and for supplying the high voltage onto the word line of the selected row.

Description

Semiconductor Memory Device Having Word Line Voltage Generation Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a circuit for generating a voltage applied to a word line of a memory cell during read / write and a semiconductor memory device using the same.

Dynamic random access memory (DRAM) devices are provided with a cell array as a place for storing information. The cell array is a matrix of memory cells consisting of one NMOS transistor and one cell capacitor used as an access transistor. The gate of the transistor is connected to the word line, one end of which is connected to the bit line and the other terminal to the capacitor, the circuit diagram of which is shown in FIG.

The access transistor is turned on by applying a selection voltage to a word line associated with a memory cell selected for storing or reading information in the memory cell. As a result, the bit line and one terminal of the selected cell capacitor may be electrically coupled to write or read data. When the write / read operation is not performed, the access transistor is turned off to preserve data stored in the capacitor. At this time, the voltage applied to the word line during the write / read operation has a level higher than the threshold voltage of the access transistor (hereinafter, referred to as VPP) when the data stored in the capacitor is at the high level.

2 is a circuit diagram showing a high voltage generation circuit according to the prior art.

Referring to FIG. 2, a high voltage generation circuit for generating a high voltage VPP applied to a word line includes a level detection circuit 10 and a high voltage pumping circuit 20. The detection circuit 10 receives a high voltage VPP and an internal power supply voltage IVC from the high voltage pumping circuit 20 and outputs a signal C that detects the level of the high voltage VPP. And, the high voltage pumping circuit 20 is activated or deactivated in accordance with the signal (C).

3 is a view showing a change in the detection level of the level detection circuit according to the change in the internal power supply voltage.

Since the conventional level detection circuit 10 uses the internal power supply voltage IVC as a power source, when the level of the internal power supply voltage IVC is lowered, its detection level is also lowered. Therefore, when the power supply voltage level is lowered, the high voltage VPP from the high voltage pumping circuit 20 cannot be maintained at a level higher than the high level of the cell capacitor plus the drain voltage. As a result, a normal read / write operation of the DRAM may not be performed.

It is therefore an object of the present invention to provide a circuit which generates a constant high voltage regardless of a change in the internal power supply voltage.

Another object of the present invention is to provide a semiconductor memory device capable of performing a stable read / write operation under a low power supply voltage.

1 is a circuit diagram showing a circuit of a typical DRAM cell array;

2 is a block diagram showing a configuration of a high voltage generation circuit according to the prior art;

3 is a view illustrating a change in a detection level of the level detecting circuit of FIG. 2 according to a change in an internal power supply voltage;

4 is a block diagram showing a configuration of a semiconductor memory device according to the first embodiment of the present invention;

FIG. 5 is a circuit diagram illustrating a level detecting circuit and a level converting circuit of FIG. 4; FIG.

6 is a circuit diagram showing the voltage generation circuit of FIG. 4;

FIG. 7 is a diagram illustrating output voltage characteristics of the voltage generation circuit of FIG. 4; FIG.

8 is a block diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention;

9 is a circuit diagram showing the level detecting circuit and the level converting circuit of FIG. 8;

FIG. 10 is a view showing output voltage characteristics of the second voltage generator circuit of FIG. 8; FIG.

11 is a view showing a change in the internal power supply voltage and a change in the output voltage of the level detection circuit according to the first and second embodiments of the present invention;

* Explanation of symbols on the main parts of the drawings

100: cell array 120: row selection circuit

140: column selection circuit 160: sense amplification circuit

210: first voltage generating circuit 220: level detecting circuit

230: level conversion circuit 240: high voltage pumping circuit

250: second voltage generating circuit

According to one aspect of the present invention for achieving the above object, a means for generating a first voltage by receiving a power supply from the outside; The first voltage increases along its level when the supply power is supplied below a predetermined reference voltage and remains constant at the reference voltage level above the reference voltage; Means for receiving the supply power and outputting a second voltage higher than the supply power in response to a predetermined control signal; Means for receiving the first and second voltages and detecting whether the second voltage is higher than the first voltage and outputting a detection signal; And a means for receiving the detection signal and converting the detection signal to a level of the power supply to output the control signal.

In this embodiment, the reference voltage has a level of about 1.5 volts.

Another feature of the invention is a means for receiving a supply power from the outside for generating a first voltage; The first voltage increases along its level when the supply power is supplied below the first reference voltage and remains constant at the first reference voltage level above the first reference voltage; Means for receiving the supply power to generate a second voltage; The second voltage increases along its level when the supply power is supplied below a predetermined second reference voltage and is maintained at the second reference voltage level between the second reference voltage and the predetermined third reference voltage. And increases along with the supply voltage above the third reference voltage; Means for receiving the second voltage and outputting a third voltage higher than the second voltage in response to a predetermined control signal; Means for receiving the first and third voltages and detecting whether the third voltage is higher than the first voltage and outputting a detection signal; And a means for receiving the detection signal and converting the detection signal to a level of the second voltage to output the control signal.

In this embodiment, the first reference voltage has a level of about 1.5 volts.

In this embodiment, the second reference voltage has a level of about 3 volts.

In this embodiment, the third reference voltage has a level of about 6 volts.

According to still another aspect of the present invention, there is provided a cell array comprising: a cell array having a plurality of memory cells for storing predetermined information; A plurality of word lines extending in a row direction; A plurality of bit lines extending in the column direction; Means for receiving a supply power supply from the outside to generate a first voltage; The first voltage increases along its level when the supply power is supplied below a predetermined reference voltage and remains constant at the reference voltage level above the reference voltage;

Means for receiving the supply power and outputting a second voltage having a predetermined level in response to a predetermined control signal; Means for receiving the first and second voltages and detecting whether the second voltage is higher than the first voltage and outputting a detection signal; Means for receiving the detection signal and converting it to a level of the power supply to output the control signal; Row selecting means for selecting one of the rows and supplying the read voltage from the second voltage generating means onto the word line of the selected row.

In this embodiment, each memory cell includes one transistor and one capacitor.

In this embodiment, the reference voltage has a level of about 1.5 volts.

In this embodiment, the second voltage has a level equal to or higher than the sum of the high level stored by the capacitor and the threshold voltage of the transistor.

Another feature of the invention is a cell array having a plurality of memory cells for storing predetermined information; A plurality of word lines extending in a row direction; A plurality of bit lines extending in the column direction; Means for receiving a supply power supply from the outside to generate a first voltage; The first voltage increases along its level when the supply power is supplied below the first reference voltage and remains constant at the first reference voltage level above the first reference voltage; Means for receiving the supply power to generate a second voltage; The second voltage increases along its level when the supply power is supplied below a predetermined second reference voltage and is maintained at the second reference voltage level between the second reference voltage and the predetermined third reference voltage. And increases along with the supply voltage above the third reference voltage; Means for receiving the second voltage and outputting a third voltage having a predetermined level in response to a predetermined control signal; Means for receiving the first and third voltages and detecting whether the third voltage is higher than the first voltage and outputting a detection signal; Means for receiving the detection signal and converting it to a level of the second voltage to output the control signal; Row selecting means for selecting one of the rows and supplying the third voltage from the second voltage generating means onto the word line of the selected row.

In this embodiment, each memory cell includes one transistor and one capacitor.

In this embodiment, the third voltage has a level equal to or higher than the sum of the high level stored in the capacitor and the threshold voltage of the transistor.

In this embodiment, the first reference voltage has a level of about 1.5 volts.

In this embodiment, the second reference voltage has a level of about 3 volts.

In this embodiment, the third reference voltage has a level of about 6 volts.

By such a circuit and apparatus, the reference voltage for detecting the high voltage level can be kept constant even if the internal power supply voltage fluctuates.

Hereinafter, a reference drawing according to an embodiment of the present invention will be described in detail with reference to FIGS. 4 to 11.

4 and 7, the novel semiconductor memory device of the present invention includes a high voltage generation circuit 200 that generates a word line selection voltage (ie, a high voltage) that remains constant even when the internal power supply voltage IVC changes. to provide. Then, when the internal power supply voltage IVC is applied, the high voltage VPP is increased using the voltage generating circuit 210 that increases along with it and is maintained at the level (1.5 volt) above a predetermined level (for example, 1.5 volt). Level detection circuit 220 is implemented to detect the level Thus, even when the internal power supply voltage IVC changes, a high voltage VPP that maintains a constant level (1.5 volts) can be obtained. In addition, it is possible to prevent degradation of low voltage characteristics of devices operating under low power supply voltages.

First embodiment

Referring again to FIG. 4, a cell array 100 as a place for storing information is a plurality of word lines extending in a row direction as a matrix of memory cells shown in FIG. 1. ) And a plurality of bit lines extending in the column direction cross each other. A row selection circuit 120 is arranged on the left side of the cell array 100 and connected to it via word lines. The circuit 120 receives a row address, selects one of the rows, and provides a high voltage VPP from the high voltage generation circuit 200 on the word line of the selected row.

One of the columns is selected by a column selection circuit 140 and a sensing and amplifing circuit 160 to sense data or write data onto them via a bit line pair of the selected column. It is to convey. The circuits 120, 140, and 160 are well known to those of ordinary skill in the art, although detailed internal circuitry is not shown in this figure.

In addition, the high voltage generation circuit 200 may have a constant level (cell capacitor) regardless of a change in an internal power supply voltage Internal VCC (hereinafter, referred to as IVC) on a word line selected through the row selection circuit 120 during a read / write operation. Is to supply a high voltage (VPP), that is, a word line selection voltage. The voltage generation circuit 210 receives the internal power supply voltage IVC and rises along the voltage IVC when the internal power supply voltage IVC is less than or equal to the reference level Va (for example, 1.5 volts). When the level is equal to or higher than the level Va, the voltage V1 that is kept constant at the reference level Va is output.

The level detector 220 receives the high voltage VPP and the voltage V1 applied to the row selection circuit 120 and detects whether the high voltage VPP is higher or lower than the voltage V1 to detect the detection signal DET. ) When the high voltage VPP is higher than the voltage V1, a high level signal DET is output, and when the high voltage VPP is low, a low level signal DET is output.

The level converting unit 230 converts the level of the signal DET into the level of the internal power supply voltage IVC. When the signal DET having the voltage level of V1 is applied, the level converting unit 230 applies a low level. That is, the control signal C of 0 volts is output, and when the low level signal DET is applied, the control signal C converted to a high level, that is, the level of the internal power supply voltage IVC, is output. The high voltage pumping unit 240 is deactivated when the low level control signal C, that is, the high voltage VPP is higher than the voltage V1, and the high level control signal C, that is, the high voltage VPP is the voltage V1. When it is lower, it is activated to perform a pumping operation to boost the level of the lowered high voltage VPP.

5 is a circuit diagram of a level detecting circuit and a level converting circuit according to a first preferred embodiment of the present invention.

Referring to FIG. 5, the level detection circuit 220 includes a voltage divider 221 and inverters 222 and 223 connected in series. The voltage divider 221 has NMOS transistors having the same characteristic (eg, resistance value at turn-on) in which a current path is connected in series between the terminal 301 to which the voltage V1 is applied and the ground. 302, 304, 306, and 308. The high voltage VPP is applied to the gates of the transistors 302, 304, and 308, and the voltage V1 is applied to the gate of the transistor 306. Since the transistors 302, 304, 306, and 308 operate as active resistors, the transistors 302, 304, 306, and 308 of the transistors 302, 304, 306, and 308 operate as active resistors. Their resistance values vary according to the voltages VPP and V1 applied to the gate, respectively.

Since the voltage V1 is a voltage maintained at a constant level Va as mentioned in FIG. 4, the turn-on resistance of the NMOS transistor 306 to which the voltage V1 is applied is constant. Do. Accordingly, the voltage level at the junction 305 of the transistors 304 and 306 varies depending on the level of the voltage VPP. If the voltage VPP is higher than the voltage V1, the turn-on resistance of the transistors 302 and 304 is smaller than that of the transistors 306 and 308. The potential will be logic high (H). In the opposite case, the potential at connection point 305 will be logic low (logic 'L').

In addition, the inverting unit 222 connected to the level detecting unit 221 includes pull-up PMOS transistors 310 and 312 and a pull-down NMOS transistor (sequentially connected in series between the power supply terminal 301 and ground). 314 to 318, and the gates of the transistors are connected to the connection point 305 in common. The inverting unit 223 includes a pull-up PMOS transistor 320 and a pull-down NMOS transistor 322 in which current paths are sequentially connected in series between the power supply terminal 301 and the ground, and the transistors 320 and Gates of 322 are commonly connected to the connection point 307.

The level converting circuit 230 includes a level shifter 231 and an inverting unit 232. In the NMOS transistor 324 whose gate is connected to the output node 309 of the level detection circuit 220, a current path is connected between the connection point 311 and the ground. The current paths of the PMOS transistor 326 and the NMOS transistor 328 having gates connected to the output node 309 are sequentially connected in series between the power supply terminal 301 and ground. The current path of the NMOS transistor 330 whose gate is connected to the junction 313 of the transistors 326 and 328 is connected between the junction 315 and ground.

Current paths of PMOS transistors 334 and 336 with gates connected to junctions 311 and 315, respectively, between terminal V1 and junction 315 and between terminal V1 and junction 311, respectively. Is connected between the In addition, the inverting unit 232 composed of the PMOS transistor 336 and the NMOS transistor 338 has a gate of the transistors 336 and 338 connected to the connection point 315 and is connected between the terminal V1 and the ground. Current paths are connected in series. The output C of the level conversion circuit 230 is applied to the high voltage pumping circuit 240 of FIG. 4.

When the signal DET from the level detection circuit 220 is at a high level (VPP V1), the transistors 324 and 326 are turned on and the transistor 330 is turned off. At this time, the connection point 311 is transitioned to the low level through the transistor 324, so that the PMOS transistor 334 is turned on. In addition, the connection point 315 becomes a high level through the PMOS transistor 334, and accordingly, the PMOS transistor 332 is turned off. As a result, the output of the level shifter 231 becomes a high level and a low level control signal C is applied to the high voltage pumping circuit 240 through the inverter 232. Thus, the high voltage pumping circuit 240 is deactivated. In the opposite case (VPP V1), the operation of the high voltage pumping circuit 240 is also performed by outputting the high level control signal C to increase the level of the lowered high voltage VPP to the required level. Let's go.

6 is a voltage generation circuit diagram according to a first preferred embodiment of the present invention.

Referring to FIG. 6, the voltage generation circuit 210 receives an external power supply voltage EVC and divides it to output a divided voltage, that is, a voltage V1. The storage 340 is connected between the terminal 341 and the connection point 343 to which the external power supply voltage EVC is applied. The resistor 342 has one end connected to the connection point 343, and the NMOS transistors 344 and 346 having a current path connected in series between its other terminal and ground, respectively, the connection point 343 and the terminal 341, respectively. ) In the PMOS transistor 348 whose gate is connected to the connection point 345, a current path is connected between the connection point 343 and the ground.

The voltage generating circuit 210 having such a configuration has a ratio of resistance, that is, a value of the resistance 340, the resistance 342, the NMOS transistors 344, and (when an external power supply voltage EVC is applied). The level of the voltage V1 is determined according to the ratio of the resistance values of 346. The voltage V1 of the voltage generating circuit 210 according to the preferred embodiment of the present invention is implemented to have a level of about 1.5 volts.

7 is a diagram illustrating output voltage characteristics of the voltage generation circuit of FIG. 4. In FIG. 7, the voltage V1 increases according to the reference voltage Va (approximately 1.5 volts) after the internal power supply voltage IVC is applied and increases when the voltage IVC increases above the reference voltage Va. It has a characteristic of being kept constant at the level of the reference voltage Va.

Second embodiment

8 is a block diagram illustrating a configuration of a semiconductor memory device according to a second embodiment of the present invention. 9 is a circuit diagram illustrating the level detection circuit and the level conversion circuit of FIG. 8. 10 is a diagram illustrating output voltage characteristics of the second voltage generator circuit of FIG. 8.

In FIG. 8, the semiconductor memory device according to the second exemplary embodiment provides a second voltage generator circuit 250 that generates a voltage V2 in the high voltage generator circuit 200. The second voltage generator circuit 250 increases along the voltage IVC while the internal power supply voltage IVC rises to the reference voltage Vb, as shown in FIG. 10, and the voltage Vb and the voltage Vc. It is kept constant in between and increases over voltage (Vc) has the characteristic of increasing again accordingly. Here, the reference voltage Vb is about 3 volts, and the reference voltage Vc has about 6 volts. In addition, the voltage level of the voltage V2 is kept constant at the voltage level of the voltage Vb. It will be apparent to those skilled in the art that the second voltage generator circuit 250 can also be configured in the same manner as that shown in FIG.

The cell array 100, the row selection circuit 120, the column selection circuit 140, the sense amplifier circuit 160, the first voltage generator circuit 210, the level detection circuit 220, and the level conversion shown in FIG. 8. Since the circuit 230 and the high voltage pumping circuit 240 are the same as those in FIG. 4, the description of them here and the configuration shown in FIG. 9 are also the same as those in FIG. 6 to avoid duplication of description. The description of the circuit configuration is omitted here. However, it should be noted that in the case of FIG. 9, the voltage V2 is applied instead of the internal power supply voltage IVC that was applied to the level conversion circuit 230 of FIG. FIG. 11 is a diagram illustrating a sensing level characteristic of a level detection circuit according to an exemplary embodiment of the present invention, which increases with an internal power supply voltage IVC below the reference voltage Va and maintains a constant level above the reference voltage Va. do.

As described above, the present invention provides a reference voltage for sensing a high voltage VPP level, and a voltage V1 that maintains a constant level even when the internal power supply voltage IVC is changed instead of the internal power supply voltage IVC. By providing the output voltage generator circuit 210, the level of the high voltage VPP applied to the word line in the write / read operation can be maintained constant. In this way, stable operation of the device can be performed during the write / read operation.

As described above, it is possible to ensure stable operation of the device during the read / write operation by generating a high voltage which always maintains a constant level even when the internal power supply voltage changes. In addition, it is possible to prevent the deterioration of the low voltage characteristics of the device under low power supply voltage.

Claims (16)

Means for receiving a supply power supply from the outside to generate a first voltage; The first voltage increases along its level when the supply power is supplied below a predetermined reference voltage and remains constant at the reference voltage level above the reference voltage; Means for receiving the supply power and outputting a second voltage higher than the supply power in response to a predetermined control signal; Means for receiving the first and second voltages and detecting whether the second voltage is higher than the first voltage and outputting a detection signal; And a means for receiving the detection signal and converting the detected signal into a level of the power supply to output the control signal. The method of claim 1, And the reference voltage has a level of about 1.5 volts. Means for receiving a supply power supply from the outside to generate a first voltage; The first voltage increases along its level when the supply power is supplied below the first reference voltage and remains constant at the first reference voltage level above the first reference voltage; Means for receiving the supply power to generate a second voltage; The second voltage increases along its level when the supply power is supplied below a predetermined second reference voltage and is maintained at the second reference voltage level between the second reference voltage and the predetermined third reference voltage. And increases along with the supply voltage above the third reference voltage; Means for receiving the second voltage and outputting a third voltage higher than the second voltage in response to a predetermined control signal; Means for receiving the first and third voltages and detecting whether the third voltage is higher than the first voltage and outputting a detection signal; And a means for receiving the detection signal and converting the detected signal into a level of the second voltage to output the control signal. The method of claim 3, wherein And the first reference voltage has a level of about 1.5 volts. The method of claim 3, wherein And the second reference voltage has a level of about 3 volts. The method of claim 3, wherein And the third reference voltage has a level of about 6 volts. A cell array having a plurality of memory cells for storing predetermined information; A plurality of word lines extending in a row direction; A plurality of bit lines extending in the column direction; Means for receiving a supply power supply from the outside to generate a first voltage; The first voltage increases along its level when the supply power is supplied below a predetermined reference voltage and remains constant at the reference voltage level above the reference voltage; Means for receiving the supply power and outputting a second voltage having a predetermined level in response to a predetermined control signal; Means for receiving the first and second voltages and detecting whether the second voltage is higher than the first voltage and outputting a detection signal; Means for receiving the detection signal and converting it to a level of the power supply to output the control signal; And row selection means for selecting one of the rows and supplying the read voltage from the second voltage generating means on a word line of the selected row. The method of claim 7, wherein Wherein each memory cell includes one transistor and one capacitor. The method of claim 7, wherein And the reference voltage has a level of about 1.5 volts. The method according to claim 7 or 8, And the second voltage has a level equal to or higher than the sum of the high level stored by the capacitor and the threshold voltage of the transistor. A cell array having a plurality of memory cells for storing predetermined information; A plurality of word lines extending in a row direction; A plurality of bit lines extending in the column direction; Means for receiving a supply power supply from the outside to generate a first voltage; The first voltage increases along its level when the supply power is supplied below the first reference voltage and remains constant at the first reference voltage level above the first reference voltage; Means for receiving the supply power to generate a second voltage; The second voltage increases along its level when the supply power is supplied below a predetermined second reference voltage and is maintained at the second reference voltage level between the second reference voltage and the predetermined third reference voltage. And increases along with the supply voltage above the third reference voltage; Means for receiving the second voltage and outputting a third voltage having a predetermined level in response to a predetermined control signal; Means for receiving the first and third voltages and detecting whether the third voltage is higher than the first voltage and outputting a detection signal; Means for receiving the detection signal and converting it to a level of the second voltage to output the control signal; And row selecting means for selecting one of the rows and supplying the third voltage from the second voltage generating means onto the word line of the selected row. The method of claim 11, wherein Wherein each memory cell includes one transistor and one capacitor. The method according to claim 11 or 12, And the third voltage has a level equal to or higher than a sum of a high level stored in the capacitor and a threshold voltage of the transistor. The method of claim 11, wherein The first reference voltage has a level of about 1.5 volts. The method of claim 11, wherein And the second reference voltage has a level of about 3 volts. The method of claim 11, wherein The third reference voltage has a level of about 6 volts.