KR19980076571A - Semiconductor memory device and its internal power supply voltage circuit - Google Patents

Abstract

The present invention relates to a semiconductor memory device and its internal power supply voltage supply circuit, comprising: a memory for storing data; Peripheral circuitry for reading data stored in said memory or writing predetermined data into said memory; A power supply voltage supply circuit comprising a power supply for converting an external power supply voltage into an internal power supply voltage in an operation mode and supplying the internal power supply voltage to the memory and the peripheral circuit; The power supplies may operate only until the first power supplies activated during the operation mode and the row address strobe signal indicating the operation mode are activated and the detection signal generated when reading data from the memory is activated. It is divided into two parts. The second power supply unit may include a comparison circuit configured to compare a reference voltage applied from the outside with the internal supply voltage and output a comparison signal in response to a predetermined first control signal; A driver for supplying a predetermined current from the external supply voltage to the output node in response to the comparison signal; A first control circuit for outputting a second control signal in response to a sensing signal for notifying data sensing and a predetermined external signal in an operation mode; And a second control circuit outputting the first control signal in response to an activation signal synchronized with the second control signal and the row address strobe signal.

Description

Semiconductor memory device and its internal power supply voltage circuit

The present invention relates to a semiconductor device, and more particularly, to an internal power supply voltage supply circuit for converting an external power supply voltage to an internal power supply voltage and a semiconductor memory device using the same.

1 is a circuit diagram showing an internal power supply voltage supply circuit according to the prior art. 2 is an operation timing diagram according to the prior art. Conventional operation will be briefly described below with reference to FIGS.

2, the row address strobe signal (a master clock) of the semiconductor memory device ( ) Transitions from a high level to a low level, the internally generated signal PRDD is enabled at a high level and the word lines are sequentially activated. At this time, since a large amount of current is consumed instantaneously when the word lines are activated, the voltage drop DIP occurs as the level of the internal power supply voltage IVC is shown in FIG. 2. Accordingly, the current consumed for stabilizing the level of the internal power supply voltage IVC is compensated for by the internal power supply voltage supply circuit of FIG. 1. 2, activation signals ( ) And ( ) Becomes a low level when the signal PRDD is activated to a high level, thereby operating an internal power supply voltage circuit. Here, the signal of the activation signals ( ) Is the level of the external supply voltage, and the signal ( Is the level of the internal power supply voltage. Therefore, the internal power supply voltage supply circuit can activate the activation signals (Fig. ) And ( ) Remains in operation while the row address strobe signal ( ) Sequentially deactivates the signal PRDD and the activation signals ) And ( ) Is deactivated to stop the operation of the internal supply voltage supply circuit.

However, according to the internal power supply voltage circuit as described above, when the semiconductor memory device is in the operation mode, that is, the row address strobe signal ( While) is active, the internal power supply voltage supply circuit is continuously activated, resulting in an increase in current consumption. In addition, the page mode and extended CBR (battery back-up mode), as shown in FIG. ), The row address strobe signal ( ) Is maintained at a low level for a long time, so that the battery backup mode current ICC7 is consumed in proportion to the operation period tRAS in the long tRAS period.

The semiconductor memory device typically includes a plurality of internal power supply voltage supply circuits for converting an external power supply voltage EVC into an internal power supply voltage IVC, and operates characteristic (on / off) of each internal power supply voltage supply circuit. Characteristics) are required quickly. If the on-state characteristic (operation state) among the operating characteristics of the internal power supply voltage supply circuit is lowered, the amount of current consumed in the semiconductor memory device is increased, and the level of the voltage dip of the internal power supply voltage IVC is deeper. This affects the semiconductor memory device and degrades the overall operating characteristics.

On the other hand, when the off characteristic of the operating characteristics is deteriorated, since the power supply time is longer than the power consumption of the semiconductor memory device, an overshoot phenomenon occurs at the level of the internal power supply voltage IVC, resulting in a noise source. Affects).

The operation characteristic of such a semiconductor memory device is dictated by the PMOS transistor 9 which operates as a driver 50 in the internal power supply voltage supply circuit of FIG. Since the driver size of the PMOS transistor 9 must be set large in order to increase the operating characteristics, the gate loading thereof becomes large. This also causes a problem that the operating characteristics of the internal power supply voltage supply circuit are degraded.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to provide an internal power supply voltage generation circuit for reducing current consumed in an operation mode.

Another object of the present invention is to provide a semiconductor memory device for improving on / off operation characteristics.

1 is a circuit diagram showing a conventional internal power supply voltage circuit;

2 is an operation timing diagram according to an operation mode;

3 is an operation timing diagram according to a battery backup mode;

4 is a block diagram showing a configuration of a semiconductor memory device according to the present invention;

5 is a circuit diagram illustrating a detailed circuit of a second power supply voltage supply circuit and a control circuit of FIG. 4;

6 is an operation timing diagram according to the present invention;

* Description of symbols on the main parts of the drawings *

200: memory 300: peripheral circuit

400a: first power supply circuit 400b: second power supply circuit

500: precharge and equalization

According to one aspect of the present invention for achieving the above object, an internal power supply voltage supply circuit for converting an external supply voltage into an internal supply voltage, comprising: an output node for outputting the internal supply voltage; Comparing means for comparing a reference voltage applied from the outside with the internal supply voltage in response to a first predetermined control signal and generating a comparison signal according to the result; A driver for supplying a predetermined current from the external supply voltage to the output node in response to the comparison signal; Means for generating a second control signal in response to a sensing signal indicative of data sensing and a predetermined external signal in an operation mode; The second control signal is generated at a first voltage level until a row address strobe signal indicating an operation mode is activated and the sense signal is activated, and is generated until the sense signal is activated and the row address strobe signal is deactivated. Occurs at 2 voltage levels; Means for generating the first control signal in response to an activation signal synchronized with the second control signal and the row address strobe signal; The means for generating the first control signal activates the comparing means when the second control signal of the first voltage level is applied and deactivates the comparing means when the first control signal of the second voltage level is applied. Let's do it.

In this embodiment, the first control signal generating means comprises: a first NOR gate having one input terminal to which the activation signal is applied and the other input terminal to which the second control signal is applied; An inverter connected to an output terminal of the first NOR gate; A first PMOS transistor having a gate connected to an output terminal of the inverter, and a source connected to the output node; A second PMOS transistor having a source connected to the drain of the first PMOS transistor, and a gate and a drain connected to each other; And a first NMOS transistor having a gate connected to the output terminal of the inverter, a drain connected to the drain of the second PMOS transistor, and a source to which a ground voltage is applied.

In this embodiment, the second control signal generating means includes: an inverter for inverting and outputting the external signal maintained at the first voltage level in an operation mode; A NAND gate having one input terminal to which the sensing signal is applied and the other input terminal connected to an output node of the inverter; And a level shifter for outputting the second control signal obtained by converting the signal of the second voltage level from the NAND gate to the level of the external power supply voltage.

In this embodiment, the driver section includes a third PMOS transistor having a gate to which the comparison signal is applied, a source to which the external power supply voltage is applied, and a drain connected to the output node.

In this embodiment, the comparing means comprises: a third PMOS transistor having a source to which the external power supply voltage is applied, and a gate and a drain connected to each other; A fourth PMOS transistor having a source to which the external power supply voltage is applied, and a gate connected to the gay of the third PMOS transistor; A second NMOS transistor having a gate to which the reference voltage is applied and a drain connected to the drain of the third PMOS transistor; A third NMOS transistor having a gate connected to the output node and a drain connected to the drain of the fourth PMOS transistor; An NMOS transistor has a drain commonly connected to the sources of the second and third NMOS transistors, a gate to which the second control signal is applied, and a source to which the ground voltage is applied.

In this embodiment, precharge and equalization means for precharging and equalizing the drains of the second and third NMOS transistors to the level of the external power supply voltage in response to the activation signal and the first control signal. It additionally includes.

In this embodiment, the precharge and equalization means comprises: a second NOR gate having one input terminal to which the first control signal is applied and the other input terminal to which the activation signal is applied; A fifth PMOS transistor having a gate connected to an output terminal of the second NOR gate, a source to which the external power supply voltage is applied, and a drain connected to the drain of the third PMOS transistor; And a sixth PMOS transistor having a gate connected to the output terminal of the second NOR gate and a channel connected between the drains of the second and third NMOS transistors.

According to another aspect of the invention, the memory for storing data; Peripheral circuitry for reading data stored in said memory or writing predetermined data into said memory; A power supply voltage supply circuit comprising a power supply for converting an external power supply voltage into an internal power supply voltage in an operation mode and supplying the internal power supply voltage to the memory and the peripheral circuit; The power supplies may operate only until the first power supplies activated during the operation mode and the row address strobe signal indicating the operation mode are activated and the detection signal generated when reading data from the memory is activated. Divided by; The second power supplies include an output node for outputting the internal supply voltage; Comparison means for generating a comparison signal by comparing a reference voltage applied from the outside with the internal supply voltage in response to a first predetermined control signal; A driver for supplying a predetermined current from the external supply voltage to the output node in response to the comparison signal; Means for generating a second control signal in response to a sensing signal indicative of data sensing and a predetermined external signal in an operation mode; The second control signal is generated at a first voltage level until a row address strobe signal indicating an operation mode is activated and the sense signal is activated, and is generated until the sense signal is activated and the row address strobe signal is deactivated. Occurs at 2 voltage levels; Means for generating the first control signal in response to an activation signal synchronized with the second control signal and the row address strobe signal;

The means for generating the first control signal activates the comparing means when the second control signal of the first voltage level is applied and deactivates the comparing means when the first control signal of the second voltage level is applied. Let's do it.

By such a device and a circuit, it is possible to operate all the power supply circuits in a period of high power consumption and to operate only a predetermined number of power supply circuits in a section of low power consumption.

Hereinafter, reference will be made in detail with reference to FIGS. 4 to 6 according to an embodiment of the present invention.

Referring to FIG. 4, the novel semiconductor memory device and the internal power supply voltage generation circuit of the present invention operate only with the first and second internal power supply voltage generation circuits 400a and 400b during a period of high current consumption. A control circuit 500 for controlling the second internal power supply voltage generation circuit 400b is provided. As a result, the current consumed in the operation mode can be reduced, and the on / off operation characteristics can be improved.

4 is a block diagram illustrating a configuration of a semiconductor memory device according to an exemplary embodiment of the present invention.

The semiconductor memory device of FIG. 4 includes a memory area 200, a peripheral circuit 300, a power supply voltage supply circuit 400, and a control circuit 500. The power supply voltage supply circuit 400 converts an external power supply voltage EVC into an internal power supply voltage IVC to the memory 200 and the peripheral circuit 300. The memory 200 and the peripheral circuit operated by the internal power supply voltage IVC are operated to store data, respectively, and write data in the memory 200 or write data in the memory 200. Is to read.

The power supply voltage supply circuit 400 is in active mode with a plurality of first power supply circuits 400a which generate an internal power supply voltage IVC during operation (hereinafter, referred to as an active mode). Second power supply circuits 400b operate only from a point in time to a sensing point for reading data stored in the memory or writing data into the memory 200.

The control circuit 500 operates only from a time point when the second power supply circuits 400b of the power voltage supply circuit 400 enters an active mode to a sensing time point for reading or writing data stored in the memory. To control. The control circuit 500 generates the low level control signal PIVCED only from the time of entering the active mode to the sensing time, that is, while the low level detection signal PS is applied, thereby generating the second power supply circuits ( By activating 400b), an internal power supply voltage IVC is generated by them. After the sensing time point, the sensing signal PS is applied to the high level to generate the control signal PIVCED having a high level. Accordingly, the second power supply circuits 400b are deactivated, thereby being consumed while sensing is performed. Will reduce power.

FIG. 5 is a circuit diagram illustrating a detailed circuit of the second power supply circuit and the control circuit of FIG. 4. A detailed circuit for one of the second power supply circuits of FIG. 4 is shown and the detailed circuit for the remaining circuits is also configured the same.

Referring to FIG. 5, the internal power supply voltage supply circuit according to the present invention includes a comparator 401, a driver 402, a controller 403, and a precharge and equalization unit 404, and enter the active mode. And a second power supply circuit 400b that operates only until a sensing time point, and a control circuit 500 for controlling the second power supply circuit 400b. The comparison unit 401 compares the internal power supply voltage IVC and the reference voltage VREFP and generates a comparison signal S_COMP according to the result. That is, when the internal power supply voltage IVC is at a level higher than the reference voltage VREFP, the comparison signal S_COMP is output at a high level. On the other hand, when the internal power supply voltage IVC is lower than the reference voltage VREFP, the comparison signal S_COMP is output at a low level.

The comparison unit 401 includes PMOS transistors 101 and 102 and NMOS transistors 103, 104, and 105. The PMOS transistor 101 is supplied with an external power supply voltage EVC and a gate and a drain are connected to each other. The external power supply voltage EVC is applied to the PMOS transistor 102 by a source, and a gate thereof is connected to the gate of the PMOS transistor 101. The reference voltage VREFP is applied to a gate of the NMOS transistor 103, and a drain thereof is connected to the drain of the PMOS transistor 101. The NMOS transistor 104 has a gate applied with the internal power supply voltage IVC, and a drain thereof is connected to the drain of the PMOS transistor 102. In the NMOS transistor 105, a drain is commonly connected to each drain of the NMOS transistors 103 and 104, a gate is connected to the controller 403, and a ground voltage VSS is applied to the source.

The driver 402 may be configured to provide a source connected to a source to which an external power supply voltage EVC is applied, a gate to which the comparison signal S_COMP is applied, and a conductive path L1 for transferring the internal power supply voltage IVC. It has a PMOS transistor 109 having. The driving unit 402 is activated when the comparison signal S_COMP at a low level is applied, and accordingly, a constant current is supplied from the external power supply voltage EVC to the conductive path L1 for the transfer of the internal power supply voltage IVD. Supply. On the other hand, the driving unit 402 is deactivated when the comparison signal S_COMP of high level is applied and the current supply is cut off. In addition, a MOS diode D1 having a drain connected to the conductive path and a source and a gate to which the external power supply voltage EVC is applied is provided.

In addition, the controller 403 may control the control signal PIVCED generated from the control circuit 500 and the row address strobe signal indicating the operation mode ( Activation signal synchronized to ) Generates an internal signal S_CONT. The activation signal ( ) Is a signal maintained at the low level during this period when entering the active mode. In this case, when the control signal PIVCED is applied at a low level, the internal signal S_CONT is output at a high level. On the other hand, when the control signal PIVCED is applied at a high level, the internal signal S_CONT is output at a low level.

The control unit 403 includes PMOS transistors 110 and 111, an NMOS transistor 112, an inverter 113, and a NOR gate 114. The NOR gate 114 is a single input terminal to the internal signal ( ) Is applied and the control signal PIVCED is applied to the other input terminal. An input terminal is connected to the output terminal of the NOR gate 114 of the inverter 113. The PMOS transistor 110 is supplied with the internal power supply voltage IVC and a gate thereof is connected to the inverter 113. The PMOS transistor 111 has a source connected to the drain of the PMOS transistor 110 and a gate and a drain connected to each other. The NMOS transistor 112 has a gate connected to the output terminal of the inverter 113, a drain connected to the drain of the PMOS transistor 111, and the ground voltage VSS is applied to the source.

In addition, the precharge and equalizer 404 generates an activation signal ( ) And the drains of the NMOS transistors 401 and 402 of the comparator 401 to the same level in response to the control signal PIVCED. The precharge and equalization unit 404 includes a NOR gate 106 and PMOS transistors 107 and 108. The NOR gate 106 is connected to one input terminal of the activation signal ( ) Is applied and the control signal PIVCED is applied to the other input terminal. In addition, a gate of the PMOS transistor 107 is connected to an output terminal of the NOR gate 106, an external power supply voltage EVC is applied to a source, and a drain thereof is a drain of the PMOS transistor 101 of the comparator 401. Is connected to. The PMOS transistor 108 has a gate connected to an output terminal of the NOR gate 106 and a source-drain channel connected between each drain of the NMOS transistors 103 and 104 of the comparator 401. have. Here, the activation signal ( And the input level of the control signal PIVCED are the levels of the external power supply voltage EVC.

Finally, the control circuit 500 generates the control signal PIVCED in response to the sensing signal PS and the external signal PWBE applied from the outside. The external signal PWBE is a signal applied at a low level in an operation mode and at a high level in other modes (eg, a wafer burn-in test mode). Therefore, the control circuit 500 may know that the level of the control signal PIVCED is determined according to the level of the detection signal PS.

The control circuit 500 includes an inverter 115, a NAND gate 116, and a level shifter 502. The inverter 115 inverts and outputs the phase of the external signal PWBE, and the NAND gate 116 is applied with the detection signal PS to one input terminal and the other input terminal of the inverter 115. An output terminal is connected to an input terminal of the level shifter 501. The level shifter 501 inputs the level of the control signal PIVCED to the control unit 403 since the input level of the sensing signal PS and the external signal PWBE is a level of an internal power supply voltage IVC. The level is changed to the level of the external power supply voltage EVC. The resistors 123 and 125 and the capacitor 124 in the control circuit 500 are used to drive the second power supplies 400b by delaying the sensing signal PS by a predetermined time. It may be selectively used according to the output level of the two voltage supplies 400b.

6 is an operation timing diagram according to the present invention. The operation according to the present invention will be described below with reference to FIGS. 4 to 6.

In Fig. 6, the row address strobe signal ( ) Is activated from the high level to the low level, the signal PRDD is activated to the high level, and accordingly the activation signals ( ) And ( ) Is activated at the low level. At the same time, since the sensing signal PS and the external signal PWBE are applied at a low level, the control circuit 500 generates a low level control signal PIVCED. Accordingly, the control unit 403 is a low level of the activation signal ( And the high level internal signal S_COMP by the control signal PIVCED to activate the NMOS transistor 105 of the comparator 401 and deactivate the precharge and equalizer 404. As a result, when the internal power supply voltage IVC becomes lower than the reference voltage VREFP, a constant current is supplied to the conductive path L1 through the PMOS transistor 109. When the internal power supply voltage IVC is at a level higher than the reference voltage VREFP, the PMOS transistor 109 is turned off to cut off the supply of current to the conductive path L1.

The row address strobe signal ( Is activated, the signal PRDD is activated and the word lines are sequentially activated. When the word lines are activated, as shown in FIG. 6, a large amount of current is instantaneously consumed to generate a voltage dip in the internal power supply voltage IVC. As such, in the period in which a large amount of current is consumed as the word lines are activated, both the first and second power supply circuits 400a and 400b of the internal power voltage supply circuit 400 shown in FIG. 4 are activated. To compensate for the current consumed. In addition, the second power supply circuits 400b are deactivated and only the first power supply units 400a are activated in a section where current consumption is low. That is, the control circuit 500 generates the control signal PIVCED at the high level because the sensing signal PS is applied at a high level at the time when the detection signal PS is activated. As a result, the internal signal S_COMP having a low level is generated by the controller 403 to deactivate the comparator 401 of the second power supply units 400b, and PMOS transistors 107 and 108 are turned on to equalize each drain of NMOS transistors 103 and 104 to the same level. At the same time, the first power supplies 400a continue to operate in the active mode to generate an internal power supply voltage IVC.

As described above, the internal power supply voltage supply circuit of the semiconductor memory device operates continuously during the active mode, and the second power supply unit 400a operates only until the detection signal PS is activated at the time of entering the active mode. By separating the power supply units 400b, the size of the PMOS transistors 409 of each driver 402 may be designed to be small. As a result, the gate loading of the PMOS transistor 409 may be reduced, thereby speeding up the on / off operation characteristic of the internal power supply voltage supply circuit 400. In addition, the overall power consumption can be reduced by operating only the first power supplies 400a in a low power consumption period, and the internal power supply voltage IVC can be reduced due to the fast cut-off characteristic of the semiconductor memory device. Overshoot) can be prevented.

As described above, by controlling the circuits that supply the internal power supply voltage into a group that operates only in an operation of high power consumption and a group that always operates in an active mode, the driver size of each group can be reduced, and the semiconductor memory The overall power consumption of the device can be reduced. In addition, as the driver size is reduced, the off characteristic of the operating characteristics is faster, thereby preventing overshoot of the internal power supply voltage.

Claims (8)

An internal power supply voltage supply circuit for converting an external supply voltage into an internal supply voltage, An output node for outputting the internal supply voltage; Comparing means for comparing a reference voltage applied from the outside with the internal supply voltage in response to a first predetermined control signal and generating a comparison signal according to the result; A driver for supplying a predetermined current from the external supply voltage to the output node in response to the comparison signal; Means for generating a second control signal in response to a sensing signal indicative of data sensing and a predetermined external signal in an operation mode; The second control signal is generated at a first voltage level until a row address strobe signal indicating an operation mode is activated and the sense signal is activated, and is generated until the sense signal is activated and the row address strobe signal is deactivated. Occurs at 2 voltage levels; Means for generating the first control signal in response to an activation signal synchronized with the second control signal and the row address strobe signal; The means for generating the first control signal activates the comparing means when the second control signal of the first voltage level is applied and deactivates the comparing means when the first control signal of the second voltage level is applied. Internal power voltage supply circuit. The method of claim 1, The first control signal generating means, A first NOR gate having one input terminal to which the activation signal is applied and the other input terminal to which the second control signal is applied; An inverter connected to an output terminal of the first NOR gate; A first PMOS transistor having a gate connected to an output terminal of the inverter, and a source connected to the output node; A second PMOS transistor having a source connected to the drain of the first PMOS transistor, and a gate and a drain connected to each other; An internal power supply voltage supply circuit comprising a first NMOS transistor having a gate connected to an output terminal of the inverter, a drain connected to a drain of the second PMOS transistor, and a source to which a ground voltage is applied. The method of claim 2, The second control signal generating means, An inverter for inverting and outputting the external signal maintained at the first voltage level in an operation mode; A NAND gate having one input terminal to which the sensing signal is applied and the other input terminal connected to an output node of the inverter; And a level shifter configured to output the second control signal converted from the NAND gate to a level of the external power voltage when the signal of the second voltage level is output. The method of claim 1, The driving unit, And a third PMOS transistor having a gate to which the comparison signal is applied, a source to which the external power supply voltage is applied, and a drain connected to the output node. The method of claim 3, wherein The comparison means, A third PMOS transistor having a source to which the external power supply voltage is applied and a gate and a drain connected to each other; A fourth PMOS transistor having a source to which the external power supply voltage is applied, and a gate connected to the gay of the third PMOS transistor; A second NMOS transistor having a gate to which the reference voltage is applied and a drain connected to the drain of the third PMOS transistor; A third NMOS transistor having a gate connected to the output node and a drain connected to the drain of the fourth PMOS transistor; And an NMOS transistor having a drain commonly connected to the sources of the second and third NMOS transistors, a gate to which the second control signal is applied, and a source to which the ground voltage is applied. The method of claim 1, And in response to the activation signal and the first control signal, precharge and equalization means for precharging and equalizing the drains of the second and third NMOS transistors to the level of the external power supply voltage. Internal power supply voltage circuit. The method of claim 6, The precharge and equalization means, A second NOR gate having one input terminal to which the first control signal is applied and the other input terminal to which the activation signal is applied; A fifth PMOS transistor having a gate connected to an output terminal of the second NOR gate, a source to which the external power supply voltage is applied, and a drain connected to the drain of the third PMOS transistor; And a sixth PMOS transistor having a gate connected to an output terminal of the second NOR gate and a channel connected between the drains of the second and third NMOS transistors. A memory for storing data; Peripheral circuitry for reading data stored in said memory or writing predetermined data into said memory; A power supply voltage supply circuit comprising a power supply for converting an external power supply voltage into an internal power supply voltage in an operation mode and supplying the internal power supply voltage to the memory and the peripheral circuit; The power supplies may operate only until the first power supplies activated during the operation mode and the row address strobe signal indicating the operation mode are activated and the detection signal generated when reading data from the memory is activated. Divided by; The second power supply, An output node for outputting the internal supply voltage; Comparison means for generating a comparison signal by comparing a reference voltage applied from the outside with the internal supply voltage in response to a first predetermined control signal; A driver for supplying a predetermined current from the external supply voltage to the output node in response to the comparison signal; Means for generating a second control signal in response to a sensing signal indicative of data sensing and a predetermined external signal in an operation mode; The second control signal is generated at a first voltage level until a row address strobe signal indicating an operation mode is activated and the sense signal is activated, and is generated until the sense signal is activated and the row address strobe signal is deactivated. Occurs at 2 voltage levels; Means for generating the first control signal in response to an activation signal synchronized with the second control signal and the row address strobe signal; The means for generating the first control signal activates the comparing means when the second control signal of the first voltage level is applied and deactivates the comparing means when the first control signal of the second voltage level is applied. A semiconductor memory device.