KR19980076054A - Test device for communication terminal - Google Patents

Abstract

The present invention relates to a test device for a communication terminal, and more particularly, to a test device for a communication terminal to increase the utilization efficiency of the system memory using the test memory.

The test apparatus for a communication terminal according to the present invention includes a communication terminal for controlling peripheral devices by a program of a system memory and a system memory storing at least two or more peripheral devices and a program for controlling the peripheral devices, and a peripheral of the communication terminal. A test memory that stores a program for testing devices, and a switch installed in a communication terminal to selectively connect the system memory and the test memory to the CPU by connecting the CPU so that the CPU tests the peripheral devices according to the program of the test memory. Means.

The test apparatus for a communication terminal having a test memory according to the present invention can increase the memory utilization efficiency of the system memory of the communication terminal by using the test memory. And the test device for a communication terminal having a test memory according to the present invention can reduce the inconvenience and time to download the test program from the outside.

Description

Test device for communication terminal

1 is a block diagram of a test apparatus for a conventional communication terminal.

2 is a block diagram of a test apparatus for a communication terminal according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: central processing unit 20: system memory

30: External input / output port 40: Memory

50 to 70: Test block 80: Connection port

90: OR gate 100: pull-down resistor

110: test memory 120: tester

130: printed circuit board 140: switching unit

150: chip select signal transmission unit

The present invention relates to a test device for a communication terminal, and more particularly, to a test device for a communication terminal to increase the utilization efficiency of the system memory using the test memory.

In general, communication terminals have tended to become multifunctional for processing various information. In order to satisfy the trend of multifunctional communication terminals, sufficient processing speed and memory capacity must be secured. Multifunctional communication terminals are also driving increasing test requirements. The test of the communication terminal is performed through arithmetic processing of a test program by the central processing unit. The test program is embedded in the system memory (ROM) together with other programs at the time of manufacture. Alternatively, in the case of using fresh memory, there is a method of downloading a test program from the outside (Down Load). The central processing unit of the communication terminal reads a test program from the system memory or the fresh memory and executes a test on a circuit for each function. As communication terminals become more versatile, test program capacity is also increasing due to the increase in test requirements. System memory allocates a significant portion of memory to accommodate the capacity of the test program. This greatly reduces the memory utilization efficiency of the communication terminal. In addition, a problem due to the capacity acceptance of the test program increases the size of the communication terminal and leads to an increase in material costs.

As a result, the test apparatus of the conventional communication terminal may be difficult to accommodate all the test requirements due to the limitation of the memory capacity of the system memory of the communication terminal, and the inconvenience of wasting time and time downloading the test program from the outside. It is causing. With reference to Figure 1 attached to the problem of the test apparatus for a conventional communication terminal will be described in detail.

Referring to FIG. 1, at least two or more test blocks 50 to 70 having respective functions, a central processing unit 10 for computing a test program, and a system memory or a built-in test program are provided. Fresh memory 20 for downloading and storing a test program, an external input / output port 30 for connecting the central processing unit 10 and an external peripheral device not shown, and the test data under the control of the central processing unit 10. A test apparatus for a conventional communication terminal having a memory 40 for storing the same is shown.

The system memory (ROM) 20 or the fresh memory is serially connected to a central processing unit (hereinafter referred to as CPU) 10.

The external input / output port 30 is connected in series with the CPU 10. The CPU 10 reads a test program from the system memory (ROM) 20 and performs arithmetic processing. In this case, the test program is embedded in the system memory 20 at the time of manufacture. The CPU 10 processes the test program to execute a test on at least two test blocks 50 to 70 having respective functions. The test blocks 50 to 70 are peripheral devices each having a unique function. The memory 40 stores test data under the control of the CPU 10 and transmits it to the CPU 10.

In the case of using the fresh memory 20, the test memory is downloaded from the external peripheral device not shown through the external input / output port 30 under the control of the CPU. The CPU 10 reads a test program from the fresh memory 20 and executes a test on the test blocks 50 to 70. On the other hand, the user can change the test mode or set the test parameters by connecting the input device and the external input and output port 30 not shown. In addition, the user may display on an output device not shown.

As a result, the test apparatus for a conventional communication terminal can limit the memory utilization efficiency of the system with the built-in test program, and causes inconveniences and waste of time downloading the test program from the outside.

Accordingly, an object of the present invention is to provide a test device for a communication terminal that can increase the memory utilization efficiency of the system memory by using a test memory incorporating a test program.

Another object of the present invention is to provide a test device for a communication terminal that reduces the inconvenience and time of downloading by directly connecting the CPU and the test memory.

In order to achieve the above object, the test apparatus for a communication terminal according to the present invention is a communication terminal for controlling the peripheral devices by the program of the system memory and the system memory storing at least two or more peripheral devices and a program for controlling the peripheral devices. And a test memory storing a program for testing peripheral devices of the communication terminal, and installed in the communication terminal and selectively connecting the system memory and the test memory to the CPU by connection of the CPU so that the CPU according to the program of the test memory. Switching means for testing the devices.

Other objects and advantages of the present invention other than the above objects will become apparent from the detailed description of the preferred embodiments of the present invention with reference to the accompanying drawings.

Hereinafter, with reference to the accompanying Figure 2 of the embodiment of the present invention will be described in detail.

2 shows a test apparatus for a communication terminal having a test memory according to an embodiment of the present invention.

2, the communication terminal according to the present invention comprises at least two test blocks 50 to 70 having respective functions, a test memory 110 having a test program therein, and a test memory 110. A mounted tester 120, a system memory 20 without a built-in test program, a CPU 10 for selectively controlling the system memory 20 and a test memory 110, a CPU 10 and a system memory And a switching unit 140 for selectively switching the connection of the test memory 110 and the test memory 110.

The CPU 10 may read / write an address bus via the first node 1, a data bus via the second node 2, and a third bus 3 via the third bus 3. It is connected in parallel to the system memory 20 and the connection port 80 via a read / write control bus. System memory 20 may also be fresh memory. The CPU 10 is connected to an input terminal of the switching unit 140 via a chip select control bus via the fourth node 4. The test blocks 50 to 70 are connected in series with the CPU 10, respectively. The test blocks 50 to 70 are peripheral devices of the communication terminal having unique functions.

The above components are configured in the printed circuit board (PCB) 130 of the communication terminal. The test memory 110 is connected to the connection port 80 by an address bus and a read / write control bus. The enable terminal 9 of the tester 120 is connected to the input terminal of the switching unit 140 via the connection port 80. System memory 20 has its own It is driven by a Chip Select signal with a low logic value at its terminal.

When the tester 120 mounted with the test memory 110 is connected to the CPU 10 of the communication terminal via the connection port 80, the enable signal generated in the control signal generator not shown in the tester is A high logic value is applied to the switching unit 140 as an input signal via the connection port 80. The switching unit 140 generates a chip select signal with a logic value of high as an output signal in response to an enable signal of the tester 120. System memory 20 has its own It cannot be driven by a high Chip Select signal input to the terminal. Therefore, the communication path between the CPU 10 and the system memory 20 is switched by the enable signal of the tester 120. Due to the switching of the CPU 10 and the system memory 20, the CPU 10 directly controls the test memory 120 connected in parallel to read a test program from the test memory 110. The CPU 10 then tests at least two test blocks 50 to 70 having respective functions by the test program.

When the test memory 110 of the tester 120 is not connected to the CPU 10 of the communication terminal, A low chip select signal is input to the terminal. The system memory 20 is driven by a low chip select signal. As a result, the CPU 10 controls the system memory 20.

To this end, the switching unit 140 includes a connection port 80 and a chip select signal transmission unit 150 for connecting the CPU 10 and the test memory 110.

In addition, the chip select signal transfer unit 150 further includes an OR gate 90 and a pull-down resistor 100. The pull-down resistor 100 is connected between the fifth node 5 and the ground voltage source GND to detect whether the test memory 110 of the tester 120 is connected to the connection port 80. The pull-down resistor 100 is connected between the fifth node 5 and the ground voltage source GND. The input signal of the chip select signal transmitter 150 is a chip select signal generated by the CPU 10 and an enable signal generated by the tester 120. The OR gate 90 of the chip select signal transfer unit 150 generates an output signal having a logic value of high or a logic value of low as a result of an OR operation of two input signals. If the enable signal of the tester 120 is applied to the input terminal of the OR gate 90 of the chip select signal transmission unit 150 with a high logic value, the output of the OR gate 90 is the input signal of the other side Regardless of the logic condition of the chip select signal generated in the CPU 10, the system memory 20 is set to a high logic value. It is input to the terminal. The pull-down resistor 100 prevents the output terminal from being uncertain when the tester 120 is not connected, that is, the input terminal of the switching unit 140 is opened. The pull-down resistor 100 keeps the logic condition of the enable signal input terminal low when the enable signal of the tester 120 that is the input signal of the OR gate 90 is switched.

As a result, when the test memory 110 of the tester 120 is connected to the communication terminal via the connection port 80, the test memory 110 replaces the system memory 20.

To this end, the address bus and the data bus of the CPU 10 and the system memory 20 are matched 1: 1 with the address bus and the data bus of the test memory 110. In addition, the capacity of the test memory 110 of the tester 120 is determined according to the capacity of the test program, and has the same access speed as the system memory 20.

As described above, the test apparatus for a communication terminal having the test memory according to the present invention can increase the memory utilization efficiency of the system memory of the communication terminal by using the test memory. And the test device for a communication terminal having a test memory according to the present invention can reduce the inconvenience and time to download the test program from the outside.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (4)

A system memory storing at least two or more peripheral devices and a program for controlling the peripheral devices, and a communication terminal for controlling the peripheral devices by the program of the system memory; A test memory storing a program for testing the peripheral devices of the communication terminal; And switching means for selectively connecting the system memory and the test memory to the CPU by the connection of the CPU so that the CPU tests the peripheral devices according to the program of the test memory. Test device for communication terminals. The method of claim 1, The switching means includes a connection port for connecting the test memory to the CPU in parallel with the system memory; And a chip select signal transfer means for transferring the chip select signal from the CPU to either the test memory or the system memory. The method of claim 2, The chip select signal transmitting means comprises: detecting means for detecting whether the test memory is connected; And a control switch for switching the chip select signal from the CPU to the system memory and the test memory in accordance with an output signal of the detection means. The method of claim 1, And the test memory has the same access speed as the system memory.