KR19980073871A - Data driving circuit and method of liquid crystal display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a data driving circuit and a method of a liquid crystal display device which can simplify the lay-out of a data driver.

The present invention is based on the first memory and the second memory for storing the digital image signal data 1/2 line, the shift register for shifting and outputting the dot clock signal, and the clock signal output from the shift register A first latch unit for latching and outputting digital video signal data of 1/2 line of the first half, a second latch unit for latching and outputting digital video signal of half of the second half by a clock signal of the shifter register unit; And a third latch unit for latching and outputting the 1/2 line digital video signal output from the second latch unit again, and an analog corresponding to the digital video signal output from the first latch unit and the third latch unit. The first half line data of each line of the digital / analog conversion unit for outputting the video signal and the input digital video signal data is the first memory or After temporarily stored in the second memory is configured to include a controller that outputs to latch to the first latch portion and controlling such that the data of the second half of a half line of each line is latched in the second latch section directly.

Description

Data driving circuit and method of liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a data driving circuit and a method of a liquid crystal display device which can simplify the lay-out of a data driver.

In general, a liquid crystal display device includes a liquid crystal panel for displaying an image directly and a data driving circuit for driving the liquid crystal panel so that the image is displayed on the liquid crystal panel.

Such a liquid crystal panel includes a liquid crystal enclosed between an upper plate and a lower plate, and an upper plate and a lower plate.

Here, the upper plate is arranged with a color filter layer of R (red), G (green), and B (blue) for displaying the common electrode and the black matrix layer, and the lower plate has a plurality of data lines and gate lines at regular intervals. Pixel regions in a matrix form are arranged in a direction perpendicular to each other and between the data line and the gate line. In this case, one thin film transistor and one pixel electrode are arranged in each pixel region.

The data driving circuit converts the AV / OA video signals R, G, and B, which are analog types, into digital video signals by an analog / digital converter, and applies them to the column (data) lines of the panel through gamma correction.

Referring to the data driving circuit of the conventional liquid crystal display device with reference to the accompanying drawings in detail as follows.

1 is a block diagram of a data driving circuit of a conventional liquid crystal display device.

As shown in FIG. 1, a data driving circuit of a conventional liquid crystal display device includes a shift register 1 for shifting a dot clock signal and outputting R, G, and B digital image signals. The first latch unit 2 latched and output by the clock signal output from (1), and the digital R, G, B of each pixel output from the first latch unit 2 by an external latch clock signal. A second latch unit 3 for latching and outputting the video signal again, a level shifter 4 for outputting a voltage corresponding to the digital R, G, and B video signals output from the second latch unit 3, And a digital / analog converter 5 for outputting a digital video signal as an analog video signal according to the voltage output from the level shifter 4.

The operation of the data driving circuit of the conventional liquid crystal display device configured as described above is as follows.

The first latch unit 2 latches the digital video signal of one line until the last bit is turned on by the pulse (dot-clock) of the shift register unit 1. After the last bit is turned on, the first latch unit 2 outputs the latched data to the second latch unit 3.

The second latch portion 3 stores the input data while the data of the next line is latched in the first latch portion 2 in the same manner as described above, and then completely latches the data in the first latch portion 2. When the second latch unit 3 outputs the stored data to the level shifter unit 4 and receives the data from the first latch unit 2 again.

Data output from the second latch unit 3 is output a voltage corresponding to the digital data by the level shifter (4) and the digital analog converter 5 converts an analog voltage corresponding to the digital image signal data into each data line. It supplies to the data of 1 line.

In this way, the first latch unit 2 receives the data of one line until the end and outputs the data to the second latch unit 3 all at once, and the data transferred to the second latch unit 3 at once are digital / analog converters. The analog signal is supplied to the liquid crystal panel via (5).

This method is a conventional method of driving a polysilicon TFT-LCD by incorporating a circuit as shown in FIG. 1, as shown in FIG. 2, wherein a data conversion time of digital / analog conversion for each position on a panel is constant. That's the way. In addition, the data driver IC driving the amorphous silicon TFT-LCD also has a structure as shown in FIG.

The data driving circuit of the conventional liquid crystal display device has the following problems.

First, the effective area of the liquid crystal panel has been reduced since two latches must be used conventionally, and each latch must have a memory capacity capable of storing one line of data.

That is, the data driving circuit of the liquid crystal display device may be divided into a part located on the liquid crystal panel and a part located on the PCB substrate. The data driving circuit described in FIG. 1 is a driving circuit located on the liquid crystal panel. As the complexity increases, the effective area of the liquid crystal panel decreases.

Second, as the area occupied by the circuit becomes larger, there is a limit to the increase in the minimum line width, which makes it difficult to overcome the process limit pattern technology and thus the yield is reduced.

The present invention has been made to solve such a problem, and the data driving circuit of the liquid crystal display device that can reduce the area occupied by the latch portion, simplify the circuit, increase the effective area to increase the minimum line width and increase the yield; The purpose is to devise a driving method.

1 is a block diagram of a data driving circuit of a conventional liquid crystal display device.

2 is a comparison diagram of data conversion times of ADCs for each position on a panel in a conventional LCD.

3 is a block diagram of a data driving circuit of the liquid crystal display device of the present invention.

4 is a comparison diagram of data conversion times of ADCs for each position on a panel in the LCD of the present invention.

5 is an explanatory diagram of a liquid crystal display data driving method of the present invention;

* Description of the symbols for the main parts of the drawings *

11: shifter register section 12, 13, 14: latch section

15: level shifter section 16: digital / analog converter

21: controller 22, 23: memory

The data driving circuit of the liquid crystal display device of the present invention for achieving the above object includes a first memory and a second memory for storing digital image signal data every half line, and a shift register unit for shifting and outputting a dot clock signal. And a first latch section for latching and outputting digital video signal data of the first half line by the clock signal output from the shift register section, and a half line of the second half section by the clock signal of the shifter register section. A second latch unit for latching and outputting a digital video signal, a third latch unit for latching and outputting a 1/2 line digital video signal outputted from the second latch unit, the first latch unit, and a first latch unit A digital / analog converter for outputting an analog video signal corresponding to the digital video signal output from the latch unit, and the input digital video signal data The first half line data of each line is temporarily stored in the first memory or the second memory and then output to be latched to the first latch unit, and the data of the second half line of each line is directly transmitted to the second latch unit. Its feature is that it includes a controller that controls to be latched.

In addition, the data driving method of the liquid crystal display device of the present invention to achieve the above object is to divide the input digital video signal into 1/2 line signal so that the half line signal in the first half of each line is temporarily stored and outputted. The first half of the second half line signal is immediately output, and the first half line signal of the first half line signal that is temporarily stored and output is first latched, and the second half line signal is secondly latched. And a third step of simultaneously outputting half-line signals of the first half and the second half of the line, and a third step of converting the digital image signal output in the second step into an analog and applying them to the data line of the liquid crystal panel. There is a characteristic in that it is done.

Referring to the data driving circuit and method of the liquid crystal display of the present invention as described above in more detail with reference to the accompanying drawings.

3 is a block diagram of a data driving circuit of the liquid crystal display device of the present invention, FIG. 4 is a comparison diagram of data conversion times of ADCs for each position on a panel in the liquid crystal display device of the present invention, and FIG. 5 is a liquid crystal of the present invention. An illustration of a display device data driving method.

The data driving circuit of the liquid crystal display of the present invention has a shift register section 11 for shifting and outputting a dot clock signal as shown in FIG. 3 and a half line by a clock signal output from the shift register section 11. A first latch unit 12 for latching and outputting digital video signal data; and a second latch for latching and outputting the remaining 1/2 line digital video signal by a latch clock signal external to the shifter register unit 11; A third latch unit 14 for latching and outputting the digital video signal of 1/2 line again outputted from the second latch unit 13, the first latch unit 12, A level shifter 15 for outputting a voltage corresponding to the digital R, G, and B video signals output from the third latch unit 14, and an analog video signal according to the voltage output from the level shifter 15; Digital / analog conversion to output signal It is composed of 16.

Here, in the liquid crystal display device, that is, it is difficult to use the level shifter unit 15, that is, an active-matrix LCD, the output of the first latch unit 12 does not constitute the level shifter 15. The output of the third latch unit 14 may be configured to be directly input to the digital / analog converter 16.

The digital video signal supply unit supplying the digital video signal to the data driving circuit is as follows.

That is, the first memory 22 and the second memory 23 that store the digital video signal data, and the first half line of each line of the input digital video signal data are the first memory 22 or the second memory. After the temporary storage in the memory 23, the output to be latched to the first latch unit 12, and the controller 21 for controlling the data of the second half line of each line to be immediately latched to the second latch unit (13) It is composed.

The operation of the data driving circuit of the liquid crystal display device of the present invention configured as described above is as follows. same.

The present invention divides the liquid crystal panel into 1/2 and the front part is driven by a point at a time method, and the second part is driven by a line at a time method. Therefore, in order to display the input digital video signal on the liquid crystal panel, the input order of data must be changed.

That is, in FIG. 5, each line is divided into 1/2, and the digital video signal of the first half is directly input from the first latch unit 12 to the digital / analog converter 16, but the digital video signal of the second half is of the second latch. (13) and after being latched in the third latch portion 14, they are input to the digital / analog converter 16 so that the half line video signal of the second half must be latched before the half line video signal of the first half.

Therefore, when the configuration of the video signal to be displayed is as shown in Fig. 5, the data input sequence is A → D → C → F → E. Should be done.

This will be described in detail as follows.

If the digital video signal is divided into 1/2 lines, A, B, C, D, E, and F, A and B are one line of digital video signals, and C and D are the next one line of video signals.

Therefore, the digital video signal is input to the controller 21 in the order of A-> B-> C-> D-> E-> F. At this time, when the data A is input, the controller 21 stores A in the first memory 22. When the data C is input, the data A stored in the first memory 22 is output to the first latch unit 12, and the data C is stored in the second memory 23. Then, when the data D is input to the controller, the data D is immediately output to the second latch portion 13. As such, when data A and D are latched in the first latch unit 12 and the second latch unit 13, the data A latched in the first latch unit 12 by the clock signal of the shifter register is the level shifter 15. The data D outputted to the second latch portion 13 is latched to the third latch portion 14 again.

Subsequently, when data E is input to the controller 21, the controller 21 outputs the data C stored in the second memory 23 to the first latch unit 12, and soon after the data F is input to the controller 21. The data F is latched to the second latch portion 13 immediately.

The data C outputted to the first latch unit 12 is immediately passed to the digital / analog converter 16 through the level shifter 15 to generate a digital / analog converter output, and the data to the second latch unit 13. While F is latched, the data D has already been transmitted to the third latch portion 14, so that the analog signal is generated by the digital / analog converter 16 via the level shifter 15.

By repeating the above process, the controller divides the input image signal data into 1/2 lines and temporarily stores the data corresponding to the half lines of the first half in the first memory 22 or the second memory 23 and then stores the data. The first latch unit 12 latches the data, and the data corresponding to the second half line of the second half is immediately latched to the second latch unit 13.

The first latch unit 12 and the second latch unit 13 output data latched by the clock signal of the shifter register 11, and the first latch unit 12 is a level shifter 15 or a digital / analog. It outputs to the conversion part 16, and the 2nd latch part 13 is output to the 3rd latch part 14. As shown in FIG.

Eventually, the half line data of the first half is temporarily stored in the first memory 22 or the second memory 23 and then output, and the half line data of the second half is output to the second latch portion 13 and the third latch portion 14. Is latched twice.

In the data driving method of the liquid crystal display of the present invention driven as described above, as shown in FIG. 4, the half-line signal at the first half of each line is output through the digital / analog converter in a point-by-time method, so that the data conversion time is horizontally scanned. In the period T, the data conversion time is constant since the half line signal at the latter half of each line is latched twice and output through the digital / analog converter.

Therefore, it is related to which position (x1, x2) to make point edge time. When there are many point edge time methods, x1 becomes large and relatively x2 becomes small.

At this time, x2 should be minimal, and if x2 is too large, it will not contribute to the increase of the effective area. If too small, not only will the excess area be effective, but also the lack of time set by the last digital / analog converter at the point edge time.

Therefore, the positions of x1 and x2 should be appropriately selected.

As described above, the data driving circuit and the driving method of the liquid crystal display device of the present invention have the following effects.

As described above, conventionally, two latch portions capable of latching one line (four latch portions capable of latching 1/2 lines) are required, but in the present invention, three latch portions capable of latching 1/2 lines are required. need. Therefore, since the area occupied by the driving circuit on the liquid crystal panel is narrowed, the display area is relatively increased and the number of circuits on the panel is reduced, so that the yield of the liquid crystal panel is increased.

That is, it is true that the area occupied by the latch portion is reduced as compared with the prior art, but the first memory and the second memory are needed more than the prior art. However, since the controller and the first and second memories are not formed on the liquid crystal panel but formed on the PCB substrate, the area occupied by the driving circuit on the liquid crystal panel is reduced.

Claims (5)

A first memory and a second memory for storing a first half or a second half of one line of digital video signal data; A shift register unit for shifting and outputting a dot clock signal; A first latch unit for latching and outputting digital video signal data of the first half of one line by a clock signal output from the shift register unit; A second latch unit for latching and outputting a digital video signal of the latter half of one line by a clock signal of the shifter register unit; A third latch unit for latching and outputting a digital video signal of the second half part output from the second latch unit again; A digital / analog converter for outputting an analog video signal corresponding to the digital video signal output from the first latch unit and the third latch unit; The first half data of each line among the input digital video signal data is temporarily stored in the first memory or the second memory and output to be latched to the first latch portion, and the second half data of each line is immediately latched to the second latch portion. And a controller for controlling the data driving circuit of the liquid crystal display device. The method of claim 1, And a level shifter for outputting a voltage corresponding to the digital video signal output from the first latch section and the third latch section to the digital / analog converter. The data driving circuit of claim 1, wherein the first half or the second half corresponds to one-half line of one line of digital image signal data. A first step of dividing the input digital video signal into half line signals so that the half line signals in the first half of each line are temporarily stored and then output, and the half line signals in the second half of each line are immediately output; A second latching of the half line signal of the first half of the temporary storage and outputting; and a half line signal of the second half of the second half so as to simultaneously output the half line signals of the first half and the second half of each line at the same time. step; And converting the digital image signal output in the second step into an analog and applying the analog image signal to a data line of the liquid crystal panel. The method of claim 4, wherein Temporarily storing the half-line signal of the first half of the 4n-3th line in the memory and outputting and latching the half-line signal of the first half of the 4n-th line before the memory from the memory; When the 1/2 line signal of the latter part of the 4n-3th line is input, it is latched, and the 1/2 line signal of the latter part of the 4nth line latched before is latched again, and the half of the first and second half of the latched 4n line is again latched. Outputting a line signal as an analog signal; If the half line signal of the first half of the 4n-2th line is input to the memory and outputting the half line signal of the 4n-3th first half to the memory and latching it; As soon as the 1/2 line signal of the 4n-2 second half is inputted, it is immediately latched and the latched 1/2 line signal of the latter part of the 4n-3 second line latched again is latched again, and the first half and the second line of the latched 4n-3 line Outputting a 1/2 line signal from the memory as an analog signal; If the half line signal of the first half of the 4n-1th line is input to the memory, the half line signal of the first half of the 4n-2th line is output from the memory and latched; As soon as the 1/2 line signal of the latter part of the 4n-1th line is input, it is immediately latched, and at the same time, the 1/2 line signal of the latter part of the 4n-2th line latched again is latched again. Outputting the signal and the half-line signal of the fourth half of the 4n-2 th as an analog signal; Storing the half line signal of the first half of the 4n-th line and outputting and latching the half line signal of the first half of the 4n-1th line; As soon as the 1/2 line signal of the latter part of the 4n-th line is input, it is immediately latched, and the latched half-line signal of the latter part of the 4n-1th line which is latched at the same time is again latched. A method of driving data of a liquid crystal display device comprising repeating the step of outputting a 1/2 line signal of the fourth half of the 4n-1th half as an analog signal.