KR19980067996U - Monitor power supply - Google Patents

Abstract

The present invention relates to the power supply of the monitor in the power system of the monitor, so that the auxiliary power supplied in the DPMS mode does not exceed the prescribed value.

The circuit of the present invention outputs a first power supply voltage and a second power supply voltage in a normal mode to supply a first normal power supply V1, a second normal power supply V2, and an auxiliary power supply V3, and a DPMS mode. When the first power supply voltage and the second power supply voltage are reduced, the supply of the first normal power supply V1 and the second normal power supply V2 is stopped, and the reduced first power supply voltage receives the off / suspend signal and receives the auxiliary power supply unit ( In the power supply of the monitor for supplying the auxiliary power (V3) through 40, the second power supply voltage is supplied in the normal mode to supply the auxiliary power (V3), and in the DPMS mode from the auxiliary power supply (40) It is composed of an auxiliary power supply limiting unit 50 which receives the reduced first power supply voltage and limits it to a predetermined rated voltage to supply the auxiliary power supply V3, so that the rated voltage is applied to the zener diode ZD even if the auxiliary power supply exceeds the specified value. Stable auxiliary power supply (V3) It can provide.

Description

Monitor power supply

The present invention relates to a power supply system of the monitor, and more particularly, to a power supply device so that the auxiliary power does not exceed the prescribed value when supplying the necessary power using the auxiliary power supply is stopped in the DPMS mode.

In general, Display Power Management Signaling (DPMS) is a type of office equipment that is regulated by the Video Electronics Standards Association (VESA), a video equipment standardization organization, to save energy by reducing the waste of power consumed in the most widely used monitors. A power control related technology.

In the DPMS, as shown in Table 1, four states are defined according to the state of APM (Advanced Power Management) operated in the computer main body, and horizontal and vertical synchronization signals are used to identify them. Here, APM is a computer power management process defined by Microsoft and IBM.

TABLE 1

condition signal Required Power saving degree Normal recovery time Horizontal synchronization Vertical synchronization video On has exist has exist Normal input compulsion Saving - Standby none has exist Blanking option small short Suspend has exist none Blanking compulsion versus Kim off none none Blanking compulsion maximum -

As shown in Table 1, the state (or mode) in the DPMS is on (on), standby (stand-by), suspend (suspend), off (off), at least on (on), suspend Suspend and off states must be accepted.

In the on state (mode), there are both a horizontal synchronous signal and a vertical synchronous signal input from the computer through the D-sub, and the video signal is normally input and displayed on the screen. In standby mode (mode), there is no horizontal synchronous signal input from the computer through D-sub, only vertical synchronous signal, and the video signal is blanked so that nothing is displayed on the screen. This is a state of saving. In the suspend state (mode), there is a horizontal synchronous signal input from the computer through the D-sub, no vertical synchronous signal, and the video signal is blanked so that nothing is displayed on the screen. It is a state of saving. The off state (mode) is a state in which the power is off, there is no vertical and horizontal synchronization signal, the video signal is blanked, and the power is maximized.

In this way, the state of the DPMS is determined according to the synchronization signal input from the computer, and power can be saved by turning off or on the power of the corresponding part according to each state.

The power supply circuit of the monitor receives commercial AC power according to the above mode and supplies various power required for the monitor.In the normal mode, the power supply is normally supplied. In the DPMS mode, the normal power supply is stopped and the auxiliary power is supplied. To supply power.

Referring to FIG. 1, a DC power supply unit (not shown) on the primary side of the transformer 10 receives a commercial AC power source and converts it into direct current to apply a DC voltage to the primary side of the transformer 10. When the AC voltage is induced to the secondary side of the transformer 10 by the switching operation of the primary side of the transformer 10, the rectifying diodes D1 and D2 and the smoothing capacitors C1 and C2 of the output unit 20 are converted into DC voltages. It is converted and supplied to each circuit of the monitor to operate the circuit.

The first power supply voltage generated through the above process is a high voltage of about 100V and is used as the first normal power supply V1, and the second power supply voltage is about 12V and passes through the regulator 30. After the stable 12V voltage is used as a normal power supply (V2). In addition, the voltage passing through the regulator 30 is also used as the auxiliary power supply V3 via the diode D3.

Looking at the power supply according to the mode, first, in the normal mode, the first power supply voltage is supplied to the first normal power supply V1, and the second power supply voltage is supplied to the second normal power supply V2 and the auxiliary power supply through the regulator 30. Supplied to V3.

Then, when the microcomputer (not shown) outputs the off / suspend signal to the auxiliary power supply 40 during the conversion to the DPMS mode, the first power supply voltage and the second power supply voltage are reduced to about 1 / 8th and are required for the normal power supply (V1, V2). Not supplying the rated power, only the auxiliary power supply (V3) to supply power through the auxiliary power supply (40).

However, conventionally, in the DPMS mode, the transistors of the auxiliary power supply are turned on before the first power supply voltage is reduced to about 1/8 so that a voltage higher than a predetermined value is transferred to the auxiliary power.

The present invention has been made to solve the above problems, the power supply for always delivering a fixed rated voltage to the auxiliary power supply even if the transistor is turned on before the first power supply voltage is down to 1/8 in DPMS mode The purpose is to provide.

The apparatus of the present invention for achieving the above object, in the normal mode outputs the first power supply voltage and the second power supply voltage to supply all of the first normal power supply, the second normal power supply and the auxiliary power supply, in the DPMS mode A monitor for stopping supply of the first normal power supply and the second normal power supply by reducing the first power supply voltage and the second power supply voltage, and supplying the auxiliary power through the auxiliary power supply by receiving an off / suspend signal from the reduced first power supply voltage. In the power supply of the power supply, the auxiliary power is supplied by receiving the second power supply voltage in the normal mode, and the auxiliary power is supplied by limiting to the predetermined rated voltage by receiving the reduced first power voltage from the auxiliary power supply in the DPMS mode. It is characterized by consisting of a secondary power supply limiting unit.

1 is a circuit diagram showing a part for supplying various power in the monitor,

2 is a circuit diagram showing a power supply of the monitor according to the present invention.

＊ Explanation of symbols for main parts of drawing

10: transformer 20: output unit

30: regulator 40: auxiliary power supply

50: auxiliary power limiter D1, D2, D3: diode

ZD: Zener Diodes Q1, Q2, Q3, Q4: Transistor

R1, R2, R3, R4, R5, R6, R7: Resistor C1, C2, C3: Capacitor

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram showing a power supply of the monitor according to the present invention.

As shown in FIG. 2, the auxiliary power stabilization circuit according to the present invention includes a transformer 10, an output unit 20, a regulator 30, an auxiliary power supply unit 40, and an auxiliary power limiting unit 50. It is.

In addition, the auxiliary power supply 40 has a bias resistor (R1 ~ R6), the NPN type first transistor (Q1) is connected to the base terminal, the base terminal is connected to the collector terminal of the first transistor (Q1) When the first transistor Q1 is turned on, 'low' is applied to turn on the PNP type second transistor Q2, and the base terminal is connected to the collector terminal of the second transistor Q2. When (Q2) is turned on, 'high' is applied to the NPN type third transistor (Q3) is turned on, the auxiliary power supply limiting unit 50 is a resistor (R7), capacitor (C3), Zener diode (ZD) ) And a fourth transistor Q4.

First, when the microcomputer (not shown) outputs a 'low' level off / suspend signal to the auxiliary power supply 40 in the normal mode, the NPN type first transistor Q1 of the auxiliary power supply 40 is turned off. As a result, the PNP type second transistor Q2 is turned off, and as the second transistor Q2 is turned off, the NPN type third transistor Q3 is turned off.

Since the transistors Q1, Q2, and Q3 are turned off, the first power supply voltage output by the output unit 20 does not supply power to the auxiliary power supply V3, but only about 100 V is supplied to the first normal power supply V1. To supply. The second power supply voltage supplies the second normal power supply V2 of 12V through the regulator 30, and the 12V voltage passing through the regulator 30 is transmitted to the auxiliary power supply limiter 50 through the forward diode D3. .

The 12V voltage is a cathode terminal of the Zener diode ZD having a base terminal of the NPN type fourth transistor Q4 and a predetermined zener voltage (eg, 12V) through the resistor R7 of the auxiliary power supply limiting unit 50. Is connected in parallel. At this time, the capacitor (C3) is connected in parallel with the zener diode (ZD) at the base end to remove noise during switching and to supply a stable power. The 12V voltage is applied to the base terminal of the fourth transistor Q4 through the start resistor R7. As a result, the fourth transistor Q4 is turned on so that a voltage of about 12 V is transferred to the auxiliary power source V3.

On the other hand, when switching to the DPMS mode, the first power supply voltage and the second power supply voltage decrease by about 1/8, so that the rated voltage is not transmitted to the normal power supplies V1 and V2. Output as' Thus, 'high' is applied to the base terminal of the first transistor Q1 so that the first transistor Q1 is turned on. Accordingly, 'low' is applied to the base terminal of the second transistor Q2 to turn on the second transistor Q2, and as the second transistor Q2 is turned on, to 'base' of the third transistor Q3. High 'is applied to turn on the third transistor Q3.

Accordingly, the first power supply voltage reduced by about 1/8 flows through the turned-on third transistor Q3. At this time, the diode D3 in the reverse direction is cut off so that power is not supplied to the second normal power supply V2, and only about 12V of power is supplied to the auxiliary power supply V3 through the auxiliary power supply limiter 50.

If the transistors Q1, Q2, and Q3 are turned on before the first power supply voltage decreases by about 1/8, a predetermined voltage (for example, 20V) exceeding 12V is applied to the A point. The resistor R7 is connected in parallel to the cathode terminal of the zener diode ZD and the base terminal of the fourth transistor Q4. Since the voltage of 20V is greater than the zener voltage of 12V, the zener diode ZD is turned on and 12V is applied to the base terminal of the fourth transistor Q4 so that the fourth transistor Q4 is turned on. About 12V of power is transferred to the power supply V3.

As described above, the device of the present invention interrupts the normal power in the DPMS mode of the monitor and supplies the auxiliary power to limit the rated voltage to a zener diode having a predetermined zener voltage when the auxiliary power exceeds a specified value. By providing a stable auxiliary power is effective.

Claims (2)

In the normal mode, the first power voltage and the second power voltage are output to supply all of the first normal power supply V1, the second normal power supply V2, and the auxiliary power supply V3. The second power supply voltage is reduced to stop the supply of the first normal power supply V1 and the second normal power supply V2, and the reduced first power supply voltage receives the off / suspend signal and receives the auxiliary power supply through the auxiliary power supply unit 40. In the power supply of the monitor for supplying (V3), In the normal mode, the second power supply voltage is supplied to supply the auxiliary power supply V3, and in the DPMS mode, the auxiliary power supply V3 is limited to the predetermined rated voltage by receiving the reduced first power supply voltage from the auxiliary power supply unit 40. Power supply of the monitor consisting of a secondary power limiting unit for supplying 50. The NPN type fourth transistor (Q4) of claim 1, wherein the auxiliary power supply limiting unit (50) is applied with a first power supply voltage reduced through the resistor (R7) between the collector terminal and the base terminal and a capacitor (C3) is connected to the collector terminal. ); And And a Zener diode (ZD) connected in parallel with the capacitor (C3) and having a base end of the NPN type fourth transistor (Q4) connected to the cathode end.