KR19980064530U - Clock generator for OSD of TV - Google Patents

Abstract

The present invention corrects the frequency and phase deviation of the clock signal output from the RC oscillator circuit 100 according to the deviation signal of the RC oscillation circuit 100 and the phase synchronization loop circuit 103 for generating a clock signal of a predetermined frequency. Compares the phase of the clock generator 101 outputting the OSD clock with the OSD clock generated by the clock generator 101 with the phase of the horizontal synchronization signal multiplied at an arbitrary frequency, and extracts the phase difference. A phase synchronization loop circuit 103 which provides a phase difference value to the clock generator 101 as a deviation signal, and generates a clock signal of a predetermined frequency to compensate for the clock signal frequency and phase, thereby adjusting the phase of the OSD clock. Phase difference is extracted by comparing the phase of the horizontal synchronization signal multiplied by an arbitrary frequency with a predetermined frequency, and the frequency and phase deviation of the clock signal are corrected according to the extracted phase difference value and output to the OSD clock. Is one characterized in that it performs a row.

Description

Clock generator for OSD of TV

The present invention compares the phase of the horizontal synchronization signal, which is one of the television signals, with the feedback of the OSD clock, and compensates the OSD clock generated by the phase difference, thereby generating the OSD clock for the television to synchronize the OSD clock with the horizontal synchronization signal. It is intended to provide a device.

A typical television receives and demodulates a broadcast signal transmitted from a broadcasting station and outputs the demodulated signal as a video signal and an audio signal through a CRT and a speaker. Such a general TV requires an OSD clock that provides an operation timing such as an on-screen display microcomputer, and the configuration and functions of a general TV having a function of generating an OSD clock as described above are shown in FIG. 1. Looking at it as follows.

In Fig. 1, reference numeral 1 denotes an antenna, 2 denotes an RF amplifying unit for amplifying a radio frequency (hereinafter referred to as RF) signal received through the antenna 1, and 3 denotes the RF amplifying unit ( A first mixer for mixing the radio frequency signal output from 2) and the oscillation frequency signal output from the local oscillation circuit 17 to be described later and outputting an intermediate frequency signal (hereinafter referred to as IF) is shown.

Further, reference numeral 4 denotes an IF amplifier section for amplifying the intermediate frequency signal output from the first mixer 3, and 5 denotes an image intermediate frequency signal PIF in the intermediate frequency signal output from the IF amplifier section 4. And a P / S separator for separating the voice intermediate frequency signal SIF, and 6 represents a voice detector for detecting a voice signal from the voice intermediate frequency signal SIF output from the P / S separator 5. 7 denotes an image detector for detecting an image signal from an image intermediate frequency signal PIF output from the P / S separator 5.

In addition, reference numeral 8 denotes a remote control device that allows a viewer to select a desired channel or to select each mode of the television, that is, a TV / AV mode, and 9 denotes an infrared signal from the remote control device 8. 10 shows a receiver for converting a conventional code signal, 10 denotes a channel memory in which predetermined channel data is stored, and 11 denotes a microprocessor which controls the entire system in accordance with an input signal from the remote controller device 8.

In addition, reference numeral 12 denotes a screen display for overlapping and outputting a character or a picture on a screen on which a broadcast signal is output separately from the broadcast signal according to the control signal of the microprocessor 11 (On Screen Display). (Hereinafter referred to as OSD), and 13 denotes a PWM generator which generates a predetermined pulse width modulation (PWM) signal according to a control signal from the microprocessor 11, and 14 denotes the above. An integration circuit for integrating the PWM signal output from the PWM generator 13 to generate a predetermined level signal is shown.

In this case, when the viewer selects a predetermined channel using the remote controller device 8, the microprocessor 11 reads out channel data corresponding to the channel selected by the viewer from the channel memory 10 and then based on the selected channel. By controlling the PWM generator 13 to generate a predetermined PWM signal, the PWM signal is output as a voltage control signal corresponding to the channel selected by the viewer through the integrator circuit 14.

In addition, reference numeral 15 is provided for a precise tuning operation, and represents an Auto Fine Tunning circuit (hereinafter referred to as AFT) circuit 15, and 16 represents a voltage signal applied from the integrating circuit 14; An adder for adding a voltage signal applied from the AFT circuit 15 is shown, and 17 represents a local oscillating circuit for outputting a predetermined oscillation frequency.

In addition, reference numeral 18 controls the amplification degree of the above-described RF amplifier 102 and the IF amplifier 4 on the basis of the level of the image signal detected by the image detector 7, the image detector ( Figure 7 shows the Automatic Gain Control (AGC) circuit that controls the video signal output level from 7).

On the other hand, reference numeral 19 denotes an external AV device such as a VCR or a laser disc player, and 20 denotes the voice detector 6 and the image detector 7 according to the switching signal from the microprocessor 11 described above. A first switching section for selectively outputting audio and video signals from and external audio and video signals from the external AV device 19 is shown.

Although reference numeral 23 is not shown for the image signal output from the first switching unit 20, the color, tint, and brightness are in accordance with the control signal from the microprocessor 11. A video processing unit which processes (Brightness) and the like and outputs R (Red), G (Green), and B (Blue) signals corresponding to the video signal.

The RGB signal output from the image processor 23 is output by mixing RGB and OSD blanking signals Y ′, which are output signals of the OSD generator 12 described above, in the second mixer indicated by reference numeral 24. Reference numeral 25 denotes a CRT driving unit for driving the CRT based on the RGB signal output from the mixer 24.

In addition, reference numeral 21 denotes a base, treble, and volume according to a control signal from the microprocessor 11 although not shown for the voice signal output from the first switching unit 20. A voice processing unit for executing voice processing such as a volume), and 22 denotes a voice amplifying unit for amplifying and outputting the voice signal processed by the voice processing unit 21 to a speaker.

In the general TV configured as described above, when the viewer selects the TV / AV mode by using the remote controller 8, the microprocessor 11 controls the switching unit 20 to control the voice detector 6. And by selectively outputting the video and audio signals from the video detector 7 or the video and audio signals from the external AV device 19 to the video processor 23 and the audio processor 21. Can watch the video and audio through the CRT and speakers of the TV.

In the TV operating as described above, a clock generator for an OSD that provides an operation clock of a conventional on-screen display microcomputer or a memory is as shown in FIG.

As shown in the drawing, a conventional OSD clock generator is required for an RC oscillator circuit 26 for generating a clock signal of a predetermined frequency and an on-screen display microcomputer for shaping a clock generated by the RC oscillator circuit 26. It consists of a clock generator 27 to output to the clock for the OSD, when the power supply to the system to generate a clock by oscillating in a predetermined period in the RC oscillator circuit 26, the clock generator 27 The generated clock is shaped and output to the clock for the OSD.

The output clock for the OSD is provided as an operation timing to the microcomputer for the on-screen display.

However, the conventional OSD clock generator as described above generates oscillation signals only by a set period without generating synchronization with the horizontal synchronizing signal or the vertical synchronizing signal, which is a television signal, and thus generates the OSD clock. The display of the (OSD video signal) caused a problem that the display of the correct video signal was impossible.

Therefore, the present invention is proposed to solve the above problems of the conventional OSD clock generator, and an object of the present invention is to compare the phase of the horizontal synchronization signal, which is one of the television signals, with the feedback of the OSD clock, and as much as the phase difference. The present invention provides an OSD clock generator for a television that compensates for the generated OSD clock and synchronizes the OSD clock with a horizontal synchronizing signal.

1 is a block diagram of a general television system

2 is a block diagram of a conventional clock generator for the OSD

3 is a block diagram of the clock generator for the OSD of the television to which the present invention is applied

Explanation of symbols for the main parts of the drawings

100: RC oscillation circuit 101: Clock generator

102: multiplier 103: phase synchronization loop circuit

Features of the present invention for achieving the above object, the RC oscillation circuit for generating a clock signal of a predetermined frequency, and the frequency and phase deviation of the clock signal output from the RC oscillator circuit in accordance with the deviation signal of the phase synchronization loop circuit A phase difference by extracting a phase difference by comparing a phase of a clock generator outputted from the clock generator with a phase of an OSD clock generated by the clock generator and a horizontal synchronization signal multiplied at an arbitrary frequency, and outputting a phase difference value to the clock generator. It consists of a phase-locked loop circuit provided by

An additional feature of the present invention for achieving the above object is to further comprise a multiplier 102 for multiplying the horizontal synchronization signal input to an arbitrary frequency to provide the phase synchronization loop circuit 103.

When a clock signal of a predetermined frequency is generated due to a feature according to the present invention for achieving the above object, a phase of a horizontal synchronization signal multiplied by an arbitrary frequency and a phase of an OSD clock whose frequency and phase of the generated clock signal are corrected The phase difference is extracted, and the frequency and phase deviation of the clock signal are corrected according to the extracted phase difference value to output the clock to the OSD.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention in detail as follows.

3 is a block diagram of a clock generator for an OSD of a television according to the present invention. As shown here, the clock is output from the RC oscillator circuit 100 according to the deviation signal of the RC oscillation circuit 100 and the phase synchronization loop circuit 103 to generate a clock signal of a predetermined frequency by oscillating at a predetermined period. A clock generator 101 for correcting the frequency and phase deviation of the signal and outputting it as an OSD clock, a multiplier 102 for multiplying a horizontal synchronization signal at an arbitrary frequency, and an OSD generated by the clock generator 101 A phase synchronization loop circuit 103 which compares the phase of the clock and the phase of the multiplied horizontal synchronization signal obtained by the multiplier 102 to extract a phase difference and provide the phase difference value to the clock generator 101 as a deviation signal. It consists of.

Referring to Figure 3 attached to the operation of the clock generator for the OSD according to the present invention configured as described above in detail as follows.

As is well known, when power is supplied to the system, the RC oscillation circuit 100 oscillates at a predetermined cycle to generate a clock, and the clock generator 101 generates a phase difference value (deviation signal) obtained by the phase synchronization loop circuit 103. By correcting the frequency and phase of the clock generated by the RC oscillator circuit 100 to output an OSD clock synchronized with the horizontal synchronizing signal.

Here, when the deviation signal generation of the phase synchronization loop circuit 103 is described in more detail, the multiplier 102 multiplies (multiplies by 32 times) the input horizontal synchronization signal at an arbitrary frequency, and the phase synchronization loop circuit 103 The phase difference is extracted by comparing the phase of the multiplied horizontal synchronization signal with the phase of the clock divided by the OSD clock generated by the clock generator 101 to a predetermined level. The phase difference value thus extracted is provided to the clock generator 101 as a deviation signal so that the frequency and phase of the clock generated by the RC oscillation circuit 100 are corrected in synchronization with the horizontal synchronization signal. Becomes a clock synchronized with the horizontal synchronizing signal.

By generating the OSD clock in synchronism with the horizontal synchronizing signal, the image signal is prevented from being displayed incorrectly during the on-screen display.

As described above, the present invention generates the OSD clock in synchronization with the horizontal synchronizing signal, thereby enabling the display of a clear and accurate image at all times during the on-screen display.

Claims (2)

A clock generator for generating a clock for an OSD of a television, An RC oscillation circuit 100 for generating a clock signal of a predetermined frequency; A clock generator 101 for correcting the frequency and phase deviation of the clock signal output from the RC oscillator circuit 100 according to the deviation signal of the phase-locked loop circuit 103 and outputting it as an OSD clock; The phase difference is extracted by comparing the phase of the OSD clock generated by the clock generator 101 with the phase of a horizontal synchronization signal multiplied by an arbitrary frequency and providing the phase difference value to the clock generator 101 as a deviation signal. The clock generator for the OSD of the television, characterized in that it comprises a phase-locked loop circuit (103). The apparatus of claim 1, further comprising a multiplier (102) for multiplying an input horizontal synchronizing signal by an arbitrary frequency and providing the multiplier to the phase-locked loop circuit (103).