KR200158350Y1 - Common device of a synchronous clock - Google Patents

Abstract

The present invention relates to an apparatus for providing a synchronization clock between a microprocessor and a specific device using a synchronization clock having the same frequency. In particular, the synchronization clock generator 100 generates a synchronization signal corresponding to a frequency required for the operation of the microprocessor. And a buffer amplifier 300 for branching the clock signal generated by the synchronous clock generator 100 to amplify and output the current, and the clock signal amplified and output from the buffer amplifier 300. A switch (sw) that receives an input and delivers it to the specific device, and selectively opens a transmission path according to a control signal; And a power detecting unit 400 for detecting a power on / off state of the system and providing a control signal to the switch sw when the power is on. By eliminating the need for the synchronous clock oscillator, the complexity and inefficiency of the hardware can be solved.

Description

Synchronous Clock Common Device

The present invention relates to an apparatus for providing a synchronous clock to a microprocessor, and more particularly, to a synchronous clock sharing apparatus for allowing one clock generator to be shared among devices using the same clock frequency among a plurality of devices.

In general, devices for electronic control operate by receiving a clock signal of a specific frequency band in order to control an operation reference and an operation speed. As a representative example, a central processing unit such as a microprocessor operates to control a system. The synchronous clock for the constant control operation is input even in the case of a standby state or a standby state, and a reserve power supply (for example, a battery) is supplied when the power is turned off.

Referring to the attached system of FIG. 1, a system employing a central processing unit such as a microprocessor will be described. As a simplified block diagram of a general television broadcasting receiver, reference numeral 1 denotes an antenna and reference numeral 2 denotes an antenna (1). ) Denotes an RF amplifying unit for amplifying a radio frequency signal (hereinafter referred to as RF), and reference numeral 3 denotes a radio frequency signal output from the RF amplifying unit 2 and a local oscillation circuit to be described later. The first mixer outputs an intermediate frequency (IF) signal by mixing the oscillation frequency signals outputted from (17).

Further, reference numeral 4 denotes an IF amplifier section for amplifying the intermediate frequency signal output from the first mixer 3, and 5 denotes an image intermediate frequency signal PIF in the intermediate frequency signal output from the IF amplifier section 4. And a P / S separator for separating the voice intermediate frequency signal SIF, and 6 represents a voice detector for detecting a voice signal from the voice intermediate frequency signal SIF output from the P / S separator 5. 7 denotes an image detector for detecting an image signal from an image intermediate frequency signal PIF output from the P / S separator 5.

In addition, reference numeral 8 denotes a remote control device that allows a viewer to select a desired channel or to select each mode of the television, that is, a TV / AV mode, and 9 denotes an infrared signal from the remote control device 8. 10 shows a receiver for converting a conventional code signal, 10 denotes a channel memory in which predetermined channel data is stored, and 11 denotes a microprocessor which controls the entire system in accordance with an input signal from the remote controller device 8.

In addition, reference numeral 12 denotes a screen display for outputting a character or a picture and the like on the screen on which the broadcast signal is output separately from the broadcast signal according to the control signal of the microprocessor 11 (On Screen Display: Hereafter referred to as OSD.) 13 represents a PWM generator for generating a predetermined pulse width modulation (PWM) signal according to the control signal from the microprocessor 11, 14 is the PWM An integration circuit for generating a predetermined level signal by integrating the PWM signal output from the generator 13 is shown.

Here, when the viewer selects a predetermined channel by using the remote controller device 8, the microprocessor 11 reads out channel data corresponding to the channel selected by the viewer from the channel memory 10 and then based on the selected channel. By controlling the PWM generator 13 to generate a predetermined PWM signal, the PWM signal is output as a voltage control signal corresponding to the channel selected by the viewer through the integrator circuit 14.

Further, reference numeral 15 denotes an auto fine tuning (AFT) circuit 15 as provided for a precise tuning operation, and 16 denotes a voltage signal applied from the integration circuit 14. An adder for adding a voltage signal applied from the AFT circuit 15 is shown, and 17 represents a local oscillation circuit for outputting a predetermined oscillation frequency.

In addition, reference numeral 18 controls the amplification degree of the above-described RF amplifier 102 and the IF amplifier 4 on the basis of the level of the image signal detected by the image detector 7, the image detector ( The following shows an automatic gain control circuit (AGC) that controls the video signal output level from 7).

On the other hand, reference numeral 19 denotes an external AV device such as a VCR or a laser disc player, and 20 denotes the voice detector 6 and the image detector 7 according to the switching signal from the microprocessor 11 described above. A switching unit for selectively outputting audio and video signals from and external audio and video signals from the external AV device 19 is shown.

Although reference numeral 23 is not shown with respect to the image signal output from the switching unit 20, the color, tint, and brightness according to the control signal from the microprocessor 11 is used. ), And outputs R (Red), G (Green), and B (Blue) signals corresponding to the video signal.

The RGB signal output from the image processor 23 is mixed with the RGB and OSD blanking signals y ', which are the output signals of the OSD generator 12 described above, in a mixer indicated by reference numeral 24, and is output by the reference numeral 25. Denotes a CRT driver for driving the CRT based on the RGB signal output from the mixer 24.

In addition, although not shown for the voice signal output from the switching unit 20, reference numeral 21 according to the control signal from the microprocessor 11 Base, Treble, Volume And a voice processing unit for executing voice processing such as the above, and 22 denotes a voice amplifier which amplifies the voice signal processed by the voice processing unit 21 and outputs it to the speaker.

In a general TV structured as such, reference numerals 2 to 4 and reference numerals 13 to 18, which are components for TV broadcast channel selection, are often referred to as AFC blocks in a broad sense, and the clock frequency used in these AFC blocks is micro. It is the same clock frequency used by the processor.

However, in spite of using the same frequency, a problem arises in that the complexity and inefficiency of the hardware are caused by using separate frequency oscillators.

An object of the present invention for solving the above problems is to provide a synchronization clock sharing apparatus that can share a clock generator between devices using the same clock frequency among a plurality of devices.

1 is a block diagram illustrating a general television receiver.

2 is a diagram illustrating a relationship between a synchronization clock sharing device and a peripheral device according to the present invention.

A feature of the present invention for achieving the above object is a device for providing a synchronization clock between a microprocessor and a specific device using a synchronization clock of the same frequency, the synchronization signal corresponding to the frequency required for the operation of the microprocessor A synchronous clock generator for generating a signal, a buffer amplifier for branching the clock signal generated by the synchronous clock generator, and amplifying and outputting the current; and a clock signal amplified and output from the buffer amplifier; And a switch for delivering to a specific device and selectively opening a transmission path according to a control signal, and a power detector for detecting a power on / off state of the system and providing a control signal to the switch if the power is on.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is an exemplary diagram illustrating a relationship between a synchronous clock sharing device and a peripheral device according to the present invention, and a configuration of an apparatus for sharing a synchronous clock between an AFC block 500 using a synchronous clock of the same frequency as the microprocessor 200. to be.

Looking at the configuration, the synchronization clock generator 100 for generating a synchronization signal corresponding to the frequency required for the operation of the microprocessor 200 and the clock signal generated by the synchronization clock generator 100 receives a branch input A buffer type amplifier 300 for amplifying and outputting a current and a clock signal amplified by the buffer type amplifier 300 are received and delivered to the AFC block 500, and the transmission path is selectively selected according to a control signal. The switch SW to open and the power detection unit 400 for detecting a power on / off state of the television to provide a control signal to the switch (SW) when the power is on.

Looking at the operation of the synchronization clock commonizing apparatus according to the present invention configured as described above, in the synchronization clock generator 100 for generating a synchronization signal corresponding to the frequency 507 kHz required for the normal operation of the microprocessor 200 is The clock signal is provided to the synchronization clock supply terminal of the microprocessor 200.

In addition, the clock signal generated by the synchronous clock generator 100 is branched and provided to the buffered amplifier 300. The buffered amplifier 300 is a clock generated by the synchronous clock generator 100. It receives the signal and amplifies and outputs the current.

At this time, if it is determined that the power of the television is turned on, the power detector 400 provides a control signal of a high state to the switch SW. Accordingly, the switch SW is switched on to receive a clock signal amplified by the buffer amplifier 300 and transferred to the AFC block 500.

Accordingly, the AFC block 500 operates normally by sharing the clock signal generated by the sync clock generator 100 with the microprocessor 200.

On the other hand, when the power detection unit 400 determines that a system such as a television is turned off, the control signal in the high state is switched to the low state, so that the switch SW is switched off and the buffer type accordingly. The clock signal amplified by the amplifier 300 is not transmitted to the AFC block 500 side, thereby reducing the load by the unnecessary AFC block 500 when the power is turned off.

In the present invention, the synchronous clock sharing apparatus according to the present invention has been described with reference to the television, but it can be seen that the present invention can be applied to any system having a specific device using a microprocessor and using the same clock as the microprocessor.

Providing the synchronous clock sharing apparatus according to the present invention that operates as described above, it is possible to solve the problem of having the complexity and inefficiency of the hardware by eliminating the unnecessary oscillation unit of the same configuration.

Claims (1)

An apparatus for providing a synchronization clock for use in specific devices using a synchronization clock of the same frequency as the microprocessor 200 embedded in the system, the synchronization corresponding to the frequency required for the operation of the microprocessor 200 A synchronization clock generator 100 generating a signal; A buffer type amplifying unit 300 which receives the clock signal generated by the synchronous clock generating unit 100 and amplifies and outputs the current; A switch (SW) for receiving a clock signal amplified and output from the buffer type amplifier 300 and transferring the clock signal to the specific devices, but selectively opening a transmission path according to a control signal; And a power detection unit (400) for detecting a power on / off state of the system and providing a control signal to the switch (SW) when the power is on.