KR19980060657A - Processing unit for MPEG-2 audio encoder - Google Patents

Abstract

The present invention relates to the design of arithmetic processing unit (ALU), which is the core of designing a dedicated DSP core for implementing an MPEG-II audio encoder as an ASIC. Unlike the general arithmetic processing unit, the arithmetic processing unit of the present invention is capable of fast arithmetic processing in real time to be applied to an MPEG-II audio encoder, and all numbers are represented in two's complement form. In addition, logarithmic and exponential calculations are possible, and calculations are performed in one cycle by putting a separate module for these calculations. The structure of the calculation processing apparatus according to the present invention comprises an independent exponential log calculation processing unit for logarithmic and exponential calculation; It includes MIN, MAX operation processing unit for finding the maximum value and the minimum value of the absolute value.

Description

Processing unit for MPEG-2 audio encoder

MPEG-II is a compression algorithm used in next-generation digital video media such as HDTV and DVD. It includes coding of images and audio. The present invention relates to the implementation of a speech compression algorithm among the construction of this compression algorithm. A device based on a conventional general-purpose digital signal processor (DSP) has difficulty in real-time implementation because it is not suitable for the algorithm of MPEG-II.

The present invention is directed to a structure of an arithmetic processing unit suitable for such a dedicated DSP for MPEG-II audio encoding. More specifically, the present invention proposes a structure capable of performing arithmetic logic at high speed to support MPEG-II audio coding supporting multiple channels in real time using a single DSP core.

The MPEG-II audio coding process consists of an analysis filter, a psychoacoustic model including a 1024-point fast fourier transform (FFT), bit assignment, quantization, multichannel processing, and bit sequence formation. Since all of these processes need to be applied to the channel, it is difficult to implement a real time due to a large amount of computation.

1 is an overall configuration diagram of an arithmetic processing apparatus to which the present invention is applied.

* Description of the symbols for the main parts of the drawings *

1: ALU2: Multiplier

3: exponential calculation unit 4: logarithmic operation unit

5: Accumulation register 6: Multiplication register

7: Shifter 8: Output Multiplexer

9: adder

Multiplexer: 21, 22, 23, 24, 25, 26, 27, 28, 29, 30

The structure of the calculation processing apparatus according to the present invention for achieving the above object is an independent exponential log calculation processing unit (2, 3, 4, 6, 28, 29, 30) for logarithmic and exponential operation; And MIN and MAX arithmetic processing units 1, 5, 7, 26, and 27 for finding the maximum and minimum values of absolute values.

In addition, the MIN, MAX arithmetic processing unit ALU (1) for performing arithmetic logic operations in general; An accumulation register 5 connected to the output of the ALU; A multiplexer 27 for selecting an input from a memory, a register, or a multiplier output and supplying the input to the ALU; And a multiplexer 26 which selects the feedback input from the register or accumulator register 5 and supplies it to the ALU.

In addition, the exponent, log operation processing unit and a multiplier (2) for multiplying the input from the memory or register; An exponential operator (3) for exponentially calculating the output of the multiplier; A first multiplexer 28 for selecting among a memory, an exponential operation output, and an accumulation register output; A multiplication register (6) for storing the output of said first multiplexer (28); A second multiplexer (30) for outputting the output of the multiplication register (6) to a 32-bit memory; A third multiplexer (29) for selecting the output of the multiplication register (6), the output of the accumulate register, and data from a 32-bit memory; And a logarithm calculation unit 4 for logarithmically calculating the output of the third multiplexer.

Unlike the general arithmetic processing apparatus, the arithmetic processing unit (ALU: Arithmetic and Logic Unit) of the present invention is capable of fast arithmetic processing in real time to apply to an MPEG-II audio encoder. Negative numbers can be represented in complementary form. In addition, log and exponential operations are possible, and the log operation used here is a 32-bit operation for 96 dB precision. Since exponential operation needs to log operation again next time, it outputs 32 bit result by inputting 16 bit.

The following is the basic operation that must be performed by the processing unit through the process of analysis filtering and fast fourier transform (FFT) signal to become MPEG-II audio bit stream, and important operations required in each process. Take a look.

Procedure 1. The scale factor is calculated for 12 subband signals calculated from the analysis filter.

→ table search operation to find the maximum and minimum values

Process 2. Scale factor select information is performed on the three scale elements of each subband.

→ comparison of two values

Step 3. Normalize the subband samples using the scale factor.

→ division

Step 4. Obtain a signal to mask ratio (SMR) using a psycho-acoustic model.

Course 4-1. Decibel values are calculated for the 512 samples that result from the FFT calculation.

→ log operation

Course 4-2. Calculate Sound Pressure Level.

→ multiply and accumulation

Course 4-3. Find the Tonal component.

→ comparison of two values

Course 4-4. Find the Nontonal component.

→ Accumulation operation, log operation

Course 4-5. Decimation operation is performed on pure sound components.

→ addition and subtraction

Course 4-6. Get the Global Masking Threshold.

→ logarithmic, exponential

Course 4-7. Find the Minimum Masking Threshold.

→ minimum value search

Course 4-8. Obtain the signal-to-mask ratio (SMR).

→ subtraction

Step 5. Assign bits using the signal-to-mask ratio value.

→ comparison operation and subtraction

Course 6. Normalization

→ multiplication, addition

Process 7. Bit Packing

To sum up the operations that DSP Core must perform, add, subtract, multiply, divide, multiply and accumulate, accumulate, log, exponential, compare, and find the maximum and minimum values. , Table search, etc. Here, addition, subtraction, and multiplication, which are operations that can be easily implemented in ASIC, are basically provided, and they should be used to determine whether to perform the remaining operations or to place each module, and to implement the MPEG-II algorithm. Specific operations processed by the device are as follows.

1. Division is used only in the normalization process. In the normalization process, division is not a division for all numbers but a division into a scale factor having a finite number of cases. Therefore, the reciprocal of this can be solved simply by obtaining it in advance and storing it in ROM and multiplying it.

2. An accumulator can be easily implemented by placing one adder, specifying one register, connecting its output value to the adder, and using the register's input value as the adder's output.

3. MAC can also be easily implemented by placing the multiplier on top and using its output as the input of the accumulator.

4. The comparison operation is to subtract, but without storing the result again, examine the value of the result to determine which one is large.

5. Subtract the operation that finds the maximum value (minimum value), but select the larger value (or the smaller value) and store the value.

6. There are logarithmic and exponential operations, but there are many ways to implement them. However, many times are used to implement the MPEG audio coder to determine the success or failure of real-time processing. Therefore, their operation should be the first priority to use as few cycles as possible. Here we have a separate module for these operations. Thus, the calculation is done in one cycle. This makes all of the above possible in real time.

7. The table search operation causes separate address generation units to execute in parallel.

8. For the calculation of the scale factor, the maximum and minimum values must be derived and the absolute value taken. Therefore, the operation to find the absolute value is required.

9. Various logic operations are required for generation and reading of control words for controlling the analysis filter and the FFT unit.

Considering the above, the command set as shown in Table 1 is composed. In Table 1, AND, OR, XOR, and NOT are simple logical operations, and ADD, SUB, and MULT are simple arithmetic operations. The ABS instruction connects to the adder if the operand sign is '0' by 'pass' and if '1' is not, it is connected to the adder and the other input of the adder is set to '1'. Seek pay. Since MIN and MAX are used to find the scale factor, the absolute value must be compared to derive the maximum (or minimum) value. To do this, you can take the absolute value of each of the two values you want to compare, and then update them with a large value (small value) that you compare using the Compare command. However, this implementation requires at least four instructions, which can take considerable time to find the scale factor. Since the real-time implementation is the biggest objective, the following method is used to perform it in a single instruction, that is, one cycle. Here, the case where the maximum value is obtained will be described. For the case where the minimum value is obtained, each operation may be reversed.

Table 1. Commands

① If the sign bit of the X operand is '0', that is positive and the sign bit of the Y operand is also '0', that is, positive: Subtract two values and examine the sign of the result. If the sign bit is '1' or negative, X is updated to Y.

If the sign bit of the X operand is '0', that is positive and the sign bit of the Y operand is '1', that is, negative: If the sign is '0', i.e. positive, add the two values and examine the sign of the result Is maintained and X is updated to Y if the sign bit is '1'.

③ If the sign bit of the X operand is '1', that is negative, and the sign bit of the Y operand is '0', that is, positive: Add two values and examine the sign of the result. If the sign is '0', that is, positive, Update to Y and keep X if sign bit is '1'.

④ If the sign bit of the X operand is '1', that is negative and the sign bit of the Y operand is also '1', that is, negative: If the sign is '0', ie positive, after subtracting the two values and examining the sign of the result Is updated to Y and X is maintained if the sign bit is '1'.

This operation leaves a large value in X. If you do this for all the values you want to compare and run ABS last, the maximum absolute value is stored in X. That is, if the sign of X and the sign of Y are different, a control signal is made to perform subtraction. If the sign of X and the sign of the result are the same, X is maintained, otherwise it is updated to Y. In the case of the MIN instruction, the sign of X and the sign of the result are the same and MAX or the sign of X and the sign of the result are different. If the sign is MIN, X is maintained. Otherwise, it is updated to Y.

Figure 1 shows an embodiment implemented by applying this. ALU (1) is an arithmetic unit for logical operation, addition, subtraction, absolute value, maximum, minimum value operation, and multiplier (2), exponent operation unit (3), logarithm operation unit (4), MULT, MAC, LOG, PWR This is the configuration for operation. Many multiplexers select either the input data path or the output data.

MIN and MAX arithmetic processing unit ALU (1) for performing general arithmetic logic operation; An accumulation register 5 connected to the output of the ALU; A multiplexer (27) which selects an input from a memory, a register or a multiplier output and supplies it to the ALU; It consists of a multiplexer 26 which selects the feedback input from the register or accumulator register 5 and supplies it to the ALU.

In addition, the exponent, log operation processing unit and a multiplier (2) for multiplying the input from the memory or register; An exponential operator (3) for exponentially calculating the output of the multiplier; A first multiplexer 28 for selecting among a memory, an exponential operation output, and an accumulation register output; A multiplication register (6) for storing the output of said first multiplexer (28); A second multiplexer (30) for outputting the output of the multiplication register (6) to a 32-bit memory; A third multiplexer (29) for selecting the output of the multiplication register (6), the output of the accumulation register, and the data from the 32-bit memory; And a logarithm calculation unit 4 for logarithmically calculating the output of the third multiplexer.

The MAC instruction is a value in which the operation result of the multiplier 2 is 8-bit right shifted, or the result value accumulated from the ALU 1 to the accumulation register 5 via the multiplexer 27 is fed back through the multiplexer 26. And is added and stored in the accumulation register 5 again. The operation result of the exponential operator 3 is stored in the multiplication register 6 and output to the 32-bit memory through the multiplexer 30. In addition, data from the 32-bit memory is input through the multiplexer 28, stored in the multiplication register 6, calculated by the logarithm calculation unit 4 and output through the output multiplexer 8. MIN and MAX operations are implemented through the ALU 1 and the accumulator register 5 by the algorithm described above.

Unlike the general arithmetic processing unit, the present invention is a design focused on high-speed processing in order to be applied to an MPEG-II audio encoder, and real-time processing is possible, and all numbers are expressed in two's complement form. In addition, logarithmic and exponential calculations are possible, and calculations are performed in one cycle by putting a separate module for these calculations. In addition, it is possible to implement algorithms of complex encoders in real time by designing operations frequently used in MPEG-II operations such as maximum and minimum operations as one cycle instruction.

The preferred embodiments of the present invention are disclosed for the purpose of illustration, and those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and changes belong to the following claims Should be seen.

The present invention relates to an operation processing apparatus that can be said to be the core in designing a DSP core to implement an MPEG-II audio encoding apparatus as an ASIC.

It is an object of the present invention to propose an arithmetic processing unit employed in a dedicated DSP suitable for performing MPEG-II audio compression in real time.

It is also an object of the present invention to propose an arithmetic processing apparatus employed in a dedicated DSP suitable for performing MPEG-II audio compression in real time with a single dedicated DSP.

Claims (3)

An arithmetic processing apparatus employed in a dedicated DSP core for an MPEG-II audio coding apparatus; The operation processing value is: Independent exponential log calculation processing unit for logarithmic and exponential operations; And a MIN and MAX arithmetic processing unit for finding the maximum and minimum values of absolute values. The method of claim 1, The MIN and MAX operation processing unit An ALU performing general arithmetic logic; An accumulation register connected to the output of the ALU; A multiplexer that selects an input from a memory, register, or multiplier output and supplies the input to the ALU; And a multiplexer for selecting a feedback input from a register or an accumulation register and supplying the ALU to the ALU. The method of claim 1, The index and log operation processing unit A multiplier for multiplying inputs from memory or registers; An exponential operator for exponentially calculating the output of the multiplier; A first multiplexer for selecting among a memory, an exponential operation output, and an accumulation register output; A multiplication register for storing an output of the first multiplexer; A second multiplexer for outputting an output of the multiplication register to a 32-bit memory; A third multiplexer for selecting an output of the multiply register, an output of an accumulator register, and data from a 32-bit memory; And a log operation unit for log operation of the output of the third multiplexer.