KR100202309B1 - Operation process apparatus for mpeg-2 audio coder - Google Patents

Abstract

The present invention is MPEG- The present invention relates to the design of arithmetic processing unit (ALU), which is the core of designing a dedicated DSP core for implementing an audio encoder as an ASIC. Unlike general arithmetic processing unit, MPEG- In order to be applied to an audio encoder, the arithmetic processing unit of the present invention can perform real-time processing by performing a rapid arithmetic processing, and all numbers are represented in two's complement form. In addition, logarithmic and exponential calculations are possible, and a separate module is provided for these calculations. The structure of the calculation processing apparatus according to the present invention comprises an independent exponential log calculation processing unit for logarithmic and exponential calculation; It includes MIN, MAX operation processing unit for finding the maximum value and the minimum value of the absolute value.

Description

Processing unit for MPEG-2 audio encoder

MPEG- Is a compression algorithm employed in the next generation of digital video media such as HDTV and DVD, which includes coding of image and audio. The present invention relates to the implementation of a speech compression algorithm in the construction of this compression algorithm. The device based on the conventional general-purpose digital signal processor (DSP) is MPEG- There was a difficulty in real-time implementation due to inaccurate relationship with the algorithm.

The present invention is such MPEG- A structure of an arithmetic processing unit suitable for a dedicated DSP for audio encoding. More specifically, MPEG- supports multiple channels using a single DSP core. It is to propose a structure that can perform arithmetic logic operation required to support audio coding in real time at high speed.

MPEG- The audio encoding process consists of analytical filters, psychoacoustic models including a 1024-point fast fourier transform (FFT), bit assignment, quantization, multichannel processing, and bitstream formation. Since all of these processes must be applied, there is a difficulty in real-time implementation due to a large amount of computation.

1 is an overall configuration diagram of an arithmetic processing apparatus to which the present invention is applied.

* Explanation of symbols for main parts of the drawings

1: ALU 2: Multiplier

3: exponential operation unit 4: logarithmic operation unit

5: Accumulation register 6: Multiplication register

7: shifter 8: output multiplexer

9: adder

Multiplexer: 21, 22, 23, 24, 25, 26, 27, 28, 29, 30

Configuration of the processing unit according to the present invention for achieving the above object is

Independent exponential log arithmetic units 2, 3, 4, 6, 28, 29, and 30 for logarithmic and exponential operations;

And MIN and MAX arithmetic processing units 1, 5, 7, 26, and 27 for finding the maximum and minimum values of absolute values.

In addition, the MIN, MAX operation processing unit

ALU (1) for performing general arithmetic logic operations;

An accumulation register 5 connected to the output of the ALU;

A multiplexer 27 for selecting an input from a memory, a register, or a multiplier output and supplying the input to the ALU;

And a multiplexer 26 which selects the feedback input from the register or accumulator register 5 and supplies it to the ALU.

In addition, the exponent, log operation processing unit

A multiplier 2 for multiplying inputs from a memory or register;

An exponential operator (3) for exponentially calculating the output of the multiplier;

A first multiplexer 28 for selecting among a memory, an exponential operation output, and an accumulation register output; A multiplication register (6) for storing the output of said first multiplexer (28); A second multiplexer (30) for outputting the output of the multiplication register (6) to a 32-bit memory;

A third multiplexer (29) for selecting the output of the multiplication register (6), the output of the accumulate register, and data from a 32-bit memory;

And a log operation unit 4 for log operation of the output of the third multiplexer.

The present invention, unlike the general operation processing device MPEG- The Arithmetic and Logic Unit (ALU) of the present invention can be applied to an audio coder to perform real time processing by performing arithmetic processing, and all numbers can express negative numbers in a two's complement format. In addition, log and exponential operations are possible, and the log operation used here is a 32-bit operation for 96dB precision. Since exponential operation requires log operation again, 16-bit input produces 32-bit result.

Next, the signal filtered by Analysis Filtering and Fast Fourier Transform (FFT) is MPEG- The basic operation to be performed by the operation processor is described through the process of becoming an audio bit stream and the important operations required in each process.

Procedure 1. The scale factor (Scale FQctor) is calculated for 12 subband signals calculated from the analysis filter.

Table search operation to find the maximum and minimum values

Step 2. Obtain scale factor select information for three scale elements of each subband.

Comparison of two values

Step 3. Normalize the subband samples using the scale factor.

Division

Step 4. Obtain a signal to mask ratio (SMR) using a psycho-acoustic model.

Course 4-1. Decibel values are calculated for the 512 samples that result from the FFT calculation.

Log operation

Course 4-2. Calculate Sound Pressure Level.

Multiply and Accumulation Operations

Course 4-3. Find the Tonal component.

Comparison operation of two values

Course 4-4. Find the noise component.

Accumulation operation, log operation

Course 4-5. Decimation is performed on the pure sound components.

Addition and subtraction

Course 4-6. Get the Global Masking Threshold.

Logarithmic, Exponential Arithmetic

Course 4-7. Find the Minimum Masking Threshold.

Min find operation

Course 4-8. Obtain the signal-to-mask ratio (SMR).

subtraction

Step 5. Assign bits using the signal-to-mask ratio value.

Comparison Operations and Subtraction

Course 6. Normalization

Multiplication, addition

Process 7. Bit Packing

To sum up the operations that DSP Core must perform, add, subtract, multiply, divide, multiply and accumulate, accumulate, log, exponential, compare, and find the maximum and minimum values. , Table search, etc. Here, add, subtract, and multiply operations that are easy to implement in ASIC are basically provided, and they should be used to decide whether to perform the remaining operations or to place each module. Specific operations processed by the arithmetic processing unit of the present invention to implement an algorithm are as follows.

1. Division is used only in the normalization process. Division in the normalization process is not a division process for all numbers, but a division into a scale factor having a finite number of cases. Therefore, the reciprocal of this can be solved simply by obtaining it in advance and storing it in ROM and multiplying it.

2. An accumulator can be easily implemented with one adder, specifying one register, connecting its output value to the adder, and using the register's input value as the adder's output.

3. MAC can also be easily implemented by placing the multiplier on top and using its output as the input of the accumulator.

4. The comparison operation is to subtract, but without storing the result again, examine the value of the result to determine which one is large.

5. To find the maximum value (minimum value), subtract, but select a larger value (or smaller value) and store the value.

6. There are logarithmic and exponential operations, but there are many ways to implement them. However, many times are used to implement the MPEG audio coder to determine the success or failure of real-time processing. Therefore, their operation should be the first priority to use as few cycles as possible. Here we have a separate module for these operations. Thus, the calculation is done in one cycle. This makes all of the above possible in real time.

7. The table search operation causes separate address generation units to execute in parallel.

8. For the calculation of the scale factor, the maximum and minimum values must be derived and the absolute value taken. Therefore, the operation to find the absolute value is required.

9. Various logic operations are required for generation and reading of control words for controlling the analysis filter and the FFT unit.

Considering the above, the command set as shown in Table 1 is composed. In Table 1, AND, OR, XOR, and NOT are simple logical operations, and ADD, SUB, and MULT are simple arithmetic operations. The ABS instruction connects to the adder if the operand sign is '0' by 'pass' and if '1' is not, it is connected to the adder and the other input of the adder is set to '1'. Seek pay. Since MIN and MAX are used to find the scale factor, the absolute value must be compared to derive the maximum (or minimum) value. To do this, you can take an absolute value of each of the two values you want to compare, compare them using the compare command, and update them to a larger value (smaller value). However, this implementation requires at least four instructions, which can take considerable time to find the scale factor. Since the real-time implementation is the biggest objective, the following method is used to perform it in a single instruction, that is, one cycle. Here, the case where the maximum value is obtained will be described. For the case where the minimum value is obtained, each operation may be reversed.

(1) If the sign bit of the X operand is '0', that is positive, and the sign bit of the Y operand is also '0', that is, positive: If the sign is '0', that is, positive after subtracting two values and examining the sign of the result Keep X and update X to Y if sign bit is '1'.

(2) If the sign bit of the X operand is '0', that is positive, and the sign bit of the Y operand is '1', that is, negative: add the two values and examine the sign of the result, the sign is '0', that is, positive If X is maintained, X is updated to Y if the sign bit is '1'.

(3) If the sign bit of the X operand is '1', that is negative and the sign bit of the Y operand is '0', that is, positive: If the sign is '0', that is, positive after adding two values and examining the sign of the result Update X to Y and keep X if the sign bit is '1'.

(4) If the sign bit of the X operand is '1', that is negative and the sign bit of the Y operand is also '1', that is, negative: The sign is '0', that is, positive, after subtracting two values and examining the sign of the result. If it is, X is updated to Y, and if the bit is '1', that is, it is maintained as X.

This operation leaves a large value in X. If you do this for all the values you want to compare and run ABS last, the maximum absolute value is stored in X. That is, if the sign of X and the sign of Y are different, a control signal is made to perform subtraction. If the sign of X and the sign of the result are the same, X is maintained, otherwise it is updated to Y. In the case of MIN instruction, the sign of X is the same as the sign of result and is MAX or the sign of X is different from the sign of result and if MIN is maintained, X is maintained. Otherwise, it is updated to Y.

Figure 1 shows an embodiment implemented by applying this. ALU (1) is an arithmetic unit for logical operation, addition, subtraction, absolute value, maximum, minimum value operation, and multiplier (2), exponent operation unit (3), logarithm operation unit (4), MULT, MAC, LOG, PWR This is the configuration for operation. Many multiplexers choose either the input data path or the output data.

MIN and MAX arithmetic processing unit ALU (1) for performing general arithmetic logic operation; An accumulation register 5 connected to the output of the ALU; A multiplexer (27) which selects an input from a memory, a register or a multiplier output and supplies it to the ALU; It consists of a multiplexer 26 which selects the feedback input from the register or accumulator register 5 and supplies it to the ALU.

In addition, the exponent, log operation processing unit and a multiplier (2) for multiplying the input from the memory or register; An exponential operator (3) for exponentially calculating the output of the multiplier; A first multiplexer 28 for selecting among a memory, an exponential operation output, and an accumulation register output; A multiplication register (6) for storing the output of said first multiplexer (28); A second multiplexer (30) for outputting the output of the multiplication register (6) to a 32-bit memory; A third multiplexer (29) for selecting the output of the multiplication register (6), the output of the accumulate register, and data from a 32-bit memory; And a logarithm calculation unit 4 for logarithmically calculating the output of the third multiplexer.

The MAC instruction is a value in which the operation result of the multiplier 2 is 8-bit right shifted, or the result value accumulated from the ALU 1 to the accumulation register 5 via the multiplexer 27 is fed back through the multiplexer 26. And is added and stored in the accumulation register 5 again. The operation result of the exponential operator 3 is stored in the multiplication register 6 and output to the 32-bit memory through the multiplexer 30. In addition, data from the 32-bit memory is input through the multiplexer 28, stored in the multiplication register 6, calculated by the logarithm calculation unit 4 and output through the output multiplexer 8. MIN and MAX operations are implemented through the ALU 1 and the accumulator register 5 by the algorithm described above.

The present invention, unlike the general operation processing unit MPEG- It is designed for high speed processing to be applied to audio encoder, and real time processing is possible, and all numbers are expressed in two's complement form. In addition, logarithmic and exponential calculations are possible, and a separate module is provided for these calculations. Also, MPEG-M such as maximum and minimum calculation It is possible to implement algorithms of complex encoders in real time by designing operations that are frequently used for operations with one cycle instruction.

In addition, a preferred embodiment of the present invention is disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

The present invention is MPEG- It is about the processing processor which is the core in designing DSP core to implement audio encoder as ASIC.

The object of the present invention is to The present invention proposes a computational processing apparatus employed in a dedicated DSP suitable for performing audio compression.

It is also an object of the present invention to realize MPEG- in real time with a single dedicated DSP. The present invention proposes a computational processing apparatus employed in a dedicated DSP suitable for performing audio compression.

Claims (3)

MPEG- An arithmetic processing apparatus employed in a dedicated DSP core for an audio coding apparatus; The arithmetic processing unit includes: an independent exponential log arithmetic processing unit for logarithmic and exponential operations; And a MIN and MAX arithmetic processing unit for finding an absolute value and a maximum value and a minimum value. The MIN and MAX processing unit of claim 1, further comprising: an ALU performing general arithmetic logic; An accumulation register connected to the output of the ALU; A multiplexer that selects an input from a memory, register, or multiplier output and supplies the input to the ALU; And a multiplexer which selects a feedback input from a register or an accumulator and supplies it to the ALU. An arithmetic processing unit employed in a dedicated DSP core for an audio coding apparatus. 2. The apparatus of claim 1, wherein the exponential and logarithmic processing unit comprises: a multiplier for multiplying inputs from a memory or a register; An exponential operator for exponentially calculating the output of the multiplier; A first multiplexer for selecting among a memory, an exponential operation output, and an accumulation register output; A multiplication register for storing an output of the first multiplexer; A second multiplexer for outputting the output of the multiplication register to a 32-bit memory; A third multiplexer for selecting the output of the multiplication register, the output of the accumulate register, and data from a 32-bit memory; And a logarithm calculation unit configured to log operation of the output of the third multiplexer. An arithmetic processing unit employed in a dedicated DSP core for an audio coding apparatus.