KR19980056186A - Detection Amplifiers in Semiconductor Memory Devices - Google Patents

Abstract

The present invention relates to a sensing amplifier of a semiconductor memory device capable of improving a sensing margin by improving a sensing margin by varying a voltage of a dummy line according to a voltage change of a bit line to increase a voltage difference between the bit line and a dummy line. . The present invention provides a precharge unit comprising first and second precharge means for precharging, respectively, a dummy line to which a dummy cell is connected and a bit line to which a memory cell is connected at a predetermined voltage. A sensing amplifier of a semiconductor memory device comprising a sensing amplifier for sensing and amplifying a voltage difference between a dummy line and first and second NMOS transistors for transferring voltages of the dummy line and the bit line to the sensing amplifier. And a voltage controller for increasing the voltage difference between the bit line and the dummy line by varying the voltage between the line and the dummy line.

Description

Detection Amplifiers in Semiconductor Memory Devices

The present invention relates to a semiconductor memory device, and more particularly, to a sensing amplifier of a semiconductor memory device capable of improving a sensing margin by increasing a voltage difference between a bit line and a dummy line.

Mask ROMs are used in office automation equipment such as electronic organizers and printers, and game machines requiring high speed. The conventional mask ROM used in the above device has been relatively slowed by the sense amplifier sensing data due to the influence of a small cell current.

1 is a circuit diagram of a sense amplifier of a conventional semiconductor memory device. Referring to FIG. 1, a sense amplifier of a conventional semiconductor memory device is enabled by a sense amplifier enable signal SE, and is a dummy line 13 and a bit line generated according to data applied from the memory cell 11. The sensing amplifier 15 detects and amplifies the voltage difference of the 14 and outputs a sensed amplified signal through the output terminal SAOUT, the dummy line 13 and the memory cell 12 to which the dummy cell 11 is connected. ) Is formed of a first precharge unit 16 for precharging the bit line 14 connected to the pre-charge to a constant voltage by an equalization signal / EQ from an equalizer (not shown in the drawing).

The sensing amplifier 15 may include first and second PMOS transistors MP11 and MP12 for current mirrors and third and fourth PMOS transistors for parallel connection with the first and second PMOS transistors MP11 and MP12, respectively. First NMOS transistors MN11 and MN12 that sense-amplify and amplify the voltage difference between the MP13 and MP14, the dummy line 13 and the bit line 14, and output a sense-amplified signal through the output terminal SAOUT, and a sense amplifier. And a third NMOS transistor MN13 for current source for driving the first and second NMOS transistors MN11 and MN12 in an enable period of the enable signal SE.

The precharge circuit 16 precharges the first precharge means 16-1 for precharging the dummy line 13 to a constant voltage, and precharges the bit line 14 to a constant voltage. And a second precharge means 16-2 for giving, and the first precharge means 16-1 precharge the dummy line 13 to a constant voltage by an equalizer signal (EQ). And the sixth to eighth PMOS transistors MP16-MP18 for charging, and the second precharge means 16-2 frees the bit line 14 to a constant voltage by an equalization signal / EQ. The ninth to eleventh PMOS transistors MP19 to MP21 for charging.

In addition, the conventional sense amplifiers have equalization fourth and fifth NMOS transistors MN14 and MN15 for making the dummy line 13 and the bit line 14 equal to each other by the equalization signals EQ and / EQ. And a sixth to transfer the voltages of the dummy cell 12 and the memory cell 12 to the sensing amplifier 15 by the reference voltage Vref generated by the reference voltage generator (not shown in the drawing). And seventh NMOS transistors MN16 and MN17.

The conventional sense amplifier having the above structure has a dummy line by the first precharge unit 16 to which the equalization signal / EQ applied from the equalizer is applied in the disable section of the sense amplifier enable signal SE. 13 and bit line 14 are precharged to a constant voltage.

Subsequently, in the enable period of the sense amplifier enable signal SE, the third NMOS transistor MN13 of the sense amplifier 15 is turned on to operate the first and second NMOS transistors MN11 and MN12 to operate on the data of the memory cell. The corresponding data is output through the output terminal SAOUT.

Conventional sensing amplifier uses a general differential amplifier, and the current mirror type by using the current difference between the dummy line 13 and the bit line 14 by the precharged voltage flows the current to the bit line and dummy line It has a sense amplifier structure.

In the conventional sensing amplifier having such a structure, when the memory cell 12 connected to the bit line 14 is turned on while the voltage of the dummy line 13 is constantly fixed, the voltage of the bit line is greater than the voltage of the dummy line. Low voltage On the other hand, when the memory cell 12 connected to the bit line 14 is turned off, the voltage of the bit line 13 is higher than the dummy line voltage.

Therefore, as the memory cell 12 is turned on or turned off, data 0 or 1 of the memory cell 12 is sensed.

However, the conventional sensing amplifier has a problem that it is difficult to expect a fast data sensing speed because the voltage difference ΔV between the bit line and the dummy line is small due to the small cell currents of the bit line and the dummy line.

The present invention is to solve the problems of the prior art as described above, by increasing the voltage difference between the dummy line and the bit line, to provide a sensing amplifier of a semiconductor memory device that can improve the sensing speed by improving the sensing margin Its purpose is to.

1 is a circuit diagram of a sense amplifier of a conventional semiconductor memory device.

2 is a circuit diagram of a sensing amplifier of a semiconductor memory device according to an embodiment of the present invention;

* Description of the symbols for the main parts of the drawings *

31: Dummy cell 32: Memory cell

33: Dummy line 34: Bit line

35: detection amplification part 36: precharge branch

37: voltage controller 37-1: bit line voltage controller

37-2: Dummy line voltage regulator SE: Detection amplifier enable signal

MP31-MP45: PMOS transistor NM31-NM35: NMOS transistor

In order to achieve the above object, the present invention provides a precharge unit including first and second precharge means for precharging, respectively, a dummy line connected to a dummy cell and a bit line connected to a memory cell at a constant voltage. And a sensing amplifier for sensing and amplifying a voltage difference between the bit line and the dummy line, and first and second NMOS transistors for transferring voltages of the dummy line and the bit line to the sensing amplifier. An amplifier, characterized in that it comprises a voltage adjusting unit for varying the voltage of the bit line and the dummy line to increase the voltage difference between the bit line and the dummy line during data sensing amplification.

In the sensing amplifier of the semiconductor memory device according to an embodiment of the present invention, the voltage adjusting unit and the bit line voltage adjusting means for varying the voltage of the bit line, and the voltage of the dummy line in accordance with the voltage of the bit line And a dummy line voltage adjusting means for varying the voltage.

In a sense amplifier of a semiconductor memory device according to an embodiment of the present invention, the bit line voltage adjusting means includes a gate and a drain connected to the bit line, and a power supply voltage is applied to a source. And a second PMOS transistor connected between a second NMOS transistor and a second precharge unit of the precharge unit, to which a gate and a drain are connected to the bit line and a voltage voltage is applied to a source. It is characterized by.

In the sense amplifier of the semiconductor memory device according to an embodiment of the present invention, the dummy line voltage adjusting means is the bit line is connected to the gate, the drain is connected to the dummy line, the source voltage is applied to the source, A first NMOS transistor and a third PMOS transistor connected between a 1NMOS transistor and the dummy cell, a second precharge means of the precharge part connected to a gate, a drain connected to a dummy line, and a power supply voltage applied to a source; The precharge unit may be configured as a fourth PMOS transistor connected between the first precharge units.

EXAMPLE

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a sensing amplifier of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 2, the sense amplifier of the semiconductor memory device according to the embodiment of the present invention is enabled by the sense amplifier enable signal SE and is a dummy line 33 generated according to data applied from the memory cell 31. ) And a dummy line 33 to which a sense amplifier amplifies the voltage difference between the bit line 34 and the sense amplified signal through the output terminal SAOUT, and a dummy cell 31. And the bit line 34 connected to the memory cell 32 from an equalizer (not shown) to a precharge unit 36 for precharging to a predetermined voltage by an equalization signal / EQ. Was done.

In addition, the present invention is a voltage regulator 37 for increasing the voltage difference between the data sense amplifier bit line 14 and the dummy line 13 by varying the voltage of the bit line 14 and the dummy line 13; It further includes.

In the sensing amplifier of the semiconductor memory device according to the embodiment of the present invention, the configuration and operation of the sensing amplifier 35 and the first precharge unit are the same as in FIG. 1.

The voltage adjusting unit 37 varies the voltage of the dummy line 13 according to the bit line voltage adjusting means 37-1 for varying the voltage of the bit line 14 and the voltage of the bit line 14. It was made of a dummy line voltage adjusting means 37-2.

The bit line voltage adjusting means 37-1 is connected between the seventh NMOS transistor MN37 and the memory cell 12 in which a gate and a drain are connected to the bit line 14, and a power supply voltage Vcc is applied to the source. The second pre-charge of the seventh NMOS transistor MN37 and the precharge unit 36 to which the twelfth PMOS transistor MP42, the gate and the drain thereof are connected to the bit line 14, and the power supply voltage Vcc is applied to the source. The thirteenth PMOS transistor MP43 is connected between the azimuth means 36-2.

The dummy line voltage regulating means 37-2 has a sixth NMOS transistor (eg, a bit line 14 connected to a gate, a drain connected to a dummy line 13, and a power supply voltage Vcc applied to a source). The 14th PMOS transistor MP44 connected between the MN36 and the dummy cell 11 and the second precharge means 36-2 of the precharge unit 36 are connected to a gate thereof, and the drain is the dummy line 13. And a fifteenth PMOS transistor MP45 connected between the sixth NMOS transistor MN36 and the first precharge means of the precharge unit 36, to which a power supply voltage Vcc is applied to the source.

Although the bit line voltage adjusting means 37-1 and the dummy line voltage adjusting means 37-2 are each composed of only one PMOS transistor, it is possible to adjust the voltage of the bit line and the dummy line, but the present invention increases the effect. In order to make it a double structure is adopted.

Referring to the operation of the sensing amplifier of the semiconductor memory device according to an embodiment of the present invention having the configuration as described above are as follows.

First, in the disable period, the sense amplifier enable signal SE is transmitted through the first and second precharge means 36-1 and 36-2 of the precharge unit 36 by the equalization signal / EQ. The dummy line 13 and the bit line 14 are precharged to a constant voltage, respectively.

On the other hand, in the enable section of the sense amplifier enable signal SE, the sense amplifier 35 is operated by the sense amplifier enable signal SE in a high state to read data of the memory cell 32.

In the case of reading data, when reading data 1, the memory cell 32 is turned on to lower the voltage of the bit line 34, and accordingly, the PMOS transistors MP42 and MP43 of the dummy line voltage adjusting means 37-2 are read. ) Is turned on and the dummy line 33 is precharged to the power supply voltage.

Accordingly, the voltage of the bit line 34 is lowered and the voltage of the dummy line 33 is relatively increased to increase the voltage difference ΔV between the bit line and the dummy line, thereby improving the sensing margin.

In the case of reading data, when reading data 0, the memory cell 32 is turned off to increase the voltage of the bit line 34, and accordingly, the PMOS transistors MP44 and MP45 of the dummy line voltage adjusting means 37-2. ) Is weakly turned on to decrease the voltage of the dummy line 33.

Accordingly, the voltage of the bit line 34 is increased, and the voltage of the dummy line 33 is relatively decreased, thereby increasing the voltage difference ΔV between the bit line and the dummy line, thereby improving the sensing margin.

According to the sensing amplifier of the present invention as described above, by adjusting the voltage of the dummy line according to the voltage of the bit line by adding a voltage adjusting means to the bit line and the dummy line, increasing the voltage difference between the bit line and the dummy line Increasing the sensing margin, thereby improving the data sensing speed.

Claims (5)

A precharge part comprising first and second precharge means for precharging the dummy line to which the dummy cell is connected and the bit line to which the memory cell is connected to a predetermined voltage, respectively; In the sense amplifier of the semiconductor memory device comprising a sense amplifier for sensing and amplifying a voltage difference, and the first and second NMOS transistor for transferring the voltage of the dummy line and the bit line to the sense amplifier, And a voltage controller for varying a voltage between the bit line and the dummy line to increase a voltage difference between the bit line and the dummy line. The method of claim 1, wherein the voltage adjusting unit Bit line voltage adjusting means for varying the voltage of the bit line; And a dummy line voltage adjusting means for varying a voltage of the dummy line according to the voltage of the bit line. The method of claim 2, wherein the bit line voltage adjusting means A first PMOS transistor connected between the second NMOS transistor and the memory cell, a gate and a drain of which are connected to the bit line and a power supply voltage is applied to the source; And a second PMOS transistor connected between a second NMOS transistor and a second precharge unit of the precharge unit, in which a gate and a drain are connected to the bit line and a power supply voltage is applied to the source. Detection amplifier. The method of claim 2, wherein the dummy line voltage adjusting means A third PMOS transistor connected between the first NMOS transistor and the dummy cell, wherein the bit line is connected to a gate, the drain is connected to the dummy line, and a power supply voltage is applied to a source; A second precharge means connected to a gate of the precharge part, a drain connected to a dummy line, and a source voltage applied to a source, and connected between the first NMOS transistor and the first precharge means of the precharge part. A sense amplifier of a semiconductor memory device, characterized in that the fourth PMOS transistor. The voltage difference between the bit line and the dummy line according to claim 1, wherein when the voltage of the bit line increases, the voltage of the dummy line relatively decreases or when the voltage of the bit line decreases, the voltage of the dummy line increases relatively. The sensing amplifier of the semiconductor memory device, characterized in that for increasing.