KR19980056120A - Shallow Trench Isolation Method for Semiconductor Devices (STI) - Google Patents

Abstract

A shallow trench isolation method (STI) of a semiconductor device capable of preventing dipping occurring at the edge of a trench in a shallow trench isolation method is disclosed. To this end, the present invention comprises the steps of sequentially forming a first insulating film and a nitride film on the semiconductor substrate, by coating and patterning a photoresist on the nitride film and etching a portion of the lower first insulating film and nitride film, Stacking a polysilicon film on the resultant, performing anisotropic etching on the polysilicon film, forming spacers on side surfaces of the patterned first insulating film and the nitride film, and etching the semiconductor substrate using the nitride film as an etching mask Forming a trench, forming a second insulating film in the trench and in the spacer, depositing a third insulating film on the entire surface of the semiconductor substrate on which the second insulating film is formed, and planarizing the nitride film; A shallow trench element of the semiconductor device, comprising the steps of removing and performing wet cleaning It provides a process (STI).

Description

Shallow Trench Isolation Method for Semiconductor Devices (STI)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly, to shallowing of a semiconductor device capable of preventing dipping occurring at the edge of a trench in a shallow trench device isolation method. It relates to a trench isolation method (STI).

In recent years, as semiconductor devices have become highly functionalized and highly integrated, the importance of device isolation techniques performed at an early stage of the process has become more important. This device isolation technology is one of the difficult technical fields that requires a high level of technology compared to other processes. As a general device isolation technology, the device isolation method through local oxidation (LOCOS) and the selective polysilicon oxide (Selective Polysilicon Oxidation) method, such as to meet the design rule of the high integration era of semiconductor devices Various types of device isolation methods have been introduced, but the situation is showing its limitations. In order to overcome this limitation, the device isolation method using a trench is a method of completing device isolation by forming a trench on a semiconductor substrate and filling the inside of the trench with an oxide film generated by chemical vapor deposition. As the area can be reduced, the integration of devices is becoming more common.

1 to 5 are cross-sectional views illustrating a shallow trench isolation method (STI) of a semiconductor device in the prior art.

FIG. 1 shows that the thermal oxide film 3 is grown on the semiconductor substrate 1 to a thickness of 20 nm or less, and the nitride film 5 used as a mask during the trench etching is 100 to 300 on the thermal oxide film 3. It is formed to a thickness of ㎚. Subsequently, a photoresist film is applied and patterned on the surface of the nitride film to etch the lower semiconductor substrate 1 to form a nitride film pattern for forming a trench.

FIG. 2 is a cross-sectional view when the trench 7 is formed by etching the lower thermal oxide film 3 and the semiconductor substrate to a predetermined depth using the nitride film 5 as an etching mask.

3 is a sidewall oxide film for restoring damage generated on the sidewalls of the trenches during the formation of the trenches 7 and preventing contamination of the inside of the trenches 7 by impurities generated in subsequent processes. It is sectional drawing when 9) is formed in thickness of 20 nm or less.

FIG. 4 shows an oxide film 11 formed by Chemical Vapor Deposition (CVD) on the resultant formed trench 7, and performs a chemical mechanical polishing process to planarize the surface level. It is sectional drawing when.

FIG. 5 is a cross-sectional view when the nitride film 3 is removed by wet etching and a cleaning process is performed to remove contaminants remaining on the surface of the semiconductor substrate. In this case, in order to completely remove the contaminants remaining on the surface of the semiconductor substrate 1, sufficient over etching must be performed in the process of removing the nitride film 3. In addition, even if the same wet etching is performed, the CVD oxide film 11 has an etching rate of 2-3 times per minute as compared with the oxide film formed by the thermal oxidation method. Due to the difference between the over-etching and the etching rate, when the final cleaning process is completed, a dipping phenomenon occurs in which the edge of the CVD oxide film 11 filling the trench is recessed.

This dipping phenomenon decreases the threshold voltage of 0.1V when the depth is about 20 nm, induces a hump phenomenon in the transistor characteristics, and worsens the cut-off characteristic, thereby reducing the power consumption of the semiconductor device. Increasing or making small changes in the characteristics of the transistor even in small changes in the process may cause a decrease in overall process yield or reliability.

SUMMARY OF THE INVENTION The present invention provides a shallow trench isolation method of a semiconductor device capable of preventing a dipping phenomenon occurring at the edge of a trench in a trench isolation process of a transistor and stabilizing device operating characteristics. It is.

1 to 5 are cross-sectional views illustrating a shallow trench isolation method (STI) of a semiconductor device in the prior art.

6 to 10 are cross-sectional views illustrating a shallow trench isolation method (STI) of a semiconductor device according to an embodiment of the present invention.

* Description of Major Symbols in Drawings *

100: semiconductor substrate, 102: first insulating film,

104: nitride film, 106: polysilicon film,

108: spacer, 110: second insulating film,

112: third insulating film.

In order to achieve the above technical problem, the present invention comprises the steps of sequentially forming a first insulating film and a nitride film on a semiconductor substrate, by applying and patterning a photoresist film on top of the nitride film and a part of the lower first insulating film and nitride film Etching a layer, stacking polysilicon on the resultant, performing anisotropic etching on the polysilicon, forming spacers on side surfaces of the patterned first insulating layer and the nitride layer, and using the nitride layer as an etching mask. Etching a semiconductor substrate to form a trench; forming a second insulating film in the trench and in the spacer; depositing a third insulating film on the entire surface of the semiconductor substrate on which the second insulating film is formed; And removing the nitride film and performing wet cleaning. Device provides a shallow trench isolation method (STI).

According to the present invention, it is possible to prevent a dipping phenomenon occurring at the edge of the trench in the trench device isolation process of the transistor and to stabilize the operating characteristics of the device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

6 to 10 are cross-sectional views illustrating a shallow trench isolation method (STI) of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 6, a first insulating film 102, for example, an oxide film formed by thermal oxidation, is formed on the semiconductor substrate 100 to a thickness of 20 nm or less. Subsequently, a nitride film 104 used as a mask for trench etching is formed on the first insulating film 102 to a thickness of 100 to 300 nm, and a photoresist is applied on the nitride film 104 to form a first insulating film. The pattern 102 and the nitride film 104 are patterned to form a trench. Subsequently, a polysilicon film 106 is formed on the pattern for forming the trench to a thickness of 20 nm or less.

Referring to FIG. 7, the spacer 108 may be anisotropically etched to the semiconductor substrate on which the polysilicon film is formed, so that the polysilicon film remains only on the side surfaces of the first insulating film 102 and the nitride film 104. To form. Subsequently, the semiconductor substrate 100 is etched using the nitride film 106 having the spacer 108 formed thereon as an etching mask to form a trench.

Referring to FIG. 8, a thermal oxidation process is performed on the entire surface of the resultant product on which the spacers are formed to form a second insulating layer 110 formed of an oxide film in the trench. At this time, the spacer 108 is also simultaneously oxidized to form a part of the second insulating film 110. Here, incorporating the polysilicon spacer 108 into the second insulating film 110 using a thermal oxidation process is an important means for achieving the object of the present invention. In detail, in the prior art, the region in which the spacer is located is only filled with an oxide film generated by CVD, so that a dipping phenomenon occurs in a subsequent etching process, thereby lowering the threshold voltage and changing characteristics of the transistor. In the present invention, since the spacer is oxidized by a thermal oxidation process to be a part of the second insulating film, dipping occurs at the edge of the trench since the second insulating film is not etched better than the oxide film produced by CVD. Can be effectively prevented.

Referring to FIG. 9, a semiconductor substrate is formed by depositing a third insulating layer 112, for example, an oxide layer, and a chemical mechanical polishing (CMP) process, which are formed by performing a CVD process on the entire surface of the resultant product on which the second insulating layer 110 is formed. Planarize the surface.

FIG. 10 illustrates a process of wet etching the entire surface of the planarized semiconductor substrate to remove the nitride film 106 used as an etch mask in an etching process for forming a trench, and subsequently to form a process of etching the nitride film 106. A cleaning process is performed to remove contamination remaining on the surface of the semiconductor substrate. Here, in the present invention, the dipping phenomenon does not occur in the etching process for removing the nitride film 106 by thermally oxidizing a spacer made of polysilicon in a region where dipping occurs intensively as described above. By making the etch rate lower than the oxide film 112 produced by CVD, the object pursued by the present invention can be effectively achieved.

The present invention is not limited to the above-described embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit to which the present invention belongs.

Therefore, according to the present invention described above, it is possible to implement a trench device isolation method of a semiconductor device capable of preventing a dipping phenomenon occurring at the edge of the trench in the trench device isolation process of the transistor and stabilizing device operating characteristics. have.

Claims (1)

Sequentially forming a first insulating film and a nitride film on the semiconductor substrate; Applying and patterning photoresist on the nitride film to etch a portion of the lower first insulating film and the nitride film; Stacking a polysilicon film on top of the resultant product; Performing anisotropic etching on the polysilicon film to form spacers on side surfaces of the patterned first insulating film and the nitride film; Etching the semiconductor substrate using the nitride film as an etching mask to form a trench; Forming a second insulating layer in the trench and in the spacer; Depositing a third insulating film on the entire surface of the semiconductor substrate on which the second insulating film is formed and performing planarization; And And removing the nitride film and performing a wet cleaning process.