KR19980055819A - Data input circuit of semiconductor memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data input circuit of a semiconductor memory. In the conventional circuit, first, since the period of the DINBUFEN signal depends on the external signals / RAS, / CAS, and / WE, the operating voltage range of the external signal and the chip internal signal is particularly important. In other cases, the power loss in the interface buffer unit 31 has a lot of problems, and since the external power supply voltage (VCC) is used in both the first inverter and the next inverter which receives the input, the power loss has a lot of problems. there was. The present invention shortens the length of the DINBUFEN signal to solve this conventional problem, uses an external power supply voltage (VCC) in the first inverter that accepts an input, and less than the external power supply voltage (VCC) in other inverters. The present invention provides a data input circuit of a semiconductor memory that can reduce power loss by using an internal power supply voltage (VINT).

Description

Data input circuit of semiconductor memory

1 is a data input circuit diagram of a conventional semiconductor memory.

FIG. 2 is a detailed circuit diagram of the data input buffer section in FIG.

3 is a detailed circuit diagram of the write command detecting unit in FIG.

4 is a diagram of each sub-output waveform in FIG.

5 is a data input circuit diagram of another conventional semiconductor memory.

6 is an exemplary embodiment of the present invention,

FIG. 7 is a diagram of each sub output waveform in FIG.

8 is another exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: light command detection unit 20: pulse generator

30: Data input buffer part 31: Interface buffer part

32: latch portion 100: inverter portion

200: light enable signal generator 210: flip flop

300: the first inverter unit 400: the second inverter unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data input circuit of a semiconductor memory, and in particular, varies the operating voltage range of an external signal and an internal chip signal, and shortens an enable period of an interbase buffer that transfers an external data signal into the chip. A data input circuit of a semiconductor memory can be reduced.

FIG. 1 is a data input circuit diagram of a conventional semiconductor memory. As shown therein, a low address strobe signal (hereinafter referred to as / RAS), a column address strobe signal (hereinafter referred to as / CAS), and a write enable signal (hereinafter referred to as / WE), which are external signals, are illustrated in FIG. A write command detecting unit 10 which receives an input and internally detects a write command; A pulse generator 20 for writing to the memory cell using the detected signal when the write command is detected by the write command detecting unit 10; A plurality of data input buffer units for transmitting an external input data signal DIN_PAD into the chip according to the write enable signal WTEN and the data input buffer enable signal DINBUFEN of the write command detection unit 10. It consists of 30.

As shown in FIG. 2, the data input buffer unit 30 includes a PMOS transistor MP1 having a source connected to a power supply voltage VCC and receiving an external input data signal DIN_PAD as a gate. Is the ground (VSS) and the gate is an external input data signal (DIN_PAD) to receive the MOS transistor (MN2), the drain is connected to the drain of the PMOS transistor (MP1) and the source is the MOS transistor (MN2) An interface buffer unit 31 connected to a drain of the NMOS transistor MN1 receiving a DINBUFEN signal; A NAND gate NAND1 that receives an output signal of the PMOS transistor MP1 and the DINBUFEN signal, and outputs the NAND combination thereof; A switch SW1 that is turned on / off according to a WTEN signal to transmit an output signal of the NAND gate NAND1, an inverter INV2 that inverts an output signal of the switch SW1, and an output of the inverter INV2 A latch unit 32 which comprises an inverter INV3 for inverting the signal and applying it to the input of the inverter INV2, and latching the input data signal; NAND gate NAND2 is applied to the chip by NAND combining the WTEN signal and the output signal of the inverter INV2.

The write command detecting unit 10 is composed of three inverters (INV4-INV6) as shown in Figure 3 and the inverter unit 11 for receiving / WE, / CAS, / RAS signals respectively and inverted; NAND gate NAND3 for NAND combining the output signals of the inverters INV4 and INV5 and NAND gate NAND4 for NAND combining the output signals of the inverters INV5 and INV6 And an inverter INV7 for inverting an output signal of the NAND gate NAND4, and two NAND gates NAND5 and NAND6, each of which includes a flip-flop for receiving output signals of the NAND gate NAND3 and the inverter INV7. A write enable signal generator 13 composed of an inverter INV8 for inverting the output signal of the NAND gate NAND6 and applying it as a WTEN signal; The AND gate AND1 outputs a DINBUFEN signal by NAND combining the output signals of the inverters INV4-INV6.

The operation of the conventional apparatus configured as described above is as follows.

The data input buffer unit 30 is a buffer unit for transferring data outside the chip into the chip. When the DINBUFEN signal goes from 'low' to 'high', the interface buffer unit 31 is turned on while the NMOS transistor MN1 is turned on. Is enabled.

That is, the external signal DIN_PAD is inverted through the interface buffer unit 31 of the inverter type and is applied to one input terminal of the NAND gate NAND1.

At this time, since the WTEN signal is initially in the 'low' state, the switch SW1 is turned on, and the NAND gate NAND2 is not transmitted to the data input inside the chip because the WTEN signal is in the 'low' state.

The inverters INV2 and INV3 are sampling the outputs of the NAND gate NAND1.

In this state, when the WTEN signal is detected, the WTEN signal transitions to 'high', the switch SW1 is open, and the DIN_PAD value of the NAND gate NAND1 is latched to the inverters INV2 and INV3. At the same time, it is delivered to the data input through the NAND2.

On the other hand, the write command detecting unit 10 is a flip-flop type register.

The NENT gate NAND4 and the inverter INV7 wait 'high' at the input terminal of the NAND gate with / RAS and / CAS in a low active state.

Thereafter, when / WE is low-active, the NAND gate NAND3 outputs 'low' and applies 'high' to the other input terminal of the NAND gate NAND6 through the NAND gate NAND5.

As a result, the WTEN signal outputs 'high' and performs a write operation.

In this case, the output of the NAND gate NAND returns a 'low' state to the NAND gate NAND5 to block the NAND gate NAND3 so as to be independent of the logic change of the NAND gate NAND3.

Therefore, the path through which the WTEN signal can be reset is determined by resetting one of / CAS and / RAS to the path by NAND2.

The high set of WTEN signals is also made when / CAS transitions from 'high' to 'low' with / RAS and / WE first being 'low'.

However, as previously mentioned, the reset of the WTEN signal is independent of / WE and can only be done by a signal from / RAS or / CAS.

The above operation is described with reference to the timing diagram of FIG. 4 and is as follows.

When / RAS, / CAS and / WE are low-active, the DINBUFEN and WTEN signals are high-active to transfer external data into the chip.When / CAS or / RAS is disabled, the WTEN and DINBUFEN signals are disabled.

FIG. 5 is a data input circuit diagram of another conventional semiconductor memory. As shown in FIG. 5, a first inverter unit including a PMOS transistor MP1 and an NMOS transistor MN1 connected in series to invert an input signal to a VCC level or a VSS level is illustrated in FIG. 40; A first inverter (X1) for inverting and outputting the output signal of the first inverter unit (40); A second inverter unit (50) for inverting the output signal of the first inverter (X1) to VCC level or VSS and applying it to the input of the first inverter (X1); The second inverter X2 outputs the inverted output signal of the first inverter X1.

Looking at the operation of the conventional circuit configured as described above are as follows.

First, when the input signal is changed from 'high' to 'low', the PMOS transistor MP1 is turned on so that the potential of the node ND1 rises to the VCC level.

The potential of the node ND1 is lowered to the VSS level through the first inverter X1. As a result, the PMOS transistor MP2 is turned on to maintain the potential of the node ND1 at the VCC level.

At this time, when the input is converted to 'high' again, the NMOS transistor MN1 is turned on so that the potential of the node ND1 falls to VSS. That is, discharge from the node ND1 to ground occurs.

As such, when the potential of the node ND1 becomes VSS, the output potential of the first inverter X1 gradually increases to the VCC level. As a result, the NMOS transistor MN1 is turned on so that the potential of the node ND1 is lowered to VSS more quickly.

Thereafter, when the input becomes 'low' again, the PMOS transistor MP1 is turned on and the potential of the node ND1 is brought back to the VCC level. That is, the level of the node ND1 is precharged to the VCC level, so that the NMOS transistor MN1 is turned on.

As such, the switching threshold voltage is determined by the transition from 'low' to 'high' and from 'high' to 'low'.

As described above, in the conventional circuit, since the period of the DINBUFEN signal depends on the external signals / RAS, / CAS and / WE, the interface buffer unit ( 31), there was a lot of power loss, and there was a lot of power loss because the first inverter and the next inverter accepting the input used the external power supply voltage (VCC).

The object of the present invention is to shorten the length of the DINBUFEN signal to solve this conventional problem, and to use the external power supply voltage (VCC) in the first inverter that accepts the input, and the external power supply voltage (VCC) in the other inverters. It is to provide a data input circuit of a semiconductor memory that can reduce power loss by using a smaller internal power supply voltage (VINT).

Hereinafter, the working examples and effects of the present invention will be described with reference to Examples.

6 is an exemplary view of an embodiment of the present invention, and as shown therein, a write command detecting unit 10 which receives / RAS, / CAS, and / WE internally detects a write command; A pulse generator 20 for writing to the memory cell by using the detected signal when the write command is detected by the write command detecting unit 10; In the data input circuit of the semiconductor memory composed of a plurality of data input buffer unit 30 for transferring DIN_PAD into the chip in accordance with the WTEN signal and the DINBUFEN signal of the write command detection unit 10, the data input buffer unit ( 30, as shown in FIG. 2, a source is connected to a power supply voltage VCC terminal, a gate PMOS transistor MP1 receiving an external input data signal DIN_PAD, and a source is grounded VSS. As a gate, an NMOS transistor MN2 receiving an external input data signal DIN_PAD, a drain thereof is connected to a drain of the PMOS transistor MP1, and a source thereof is connected to a drain of the NMOS transistor MN2. The furnace includes an interface buffer unit 31 formed of an NMOS transistor MN1 for receiving a DINBUFEN signal; A NAND gate NAND1 that receives an output signal of the PMOS transistor MP1 and the DINBUFEN signal, and outputs the NAND combination thereof; A switch SW1 that is turned on / off according to a WTEN signal to transmit an output signal of the NAND gate NAND1, an inverter INV2 that inverts an output signal of the switch SW1, and an output of the inverter INV2 A latch unit 32 which comprises an inverter INV3 for inverting the signal and applying it to the input of the inverter INV2, and latching the input data signal; NAND gate NAND2 is applied to the chip by NAND combining the WTEN signal and the output signal of the inverter INV2.

The write command detecting unit 10 is composed of three inverters (INV9-INV11) as shown in Figure 6 and the inverter unit 100 for receiving the / WE, / CAS, / RAS signals respectively and inverted; NAND gate NAND7 for NAND combining the output signals of the inverters INV9 and INV10 and NAND gate NAND8 for NAND combining the output signals of the inverters INV10 and INV11 And an inverter INV12 for inverting the output signal of the NAND gate NAND8, and two NAND gates NAND9 and NAND10, each of which includes a flip-flop for receiving output signals of the NAND gate NAND7 and the inverter INV12. A light enable signal generator 200 including an inverter INV13 for inverting an output signal of the NAND gate NAND10 and applying it as a WTEN signal; An inverter INV14 that inverts the output signal of the inverter INV13; The AND gate AND2 outputs a DINBUFEN signal by NAND combining the output signal of the inverters INV4-INV6 and the output signal of the inverter INV14.

The operation of one embodiment of the present invention configured as described above will be described with reference to FIG. 7.

The operations of the inverters INV9-INV13 and the NAND gates NAND7-NAND10, which are flip-flop type registers for detecting a write command, are the same as in the related art.

That is, the NAND gate NAND8 and the inverter INV12 wait 'high' at the input terminal of the NAND gate NAND10 while the / RAS and / CAS are low-active.

Thereafter, when / WE is low-active, the NAND gate NAND7 outputs 'low', and applies 'high' to the other input terminal of the NAND gate NAND10 through the NAND gate NAND9.

As a result, the write enable signal WTEN outputs 'high' and performs a write operation. At this time, the output of the NAND gate NAND10 returns a 'low' state to the NAND gate NAND9 so as to block the NAND gate NAND10 so as not to change the logic of the NAND gate NAND7.

Therefore, the path through which the WTEN clock can be reset is determined by resetting one of the fast / CAS and / RAS by NAND2.

The high set of WTEN signals is also done when / CAS transitions from 'high' to 'low' with / RAS and / WE first being 'low'.

However, as previously mentioned, the reset of the WTEN signal is independent of / WE and can only be done by a signal from / RAS or / CAS.

The AND gate AND2 outputs high in a period where / RAS, / CAS, and / WE are all low to operate the interface buffer unit 31.

However, DINBUFEN's high section (t2) is not affected by the / RAS, / CAS and / WE signals as in the prior art, but by the 'low' signal input through the feedback packet of the inverter (INV14) when WTEN is active. 'Low' is reset.

In this way, the section t2 of DINBUFEN can be shortened.

FIG. 8 is a view illustrating another embodiment of the present invention. As shown in FIG. 8, a first inverter part including a PMOS transistor MP1 and an NMOS transistor MN1 connected in series to invert an input voltage to a VCC level or a VSS level ( 300); A first inverter (X1) for outputting an output signal of the first inverter unit (300); A second inverter unit (X2) for inverting the output of the first inverter (X1) and applying the inside of the chip; The drain is connected to the internal power supply voltage VINT, the gate is connected to the NMOS transistor MN2 receiving the output signal of the second inverter X2, the source is connected to the ground voltage VSS, The second inverter unit (1) receives an output signal of the first inverter (X1), and a drain is formed of a source of the n-MOS transistor (MN2) and an n-transistor (MN3) connected to an input terminal of the first inverter (X1). 400).

Referring to the operation of another embodiment of the present invention configured as described above are as follows.

First, the reason why the source of the PMOS transistor MP1 of the first inverter is connected to VCC is to prevent a through current with VSS in the standby state.

In other words, if VINT is used instead of VCC, the leakage current can flow according to the voltage of the input terminal.

Assume that the input of the TTI level comes in a triangular wave form.

If the input is 'low', the PMOS transistor MP1 is turned on, and the potential of the contact ND1 is at the VCC level.

The potential of the contact ND1 is inverted to the VSS potential through the first inverter X1 and applied to the gate of the n-MOS transistor MN3. At the same time, the voltage is inverted to the VINT level through the second inverter X2 and applied to the gate of the NMOS transistor MN2.

As a result, both the NMOS transistor MN2 and the NMOS transistor MN3 are turned off. In other words, the NMOS transistor MN3 is naturally turned off, and in the case of the NMOS transistor MN2, the gate-source voltage is almost 0V, so it is turned off. Therefore, the path from the contact ND1 to VINT is blocked.

At this time, when the input is changed linearly high, the discharge phenomenon from the contact ND1 to ground occurs while the NMOS transistor MN1 starts to turn on.

When the potential of the contact point ND1, which gradually decreases over time, falls below VINT-Vt, the enMOS transistor MN2 starts to turn on. At this time, Vt is the threshold voltage of the NMOS transistor MN2.

Therefore, since it is advantageous to minimize the value of Vt, the NMOS transistor MN2 uses a low Vt enMOS transistor.

In this way, when the MOS transistor MN2 is turned on, the potential of the contact ND1 will try to be maintained at VINT-Vt. Therefore, the potential of the contact ND1 falls to VSS for external noise at a level slightly higher than the input signal. Will interfere. Therefore, logical errors due to external noise can be minimized.

When the high signal is inputted to the input terminal IN, the Vgs of the NMOS transistor MN1 becomes high, so that the potential of the contact ND1 becomes VSS, and this signal becomes the VINT level through the inverter X1.

Therefore, the enMOS transistor MN3 is turned on to pull the potential of the contact ND1 down to VSS. Accordingly, the voltage output through the inverter X2 becomes VSS.

The low limit of the VIH is determined for a signal whose input goes from low to high.

On the contrary, when the input changes from high to low, the level of the contact point ND1 becomes VSS and then gradually increases to the VCC level due to the increase of the Vgs of the PMOS transistor MP1. As a result, the final output voltage is at the VINT level.

At this time, when the potential of the contact ND1 becomes less than VINT-Vt, the NMOS transistor MN2 is turned on. When the level of the contact ND1 is higher than that, the NMOS transistor MN2 is turned off, and the output voltage is at the VINT level. Will be maintained.

As described in detail above, the present invention shortens the enable period of the interface buffer unit for inputting data internally, and uses an external power supply voltage (VCC) for the first inverter that receives the input, and an external power supply for the other inverters. The power loss can be reduced by using an internal power supply voltage VINT that is smaller than the voltage VCC.

Claims (2)

A write command detection unit receiving / RAS, / CAS, and / WE to internally detect a write command; A pulse generator for writing to a memory cell by using the detected signal when a write command is detected by the write command detector; In a data input circuit of a semiconductor memory comprising a plurality of data input buffer units for transferring DIN_PAD into a chip according to the WTEN signal and the DINBUFEN signal of the write command detection unit, The write command detecting unit comprises: first inverting means for receiving and inverting / WE, / CAS and / RAS signals, respectively; A write enable signal generator configured to flip-flop and output a write enable signal by logically combining the inverted signals of / WE, / CAS and / RAS through the first inverting means; Second inverting means for inverting the write enable signal; And a data input buffer enable signal generating means for enabling a data input buffer according to the output signal of said first inverting means and disabling it according to the output signal of said second inverting means. Circuit. A first inverter part including a connected PMOS transistor MP1 and an enMOS transistor MN1 to invert an input signal to a VCC level or a VSS level; A first inverter (X1) for inverting and outputting the output signal of the first inverter unit; A second inverter (X2) for inverting the output of the first inverter (X1) and applying the inside of the chip; The drain is connected to the internal power supply voltage VINT, the gate is connected to the NMOS transistor MN2 receiving the output signal of the second inverter X2, the source is connected to the ground voltage VSS, The output signal of the first inverter (X1) is received, the drain is composed of a second inverter unit consisting of the source of the enMOS transistor (MN2) and the input terminal of the first inverter (X1) (MN3). A data input circuit of a semiconductor memory, characterized in that.