KR19980053693A - Gate electrode formation method of semiconductor device - Google Patents

Abstract

The present invention relates to a technique for forming a gate electrode having a critical dimension or less using a difference in etching speed between a doped polysilicon film and a silicide film. Providing; Forming a gate oxide film of a thin film on the active region; Sequentially forming a polysilicon film, a silicide film, and an anti-reflection film doped over the whole;

Forming a gate electrode by etching the diffuse reflection prevention film, the silicide film, and the doped polysilicon film so that the doped polysilicon film is undercut; Forming a low concentration impurity junction region in both semiconductor substrate regions of the gate electrode; Forming a spacer on sidewalls of the gate electrode; And forming a high concentration impurity junction region in the semiconductor substrate using the spacer as an ion implantation mask.

Description

Gate electrode formation method of semiconductor device

The present invention relates to a method of forming a gate electrode of a semiconductor device, and more particularly, to a method of forming a gate electrode of a semiconductor device using a difference in etching speed between a polysilicon film and a silicide film to form a gate electrode having a critical dimension or less. will be.

In general, MOS (Metal Oxide Semiconductor) is a device composed of a semiconductor substrate, an insulating film stacked thereon and a gate electrode of a metal material, as the name implies.

In order to form such a MOS transistor, as shown in FIG. 1, a device isolation film 2 is formed on a semiconductor substrate 1, and a gate oxide film of a thin film is formed on an active region between the device isolation films 2. After (3) is formed, a doped polysilicon film 4 is formed to form a gate electrode over the whole.

Subsequently, the silicide layer 5 and the diffuse reflection prevention layer 6 are sequentially formed to improve the conductivity of the doped polysilicon layer 4, and the doped polysilicon layer 4, the silicide layer 5 and The antireflection film 6 is etched in a predetermined form to form a gate electrode.

Then, a low concentration impurity junction region 7 is formed in the active region of the substrate 1 by ion implanting low concentration impurities into the semiconductor substrate 1 using the gate electrode as an ion implantation mask. A spacer 8 is formed on the sidewall of the gate electrode, and a high concentration impurity junction region 9 is formed by ion implanting high concentration impurities into the substrate 1 region.

However, the prior art as described above has a problem in that it is very difficult to form a gate electrode having a fine size, for example, a critical dimension of 0.15 μm or less according to the trend of ultra high integration of semiconductor devices.

Accordingly, an object of the present invention is to provide a method for forming a gate electrode of a semiconductor device capable of forming a gate electrode having a critical dimension or less by using a difference in etching speed between a doped polysilicon film and a silicide film.

1 is a cross-sectional view for explaining a gate electrode forming method of a semiconductor device according to the prior art.

2A to 2D are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device according to the present invention.

Explanation of symbols on the main parts of the drawings

11: semiconductor substrate 12: device isolation film

13 gate oxide film 14 doped polysilicon film

15: tungsten silicide 16: diffuse reflection prevention film

17 low concentration impurity junction region 18 spacer

19: high concentration impurity junction region

The above object is to provide a semiconductor substrate on which a device isolation film is formed; Forming a gate oxide film of a thin film on the active region; Sequentially forming a polysilicon film, a silicide film, and an anti-reflection film doped over the whole; Forming a gate electrode by etching the diffuse reflection prevention film, the silicide film, and the doped polysilicon film so that the doped polysilicon film is undercut; Forming a low concentration impurity junction region in both semiconductor substrate regions of the gate electrode; Forming a spacer on sidewalls of the gate electrode; And forming a high concentration impurity junction region in the semiconductor substrate using the spacer as an ion implantation mask.

According to the present invention, during the etching process for forming the gate electrode, the doped polysilicon film is under cut because the etching rate of the doped polysilicon film and the silicide film is different, thereby forming a gate electrode having a fine size can do.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to FIGS. 2A to 2D.

Referring to FIG. 2A, an isolation layer 12 for separating an element from an element is formed on a semiconductor substrate 11, a gate oxide layer 13 of a thin film is formed on an active region, and then the gate oxide layer ( 13, a doped polysilicon film 14 for forming a gate electrode is formed. Subsequently, a tungsten silicide film 15 and an antireflection film 16 for improving its conductivity are laminated on the doped polysilicon film 14. In this case, one of the molybdenum silicide film, the tantalum silicide film, the cobalt silicide film, the chromium silicide film, the niobium silicide film, and the vanadium silicide film may be formed instead of the tungsten silicide film.

Referring to FIG. 2B, an antireflection film 16, a tungsten silicide film 15, a doped polysilicon film 14, and a gate oxide film 13 may be etched by a predetermined photoresist pattern (not shown). Etch In this case, the doped polysilicon layer 14 is etched under the tungsten silicide layer 15 by using an etching rate difference between the tungsten silicide layer 15 and the doped polysilicon layer 14. .

In detail, the anti-reflective coating 16, which is usually formed of a material of a TiN film or a nitric oxide film, having a thickness of about 150 to 300 kPa, is made of CHF ₃ of 1,000 to 2,000 mTorr, 300 to 500 Watt, 10 to 50 SCCM, CF ₄ of 100 to 100 SCCM, and 100 to 100 After anisotropic etching at an etching rate of about 700 to 1,500 mW / min under an etching condition such as He of 200 SCCM, the tungsten silicide layer 15 and the doped polysilicon layer 14 were 100 to 500 mTorr, 300 to 500 Watt. , Tungsten silicide layer 15 under an etching condition such as Cl ₂ of 10 to 70 SCCM, SF ₆ of 10 to 50 SCCM, He of 100 to 200 SCCM, and an etch rate of about 3,500 to 4,500 μs / min, and doped polysilicon The film 14 is anisotropically etched to have an etch rate of about 6,000 to 7,000 kW / min.

Then, in order to remove the residual polysilicon film, 100 to 500 mTorr, 150 to 300 Watt, poly ₂ of 100 to 150 SCCM, HBr of 30 to 100 SCCM, He to 100 to 200 SCCM, and about 2,500 to 3,500 mW / min poly Transient etching is performed at a silicon film etch rate and a gate oxide film etch rate of about 25 to 50 mA / min to form a fine gate electrode.

Referring to FIG. 2C, the low concentration impurity junction region 17 is implanted into the active region of the substrate 11 by ion implantation of the low concentration impurity twice in succession to the semiconductor substrate 11 at an angle of about ± 3 ° to ± 10 °. Form.

Referring to FIG. 2D, an oxide spacer 18 is formed on a sidewall of the gate electrode by a known method, and then a high concentration of impurities are implanted into the active region of the substrate 11 by ion implanting high concentration impurities in a direction perpendicular to the semiconductor substrate 11. The impurity junction region 19 is formed.

As described above, the gate electrode forming method of the semiconductor device of the present invention is critical dimension by using the difference in the etching rate of the doped polysilicon film for forming the gate electrode and the silicide film formed to improve the conductivity of the polysilicon film The following gate electrodes can be formed.

Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (15)

Providing a semiconductor substrate provided with a device isolation film; Forming a gate oxide film of a thin film on the active region; Sequentially forming a polysilicon film, a silicide film, and an anti-reflection film doped over the whole; Forming a gate electrode by etching the diffuse reflection prevention film, the silicide film, and the doped polysilicon film so that the doped polysilicon film is undercut; Forming a low concentration impurity junction region in both semiconductor substrate regions of the gate electrode; Forming a spacer on sidewalls of the gate electrode; And Forming a high concentration impurity junction region in said semiconductor substrate using said spacer as an ion implantation mask. The method of claim 1, wherein the silicide layer is tungsten silicide. The semiconductor device according to claim 2, wherein the semiconductor device can be formed of one selected from molybdenum silicide film, tantalum silicide film, cobalt silicide film, chromium silicide film, niobium silicide film, and vanadium silicide film. Gate electrode formation method. 2. The method for forming a gate electrode of a semiconductor device according to claim 1, wherein the diffuse reflection prevention film is a TiN film or an oxynitride film. The anti-reflective coating of claim 1, wherein CHF _{3 from} 1,000 to 2,000 mTorr, 300 to 500 Watts, 10 to 50 SCCM A method of forming a gate electrode of a semiconductor device, characterized by etching under etching conditions such as CF ₄ of 50 to 100 SCCM and He of 100 to 200 SCCM. The method of claim 5, wherein the anti-reflective coating is etched at an etching rate of about 700 to 1,500 kW / min. The method of claim 1, wherein the tungsten silicide film and the doped polysilicon film 100 to 500 mTorr, 300 to 500 Watts, Cl ₂ of 10 to 70 SCCM 10 and 50 the gate electrode forming method of a semiconductor device characterized in that the etching in the etching conditions such as SCCM of SF _6, of 100 to 200 SCCM He. The method of claim 7, wherein the tungsten silicide layer is etched at an etching rate of about 3,500 to 4,500 Å / min. The method of claim 7, wherein the doped polysilicon layer is etched at an etching rate of about 6,000 to 7,000 Å / min. The method of claim 1, wherein the polysilicon film remaining in the etching process of the doped polysilicon film is removed. Cl _{2 from} 100 to 500 mTorr, 150 to 300 Watts, 100 to 150 SCCM A method of forming a gate electrode of a semiconductor device, characterized by etching under etching conditions such as HBr of 30 to 100SCCM and He of 100 to 200SCCM. The method of claim 10, wherein the polysilicon layer is etched at an etching rate of about 2,500 to 3,500 Å / min. The method of claim 10, wherein the gate oxide layer is simultaneously etched when the residual polysilicon layer is etched. The method of claim 12, wherein the gate oxide layer is etched at an etching rate of about 25 μm / min to 50 μm / min. The method of claim 1, wherein the low concentration impurity junction region is formed by implanting low concentration impurities twice in succession at a slope of about ± 3 ° to ± 10 °. The method of claim 1, wherein the high concentration impurity junction region is formed by implanting high concentration impurity ions in a direction perpendicular to the semiconductor substrate.