KR19980053137A - Electrostatic Discharge Protection Circuit - Google Patents

Abstract

The present invention relates to an electrostatic protection circuit to provide an electrostatic protection circuit suitable for reducing the driving voltage by protecting the internal circuit by discharging the static electricity easily input even when the power supply voltage is not applied. To this end, the electrostatic protection circuit of the present invention includes the first and second impurity regions of the second conductivity type and the first impurity region of the second conductivity type formed with a device isolation film interposed in a predetermined region of the first conductivity type substrate. A gate electrode formed on a substrate of a first impurity region of a first conductivity type, a second impurity region of a first conductivity type, and a third impurity region of a second conductivity type formed therebetween, and a second impurity region of a second conductivity type And second and second impurity regions of the second conductivity type with the third and fourth impurity regions of the first conductivity type formed on the substrates on both sides of the gate electrode, the fourth impurity regions of the second conductivity type and the device isolation film interposed therebetween. And a fourth impurity region of the second conductivity type formed in the region, and a fifth impurity region of the first conductivity type formed on the substrate of the first conductivity type.

Description

Electrostatic Discharge Protection Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic protection circuit, and more particularly, to a static protection circuit of a semiconductor device suitable for reducing a driving voltage of an electrostatic protection circuit by floating a well in a state where a bias is not applied.

Hereinafter, a conventional electrostatic protection circuit will be described with reference to the accompanying drawings.

1 is a circuit diagram of a conventional static electricity protection circuit.

As shown in FIG. 1, the conventional static electricity protection circuit includes a first transistor 11 having a collector connected to a substrate and an emitter connected to an input pad, a collector connected to an emitter of the first transistor 11, and an emitter A second transistor 12 connected to a Vss line and commonly connected to a base of the first transistor 11, and a P-well resistor 13 formed between the base of the second transistor 12 and the Vss line. It is composed of

2 is a structural cross-sectional view of a conventional static electricity protection circuit, a substrate 21, a P-well region 22 formed in a predetermined region on the substrate 21, and a substrate 21 in the P-well region 22. As shown in FIG. The P-well region having the first, second and third impurity regions 23, 24, and 25 formed between the device isolation layers and the impurity regions 23, 24, and 25 and the device isolation layer therebetween. The fourth impurity region 26 formed in the substrate 21 instead of the 22 is comprised.

Here, the substrate 21 is of N conductivity type and the first and second impurity regions 23 and 24 in the P-well region 22 are the same conductivity type as the substrate 21.

In addition, the third impurity region 25 is opposite to the substrate 21.

In the static electricity protection circuit, the fourth impurity region 26 and the first impurity region 23 are used as collectors and emitters of the first transistor 11.

The first impurity region 23 and the second impurity region 24 are used as collectors and emitters of the second transistor.

That is, the first impurity region 23 is used as an emitter of the first transistor 11 and a drain region of the second transistor 12.

In addition, the P-well region 13 shown in FIG. 1 is implemented by the P-well region 22.

The operation description of the conventional static electricity protection circuit configured as described above is as follows.

As shown in FIGS. 1 and 2, when a positive voltage (electrostatic) is applied through an input pad, a junction between the first impurity region 23 and the P-well region 22 connected to the pad is applied. Breakdown occurs.

Therefore, the P-well current flowing through the third impurity region 25 to the Vss line increases.

This induces a voltage rise in the P-well region 22 and eventually acts as an NPN bipolar junction transistor.

When the voltage of the P-well region 22 rises by 0.6 V or more, as shown in FIG. 1, the second transistor 12 is turned on so that the positive static electricity applied to the input pad is transferred to the Vss line. Passing prevents static electricity from entering the internal circuit.

However, such a conventional static electricity protection circuit has the following problems.

First, in order to protect the internal circuit from static electricity, a power supply voltage (Vcc) must always be applied, so a lot of driving voltage is required.

Second, if the resistance of the P-well region is not high, the voltage rise becomes difficult, and thus the driving voltage of the NPN bipolar transistor is increased.

Therefore, since the driving voltage for driving the NPN bipolar transistor is high, initial static electricity flows into the internal circuit and the internal circuit is destroyed.

An object of the present invention is to provide an electrostatic protection circuit suitable for bypassing even the initial static electricity by driving an NPN bipolar transistor under a low driving voltage.

1 is a circuit diagram of a conventional static electricity protection circuit

2 is a structural cross-sectional view of a conventional static electricity protection circuit

3 is a circuit diagram of an electrostatic protection circuit of the present invention;

Figure 4 is a structural cross-sectional view of the static electricity protection circuit of the present invention

Explanation of symbols on the main parts of the drawings

31 and 32: first and second bipolar transistors 33: NMOS transistors

42, 43: second conductivity type first and second impurity regions 47: gate electrode

In order to achieve the above object, an electrostatic protection circuit of the present invention includes first and second impurity regions of a second conductivity type formed with a device isolation film in a predetermined region of a first conductivity type substrate, and the second conductivity type. A substrate of a first impurity region of a first conductivity type, a second impurity region of a first conductivity type and a third impurity region of a second conductivity type, and a second impurity region of a second conductivity type formed in the first impurity region of the first impurity region The second conductive layer having a gate electrode formed thereon, third and fourth impurity regions of a first conductivity type formed on substrates on both sides of the gate electrode, and a fourth impurity region of the second conductivity type and an element isolation film interposed therebetween. And a fourth impurity region of the second conductivity type formed in the second impurity region of the mold and a fifth impurity region of the first conductivity type formed on the substrate of the first conductivity type.

Hereinafter, the electrostatic protection circuit of the present invention will be described with reference to the accompanying drawings.

3 is a schematic structural diagram of the static electricity protection circuit of the present invention, and FIG.

First, as shown in FIG. 3, the electrostatic protection circuit of the present invention implements a MOS transistor instead of the conventional P-well resistor.

This will be described in more detail as follows.

A first transistor 31 connected to a collector and an emitter connected to an input pad, a collector connected to a pad connected to an emitter of the first transistor 31, an emitter connected to a Vss line, and a base connected to the substrate; And a second transistor 32 commonly connected to the base of the first transistor 31, and an NMOS transistor 33 formed between the base of the second transistor 32 and the Vss line.

4 is a cross-sectional view of the structure according to the electrostatic protection circuit of the present invention, the first conductive substrate 41 and the first impurity region 42 of the second conductive type formed between the device isolation film in the substrate 41. And second impurity regions 43 and first and second impurity regions of the first conductivity type formed between the device isolation film in the substrate 41 in the first impurity region 42 of the second conductivity type. 44 and 45 and the third impurity regions 46 of the second conductivity type, the gate electrode 47 formed in the predetermined region on the substrate 41 in the second impurity region 43 of the second conductivity type and the First and third impurity regions 48 and 49 of the first conductivity type formed on the substrate 41 on both sides of the gate electrode 47, and the fourth impurity region 49 and the isolation layer interposed therebetween. The fourth conductive region 50 of the second conductivity type, the first impurity region 42 of the second conductivity type, and the device isolation film are interposed therebetween. The fifth impurity region 51 of the first conductivity type formed on the substrate 41 is included.

Here, the third and fourth impurity regions 48 and 49 of the first conductivity type and the gate electrode 47 implement one MOS transistor, and the first impurity region 42 and the region of the second conductivity type are implemented. The first and second impurity regions 44 and 45 of the first conductivity type and the third impurity regions 46 of the second conductivity type implement a bipolar transistor.

Operation of the electrostatic protection circuit of the present invention configured as described above is as follows.

3 to 4, when static electricity is applied through the pad, the first impurity region 44 of the first conductivity type connected to the pad and the first impurity region 42 of the second conductivity type are connected to the pad. Breakdown occurs.

Therefore, the P-well current flowing to the Vss line through the second impurity region 45 of the first conductivity type is increased.

This induces a voltage rise of the first impurity region (P-well region) 42 of the second conductivity type, and thus acts as an NPN bipolar junction transistor.

When the voltage of the first impurity region 42 of the second conductivity type rises by 0.6V or more, a positive (+) static electricity applied to the input pad by turning on the second transistor 32 as shown in FIG. 3. Bypassing to the Vss line prevents static electricity from entering the internal circuit.

In this case, in the electrostatic protection circuit of the present invention, when the power supply voltage Vcc is not applied, the MOS transistor is floated.

That is, when no power voltage is applied, it means that no power is applied to the gate of the MOS transistor, and when no power is applied to the gate, the MOS transistor is turned off.

As a result, if the MOS transistor is turned off, it means that the resistance is very large, which means that the resistance of the second impurity region 42 of the second conductivity type is very large, as shown in FIG.

Therefore, the time for turning on the second transistor 32 is shortened, which prevents static electricity from flowing into the internal circuit by bypassing the positive static electricity applied to the input pad to the Vss line.

As described above, the electrostatic protection circuit of the present invention has the following effects.

Since the P-well floats while the power supply voltage (Vcc) is not applied, the P-well voltage changes more easily when the power supply voltage is applied, thereby lowering the driving voltage of the bipolar transistor. Pass it.

Claims (4)

First and second impurity regions of a second conductivity type formed with a device isolation film in a predetermined region of the first conductivity type substrate, First and second impurity regions of the first conductivity type and third impurity regions of the second conductivity type formed in the first impurity region of the second conductivity type with the device isolation film interposed therebetween; A gate electrode formed on the substrate of the second impurity region of the second conductivity type; Third and fourth impurity regions of a first conductivity type formed on substrates on both sides of the gate electrode; A fourth impurity region of the second conductivity type formed in the second impurity region of the second conductivity type with the fourth impurity region of the second conductivity type interposed therebetween; And a fifth impurity region of the first conductivity type formed on the substrate of the first conductivity type. The static electricity protection circuit according to claim 1, wherein the first conductivity type is N conductive and the second conductivity type is P conductive. 2. The NMOS transistor according to claim 1, wherein the second impurity region of the second conductivity type, the gate electrode, and the third and fourth impurity regions of the first conductivity type formed on both sides of the gate electrode are formed. Static electricity protection circuit. 2. The bipolar transistor according to claim 1, wherein the bipolar transistor is composed of the first impurity region of the second conductivity type, the first, second and fifth impurity regions of the first conductivity type, and the third impurity region of the second conductivity type. Electrostatic protection circuit, characterized in that.