KR19980053017A - Method of adding absolute error value of motion estimator and adder structure - Google Patents

Abstract

The present invention relates to an adder of a motion estimator and more particularly to an addition method and an adder structure for simplifying interconnection of a pipeline structure adder applying a Wallace tree, The matrix is multiplied by a 4-input, 2-output Wallis tree to reduce the matrix size to half the size. Divided into groups The structure of the present invention is such that the first and second wallis adders 40 and 41, the third wallis adder 42 and the fourth wallis adder 43 And a merge adder 47 for outputting an absolute error value (MAE), and the fifth and sixth wavelet adders 44 and 46 are provided. The two adjacent adder outputs from the stage Wallace addition unit are input to the adder of the Wallace addition unit of the next stage to simplify the interconnection between the modules and reduce the hardware number (Wallace tree) Is reduced.

Description

Method of adding absolute error value of motion estimator and adder structure

The present invention relates to an adder of a motion estimator and more particularly to an adder of a motion estimator that simplifies interconnection between modules of an adder having a pipeline structure using a Wallace tree, An error value addition method, and an adder structure.

In general, since a two-dimensional moving image has a large amount of information, a considerable frequency band is required for its transmission. In order to solve this problem, there is redundancy of information, so information can be compressed. At this time, redundancy on the time axis can compress information through motion compensation, and an important point here is a motion vector estimator.

Motion vector extraction algorithms include PRA (Pel Recursive Algorithm) and block matching algorithm.

A block matching algorithm (BMA) divides a current frame into blocks of a fixed size (hereinafter referred to as reference blocks), and assumes that each reference block independently displaces in a predetermined area of a previous frame in block units will be.

At this time, assuming that the motion of the screen is parallel or horizontally moved, the block image of the frame in which the motion has occurred (i.e., the current frame) Estimates a motion vector, and estimates a motion vector through the position. At this time, 8 × 8 and 16 × 16 (number of horizontal pixels × number of vertical pixels) are mainly used as block sizes.

Here, in order to find the previous block most similar to the reference block of the current frame, a certain range is searched around the position of the reference block in the previous frame. Such a range is called a search window, The difference between each candidate block and the candidate block is referred to as distortion and indicates the degree of similarity between the two blocks.

As a result, in the video signal processing technology, 'motion estimation' is a method of indicating how much the pixels of the current frame move relative to the previous frame in a continuous video signal as a vector Is a technique of estimating a motion vector and compressing transmission information by transmitting these motion vectors instead of transmitting the entire image (i.e., image compression).

In this paper, we propose a new algorithm for finding the motion vector of a motion vector. In this paper, we propose a new algorithm that can find the motion vector relatively accurately. (Full search block matching algorithm).

Extraction of Motion Vector Using Full Search Block Matching Algorithm The general expression is obtained by the following equation.

[Equation 1]

In the above equation, Represents each pixel value in the (i, j) coordinate in the reference block of the current frame, Represents each pixel value at the position of the reference block of the previous frame.

The Wow (Absolute value difference) of the input signal. The Represents an accumulated value obtained by summing up the pixel value absolute difference values of the pixel values up to the k rows of the j-th column of the search block having the motion vector of the coordinates.

The Represents the total cumulative value of absolute difference values between the search block having the motion vector of the coordinates and the reference block.

The All coordinates within the range -p / + p To have the smallest value among As a motion vector of the reference block.

here, The value obtained by dividing the value by the block size is called mean absolute error (MAE).

As shown in the above equation, the basic operations required in the motion estimation include a subtraction process for obtaining a difference between a reference block and a candidate block, and an addition process for obtaining an absolute error value by adding all difference values obtained by subtraction in a macroblock have.

In particular, the adder that needs to add all the difference values requires a high speed, so it can be manufactured with a Wallace tree pipeline structure.

Here, 'Wallis tree' is a multiply operand addition circuit that adds a plurality of partial products, which are the largest and most important among the parallel multiplier internal circuits, to two output lines (Carry and Sum) CS Presented by Wallace.

FIG. 1 is a block diagram illustrating a conventional pipeline adder structure using a Willis tree in a motion estimator, and FIG. 2 is a conceptual diagram illustrating an operation of adding difference values of a macroblock according to the conventional FIG. 1 in motion estimation.

The structure shown in Fig. 1 is applied when the macroblock size (number of horizontal data x number of vertical data) is 16x16.

Referring to FIG. 1, the adder of the conventional 7-stage pipeline structure includes a first wallis adder 100, a second wallis adder 110, a third wallis adder 120, A fifth wallis adder 140, a sixth wallis adder 150, and a merge adder 160. The fifth and sixth wallis adders 150 and 160 are connected to each other.

The first to sixth adders 110 to 150 include a plurality of 4-input, 2-output Wallace trees W42. The merge adder 160 adds And an adder that adds up all four commands.

The adder operation as shown in FIG. 1 will be described with reference to FIG. 2. In the first step (step 1), 16 pixels corresponding to one column in a 16 × 16 matrix representing the difference between two blocks And adds 16 pixels corresponding to 2 columns to the first wallis adder 100 through the first set 100-1 of the first wallis adder 100, Two sets (100-2) to output 8 data, and for the remaining columns (3 to 16 columns), 16 pixels are similarly reduced to 8 data and output.

After the first step is performed through the first wavelet adder 100, if the eight data output from each set of the adder 100 are arranged in columns, a 16 × 8 matrix appears.

In the second step (step 2), 16 pieces of data corresponding to one row in the 16x8 matrix are added through a set 110-1 of the second walley adder 110, 16 data corresponding to 2 rows are added through the second set 110-2 of the second walley adder 110 to output 8 data, and the remaining rows 3 8 rows), the 16 pixels are similarly reduced to 8 data and output.

After the second step is performed through the second wally adder 110, the eight data output from each set of the adder 510 is arranged in a row-wise manner, so that an 8x8 matrix is displayed.

After the third step is performed through the third wallis adder 120, the data is displayed as an 8x4 data matrix. After the fourth step is performed through the fourth wallis adder 130, 8x2 Data matrix. After the fifth step is performed through the fifth wallis adder 140, a 4 × 2 data matrix is displayed. After the sixth step is performed through the sixth wallis adder 150, , And a 4x1 data matrix.

Now, in the seventh step (step 7), four data of the 4x1 matrix are summed by using the merge adder 160 and one data is output. This value corresponds to the absolute error value (MAE) of the finally calculated candidate block.

However, the adder having the conventional pipeline structure has a problem in that the connection (interconnection) between the input line and the output line between the modules is complicated. Also, there is a problem that a large amount of area is required for complicated interconnection when a VLSI is manufactured.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an absolute error value addition method of a motion estimator in which the number of hardware, that is, To provide an adder structure.

According to an aspect of the present invention, Each pixel value of the matrix (the number of horizontal pixels x the number of vertical pixels) A first step (step 1) of calculating by a matrix; In the first step (step 1) The addition is performed on the matrix A second step (step 2) of calculating a matrix; In the second step (step 2) Is added to the matrix A third step (step 3) of calculating a matrix; In the third step (step 3) By adding the matrix A fourth step (step 4) of calculating a matrix; In the fourth step (step 4) By adding the matrix A fifth step (step 5) of calculating a matrix; In the fifth step (step 5) By adding the matrix A sixth step (step 6) of calculating a matrix; In the sixth step (step 6) Matrix Added A seventh step (step 7) of calculating a matrix; And the seventh step And an eighth step (step 8) of adding the matrix to obtain an absolute error value (MAE).

In order to achieve the above object, the adder structure of the present invention includes The difference value is added A first wallis adder 40 for outputting data; And outputs it to the first wallis adder 40 The addition is performed on the data A second wallis adder 41 for outputting data; And outputs it to the second wallis adder 41 The data is added A third wallis adder 42 for outputting data; The third wallis signal output from the third wallis adder 42 The data is added A fourth wallis adder 43 for outputting data; The fourth wallis signal outputted from the fourth wallis adder 43 The data is added A fifth wallis adder 44 for outputting data; The fifth wallis adder 44 outputs the fifth The data is added A sixth wallis adder 45 for outputting data; The sixth wallis adder 45 outputs the The data is added A seventh wallis adder 46 for outputting data; And the seventh wallis adder (46) And a merge adder 47 for adding the data and outputting an absolute error value MAE.

1 is a block diagram showing a conventional adder structure using Willis trees in a motion estimator,

FIG. 2 is a conceptual diagram illustrating an operation of adding difference values of a macroblock according to the conventional FIG. 1 in motion estimation;

FIG. 3 is a basic structure diagram of a pipeline processor applied to the present invention,

FIG. 4 is a block diagram illustrating an adder structure according to FIG. 3 using a Wallace tree in a motion estimator;

FIG. 5 is a conceptual diagram illustrating an operation of adding difference values of a macroblock according to FIG. 4,

6 is a bit map for explaining the Wallace tree operation for reducing the four commands used in the present invention to two orders,

FIG. 7 is a detailed configuration diagram showing a detailed structure of a 4-input, 2-output adder (a Wallace tree) implemented by a full adder in FIG.

Description of the Related Art [0002]

40: first wallis adder 41: second wallis adder

42: Third Wallis adder 43: Fourth Wallis adder

44: fifth wallis addition part 45: sixth wallis addition part

46: Seventh Wallis addition part 47: Merge addition part

W ₄₂ : 4 input 2 output adder (Wallis tree)

First, generally, each stage of the pipeline structure is constituted by a combination circuit, and is useful when it is desired to carry out the operation repeatedly by transmitting data obtained through logic or arithmetic operation through a pipe. Here, the interface latches transmitting the operation result of each stage must be operated in synchronization with the same clock to prevent the bottleneck phenomenon.

Thus, the pipeline clock period is determined by the stage having the longest delay time among the respective stages, and is expressed by the following equation.

&Quot; (2) "

In the above equation Respectively, Lt; / RTI > Is the delay time of each interface latch, the sum of the longest stage delay time and the delay time of the interface latch Is determined as a clock period of the pipeline, and each interface latch is connected to a clock cycle It is synchronized.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiment applied to the present invention corresponds to a case where the macroblock size is 16 × 16 (horizontal pixel number × vertical pixel number).

4 is a block diagram showing an adder structure according to FIG. 3 using a Wallace tree in a motion estimator, FIG. 5 is a diagram illustrating a difference ≪ / RTI >

Referring to FIG. 3, the pipelined architecture of the present invention comprises eight stages of processing stages (S1 through S8) and latches (LATCHs) for temporarily storing intermediate results between stages.

Here, the first to sixth latches LATCH1 to LATCH6 operate in synchronization with a pipeline clock cycle (hereinafter, referred to as 'first clock') as in the above equation, and the seventh to ninth latches LATCH7 to LATCH9, Is synchronized with a clock cycle (hereinafter referred to as a 'second clock') corresponding to four times the clock period.

Next, FIG. 4 is a detailed block diagram of FIG. 3, wherein each stage of FIG. 3 is composed of a plurality of adders and registers including a Wallace adder.

As shown in FIG. 4, the pipeline adder structure includes a first wall addition unit 40, a second wall addition unit 41, a third wall addition unit 42, a fourth wall addition unit 43, The first to ninth latches L1 to L9, the counter (not shown in the figure), the fifth wall addition unit 44, the sixth wallis addition unit 45, the seventh wallis addition unit 46, the merge addition unit 47, Not shown).

The first walley adder 40 is composed of 16 4-input, 2-output adders having a Wallace tree structure for receiving 4 data and outputting 2 data. A first adder 40-1 for processing one row of data (16) for four cycles, and a second to a sixteenth adders 40-2 to 40- 16).

The second walley adder 41 is composed of eight 4-input, two-output adders. The outputs of the first and second adders 40-1 and 40-2 of the first walley adder 40 are input A second adder 41-2 receiving the outputs of the third and fourth adders 40-3 and 40-4 of the second wally adder 40, And third to eighth adders 41-3 to 41-8 that receive the output of the Wallace adder.

The third walley adder 42 is composed of four 4-input, two-output adders. The third and fourth adders 41-1 and 41-2 of the second walley adder 41 input A second adder 42-2 receiving the outputs of the third and fourth adders 41-3 and 41-4 and an adder 41-5 of the remaining second wall adder 42-1, And fourth to fourth adders 42-3 to 42-4 that receive the outputs of the first to fourth adders 42-1 to 42-8.

The fourth walley adder 43 is composed of two 4-input, two-output adders. The fourth and sixth adders 42-1 and 42-2 of the third walley adder 42 input And a second adder 43-2 receiving the outputs of the first adder 43-1 and the adders 42-3 and 42-4 of the third wavelet adder.

The fifth walley adder 44 is composed of one 4-input, two-output adder and outputs the outputs of the first and second adders 43-1 and 43-2 of the fourth walley adder 43 And an adder 44 for receiving.

The sixth walith adder 45 is composed of two 4-input, 2-output adders and 8 shift registers. The 4th input and the 2-output of the fifth Walsh adder 44 are input for 4 clocks, A shift register 45-1 for latching and storing data, a first adder 45-2 for receiving and adding the four data stored in the shift register 45-1, and the other four And a second adder 45-3 for receiving and adding data.

The seventh Walris adder 46 is composed of one 4-input, two-output adder. The outputs of the first and second adders 45-2 to 45-3 of the sixth walley adder 45 are And an adder 46 for receiving and outputting two data.

The merge adder 47 is composed of a merge adder for summing the two data output from the seventh wavelet adder 46 to obtain a final absolute error value MAE. The merge adder may be implemented using a carry select adder (CSA), a carry lookahead adder (CLA), or the like.

The first to sixth latches L1 to L6 must latch the data output from the first to fifth wallis adders 40 to 44 every cycle, so that they are synchronized with the first clock (clock frequency) f And the shift register is also operated in synchronization with the first clock.

Since the seventh to ninth latches L7 to L9 perform the addition operation after four pairs (eight data) of data effective in the shift register of the sixth wallis adder 45 are filled, (L7 to L9) has a second clock (clock frequency; .

At this time, the second clock COUNT_LATCH is generated every fourth clock using a counter for counting the first clock (CLOCK_LATCH) cycle.

Next, the operation of the adder having the pipeline structure constructed as shown in FIG. 4 will be described in detail with reference to FIG.

The 16 × 16 matrix shown in step 1 shown in FIG. 5 is the input data of the first wallis adder 40.

During one clock cycle, four pieces of data corresponding to the vertical 1 column are output as two pieces of data through the first adder, four pieces of data corresponding to the two columns are outputted as two pieces of data through the second adder, Four pieces of data are output as two pieces of data.

That is, in the 16 four-input, two-output adders of the first wallis adder, the A1 group (4 x 16 data) is input during the first cycle, the A2 group is input during the second cycle, the A3 group during the third cycle, As the groups are input in sequence, all the input data is processed for a total of 4 cycles and the intermediate result data is aligned as shown in the 16x8 matrix of step 2. [

The 16 × 8 matrix shown in step 2 is input to the first and second adders 40-1 and 40-2 of the first wallis adder 40 for one cycle as input data to the second wallis adder 41, 2 are input to the first adder 41-1 of the second wallis adder 41 and the output of the remaining first wallis adder 40 is also input to the second wallis adder 41 41) of the adders 41-2 to 41-8.

That is, during the first cycle, four out of the group B1 (2 × 16 intermediate result data processed by the group A1) are added through the adder and output as two data, and during the second cycle, the group B2 Group B3 (intermediate result data in which A3 is processed) during the third cycle, and group B4 (intermediate result data in which the group A4 is processed during the fourth cycle) are processed. If all the intermediate result data (16x8) are processed through the second wallis adder 41 and the intermediate result data is aligned for a total of four cycles, the result is displayed as an 8x8 matrix in step 3. [

Subsequently, in step 3, step 4, and step 5, all the intermediate result data of the previous step are processed for four cycles in units of four groups as in step 1 and step 2.

In other words, during the four cycles, the 8 × 8 matrix shown in the step 3 is output to the 4 × 8 matrix through the third wallis adder 42, and the 4 × 8 matrix shown in the step 4 is output to the fourth wallis adder 43 in the 2x8 matrix, and the 2x8 matrix shown in the step 5 is output to the 4x2 matrix through the fifth wallis adder 44. [

In the operations performed in the steps 1 to 5 described above, all the data to be processed in each step are divided into four groups, one group is processed for one cycle, and all the data are processed in four cycles, It can be seen that the hardware consumed by each module in the line has been reduced by a factor of four.

Hereinafter, a process of processing the output data after performing the step 5 will be described.

The 2x4 matrix shown in step 6 is input to the sixth wally adder 45 as two data output from the fifth wally adder 44 according to the first clock CLOCK_LATCH, Corresponds to the data latched by the latch 45-1.

That is, the data outputted for the fourth cycle from the fifth wallis adder 44 corresponds to the stored arrangement of the shift register, and when the eight valid data in the shift register 45-1 are filled, 1 adder 45-2 and the remaining four data are input to the second adder 45-3 and output as a 2x2 matrix.

At this time, the seventh latch L7 for latching the output of the sixth wallis adder 45 must be synchronized to the second clock COUNT_LATCH so as to perform an operation every four cycles by a counter.

The 2x2 matrix shown in step 7 is the input data of the seventh wallis adder 46 and the four data output from the sixth walith adder 45 are added and output as two data.

Finally, the 1x2 matrix shown in step 8 is added through the merge adder 47 to obtain the final absolute error value MAE.

Here, the eighth latch L8 for latching the output of the seventh wallis adder 46 and the ninth latch L9 for latching the output of the merge adder 47 are also similar to the seventh latch L7 And is synchronized with the second clock COUNT_LATCH generated by the counter. However, since the ninth latch latches the final result value of the last stage, it is not necessary to synchronize to the second clock COUNT_LATCH.

The pipeline operation of the adder described above is shown in Table 1 below.

T = 1 / f S1 S2 S3 S4 S5 S6 S7 S8 T0 M1, A1 T1 M1, A2 M1, B1 T2 M1, A3 M1, B2 M1, C1 T3 M1, A4 M1, B3 M1, C2 M1, D1 T4 M2, A1 M1, B4 M1, C3 M1, D2 M1, E1 T5 M2, A2 M2, B1 M1, C4 M1, D3 M1, E2 T6 M2, A3 M2, B2 M2, C1 M1, D4 M1, E3 T7 M2, A4 M2, B3 M2, C2 M2, D1 M1, E4 T8 M3, A1 M2, B4 M2, C3 M2, D2 M2, E1 M1, F1 T9 M3, A2 M3, B1 M2, C4 M2, D3 M2, E2 T10 M3, A3 M3, B2 M3, C1 M2, D4 M2, E3 T11 M3, A4 M3, B3 M3, C2 M3, D1 M2, E4 T12 M4, A1 M3, B4 M3, C3 M3, D2 M3, E1 M2, F1 M1, G1

T13 M4, A2 M4, B1 M3, C4 M3, D3 M3, E2 T14 M4, A3 M4, B2 M4, C1 M3, D4 M3, E3 T15 M4, A4 M4, B3 M4, C2 M4, D1 M3, E4 T16 M5, A1 M4, B4 M4, C3 M4, D2 M4, E1 M3, F1 M2, G1 M1, H1 T17 M5, A2 M5, B1 M4, C4 M4, D3 M4, E2 T18 M5, A3 M5, B2 M5, C1 M4, D4 M4, E3 T19 M5, A4 M5, B3 M5, C2 M5, D1 M4, E4 T20 M6, A1 M5, B4 M5, C3 M5, D2 M5, D1 M4, F1 M3, G1 M2, H1

In Table 1, T is a first clock (CLOCK_LATCH) period, S _i is a pipeline stage, M is a macroblock index, and A, B, C, D, E, F, G, It is a group of data processed in each stage.

As shown in the table, in stage 1, all the data 4 groups A1, A2, A3, and A4 of the M1 macro block are sequentially processed during the T0 to T3 clocks, and then the next new macroblock is input and processed.

The cycle required for calculating the absolute error value by summing all the data of the M1 macroblock takes at least 16 cycles, and the absolute error value of the next macroblock is calculated and output every four cycles thereafter.

To illustrate the concrete operation of the Wallace addition unit, a 4-input, 2-output Wallace tree is shown.

FIG. 6 is a bitmap diagram for explaining a Wallace tree operation for reducing four data into two data, and FIG. 7 is a detailed configuration diagram illustrating a detailed structure of a 4-input, 2-output adder implemented by a pre- .

Referring to FIG. 7, in the Willis tree, four data are received, and the bits at the same position are grouped and added to generate sum and carry (CARRY), and bits corresponding to the generated thumb and bits corresponding to the carry Are regarded as one data, and two data are output. Therefore, carry propagation is prevented from occurring.

That is, the four data (or pixels) a, b, c, and d are made up of 8 bits, and the same bit positions are added together. The bits a, b, and c are grouped into three groups. As a result, the sum SUM of each group becomes the same bit position, and the carry CARRY becomes the weight corresponding to the upper 1-bit position, so that the bits of the same weight as each of the bits of the remaining d are added again by three groups. As a result, the sum SUM of each group is the same bit position, and the carry (CARRY) is a weight corresponding to the upper one bit position, so that two data e and f form a pair of Willis trees.

At this time, up to the 9 bits of the output two data e and f are generated, but since the difference values between the pixels of the original reference block and the candidate block are added up, the two data added here are not so large, (Carrie), even if you do not take into account the results.

As described above, according to the present invention, the addition method for obtaining the absolute error value at the time of motion estimation can be performed in a parallel high-speed processing by the pipeline processing using the Wallace tree, the number of hardware (Wallace tree) is reduced, Since the interconnection is simplified, chip area and cost are reduced in VLSI fabrication.

Claims (14)

A method for adding pixel values of a matrix (the number of horizontal pixels x the number of vertical pixels) using a Wallace tree structure, Each pixel value of the matrix (the number of horizontal pixels x the number of vertical pixels) A first step (step 1) of calculating by a matrix; In the first step (step 1) The addition is performed on the matrix A second step (step 2) of calculating a matrix; In the second step (step 2) Is added to the matrix A third step (step 3) of calculating a matrix; In the third step (step 3) By adding the matrix A fourth step (step 4) of calculating a matrix; In the fourth step (step 4) By adding the matrix A fifth step (step 5) of calculating a matrix; In the fifth step (step 5) By adding the matrix A sixth step (step 6) of calculating a matrix; In the sixth step (step 6) Matrix Added A seventh step (step 7) of calculating a matrix; And In the seventh step And an eighth step (step 8) of adding a matrix to obtain a final value (MAE). In a pipeline adder structure for adding distortion values of blocks in a motion estimator using a Wallace tree structure, The difference value is added A first wallis adder 40 for outputting data; And outputs it to the first wallis adder 40 The addition is performed on the data A second wallis adder 41 for outputting data; And outputs it to the second wallis adder 41 The data is added A third wallis adder 42 for outputting data; The third wallis signal output from the third wallis adder 42 The data is added A fourth wallis adder 43 for outputting data; The fourth wallis signal outputted from the fourth wallis adder 43 The data is added A fifth wallis adder 44 for outputting data; The fifth wallis adder 44 outputs the fifth The data is added A sixth wallis adder 45 for outputting data; The sixth wallis adder 45 outputs the The data is added A seventh wallis adder 46 for outputting data; And The seventh wallis adder 46 outputs the seventh And a merge adder (560) for adding the data and outputting a final value (MAE). 3. The semiconductor memory device according to claim 2, further comprising a first latch and a ninth latch for temporarily storing intermediate results between the input end and the output end of the first to seventh adders (40 to 46) and the merge adder (47) (L1 to L9) are additionally provided to the absolute error value adder structure of the motion estimator. 4. The semiconductor memory device according to claim 3, wherein the first to sixth latches (L1 to L6) And the seventh to the ninth latches L7 to L9 operate in synchronization with the first clock CLOCK_LATCH corresponding to the clock frequency And a second clock (COUNT_LATCH) corresponding to the first clock (COUNT_LATCH). 4. The absolute error value adder structure of claim 3, wherein the ninth latch (L9) operates in synchronization with the first clock. 5. The absolute error value adder of claim 4, wherein a counter for counting the first clock (CLOCK_LATCH) and generating a second clock (COUNT_LATCH) is added every fourth clock cycle. The apparatus according to claim 2, wherein the first to seventh adders (40 to 46) comprise a plurality of 4-input, 2-output adders to which a Wallace tree for receiving and adding 4 data and outputting 2 data is applied The absolute error value adder structure of the motion estimator. 3. The apparatus of claim 2, wherein the first wallis adder (40) comprises: a first adder (40-1) for receiving four of vertical 1 column data every cycle and processing one row of data (16) for 4 cycles; And And a second to a sixteenth adders (40-2 to 40-16) for inputting four data for the remaining vertical columns and processing one column of data. 3. The apparatus according to claim 2, wherein the second wally adder (41) comprises a first adder (41) for receiving the outputs of the first and second adders (40-1 and 40-2) -1); A second adder 41-2 receiving the outputs of the third and fourth adders 40-3 and 40-4 of the first wallis adder 40; And And the third to eighth adders (41-3 to 41-8) receiving the outputs of the remaining first wallis adder (40). 3. The apparatus according to claim 2, wherein the third wallis adder (42) comprises a first adder (42) for receiving the outputs of the first and second adders (41-1, 41-2) -1); A second adder 42-2 receiving the outputs of the third and fourth adders 41-3 and 41-4; And And the third to fourth adders (42-3 to 42-4) receiving the output of the remaining second wavelet adder (41). 3. The apparatus according to claim 2, wherein the fourth wallis adder (43) comprises a first adder (43) for receiving the outputs of the first and second adders (42-1 and 42-2) of the third wallis adder -One); And And a second adder (43-2) receiving the outputs of the adders (42-3 and 42-4) of the third wavelet adder (42). 3. The apparatus according to claim 2, wherein the fifth wallis adder (44) comprises an adder (44) receiving the outputs of the first and second adders (43-1, 43-2) of the fourth wallis adder And an absolute error value adder structure for a motion estimator. 3. The apparatus according to claim 2, wherein the sixth wallis adder (45) comprises: a shift register (45-1) for receiving and shifting two outputs of the fifth wallis adder (44) ; A first adder 45-2 for receiving and adding the four data stored in the shift register 45-1; And And a second adder (45-3) for receiving and adding the other four data stored in the shift register (54-1). 3. The apparatus according to claim 2, wherein the seventh wallis adder (46) receives and adds four outputs of the first and second adders (45-2 to 45-3) of the sixth wallis adder (45) And an adder (46) for outputting the data as two data.