KR19980052162A - PLC instruction high speed processing system - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a logic processor for instruction processing, which is applied to PSI, which is an industrial controller. In particular, the instruction analysis is executed in a hardware logic calculator of a small, lightweight, and low-consumption strategy composed of an on-demand semiconductor gate array chip. The present invention relates to a PSI instruction high-speed processing system that can reduce and achieve high-speed processing of instructions.

A feature of the present invention is to design a hardware logic operator 10 composed of a data address register 13, a processor 11, and an interface block as a single-chip on-demand semiconductor for one-bit data processing, and the interface block 15 The control signal, data signal, and address signal of the CPU 16 are provided to the processor 11 through the processor 11, and the instruction memory 12 is connected to the processor 11, thereby providing a 5-bit opcode and 14 bits. And operand instructions, and the processor 11 is connected to the data memory 14 so that 8-bit data exchange can be performed. It is to improve the instruction processing speed.

Description

PLC instruction high speed processing system

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a logic processor for instruction processing applied to PSI, an industrial controller. In particular, CPU instruction is a burden by allowing instruction interpretation to be executed in a small, lightweight, and low power hardware logic calculator composed of a custom semiconductor gate array chip. The present invention relates to a PSI instruction fast processing system which can reduce the number of instructions to achieve high speed processing.

Prior art in the basic instruction high-speed processing system of PIEL has been presented in Japanese Patent Application Laid-Open No. 92-004937.

It includes the FPGA (Field Programming Gate Array) and the existing technology, which consists of a timing generator, a program counter, a microcomputer, a memory, a hardware logic controller, a read / write signal generator, a code latch, and a shift register. General logic circuits are used to construct or process software instructions. Specifically, the timing generator generates clock pulses in synchronization with an external clock pulse and a control signal of a microcomputer, a program counter for generating an address for reading program data, and an address from the program counter. The microcomputer and program counter that controls the entire system outputs the data desired by the user, and stores the data, a code latch unit for latching the read data and generating an address accordingly, and address timing of the code latch unit. The hardware logic control unit performs basic instructions with data output from the memory unit by the negative clock pulse, and the hardware logic by the clock pulses of the read / write signal generator and the timing generator that read the basic command codes of the memory unit and process the corresponding information. Output of control It consists of a shift register processing unit which temporarily stores data. In addition, the hardware logic controller inverts the logic code that logically computes the output data of the memory unit and the shift register processing unit by the designation of the code latch unit and the instruction code discrimination signal of the code latch unit through the inverter, and the clock signal and the NAND of the timing generator unit are inverted. Master control set signals and readouts of NAND gates, OA gates, and microcomputers that output the output signals of the multiplexer to select the output signal of the logic operator according to the NAND gate, the output signal of the NAND gate, and the instruction code signal of the code latch unit. And a high speed processing system for PLC basic instructions as an AND gate for outputting each instruction by ANDing the outputs of the controller and the OR gate by the recording signal of the recording / recording signal generator. have.

In the prior art of such a configuration, the actual instructions are interpreted by the microcomputer, not by the processor itself, and the hardware is configured by using the shift register for bit operation. In this case, a general logic element is used to expand the size area. And big power consumption problems have appeared, and also problems in terms of instruction processing speed and reliability of processing results are exposed.

An object of the present invention is to construct a logic processing unit for the instruction processing applied to the industrial controller PSI as a single-chip on-demand semiconductor gate array so that the main instructions are processed in hardware here, while at the same time reducing the operation unit of the main CPU It is to provide a PSI instruction high speed processing system that can achieve small size, light weight, low power consumption and high data processing speed.

A feature of the present invention is to design a hardware logic operator consisting of a data address register and a processor and an interface block as a single-chip on-demand semiconductor that performs one-bit data processing. A signal and an address signal are connected to each other, and an instruction memory is connected to the processor, and the 5-bit opcode and a 14-bit operand instruction are connected. The processor is connected to a data memory to perform 8-bit data exchange. By using hardware logical processing of frequently used instructions, the burden on the main processor is ultimately improved.

1 is a block diagram of a CPU CPU board of the present invention system.

2 is a block diagram of a hardware logic calculator of the system of the present invention.

3 is a block diagram of a processor of the system of the present invention.

4 is a structural diagram of a control register and a state register of the system of the present invention.

Explanation of symbols on the main parts of the drawings

10: hardware logic operator 11: processor

12: instruction memory 13: data address register

14: data memory 15: interface block

16: CPU17: data selector

18: control unit 19: data register

20: control register

Hereinafter, the present invention will be described with reference to the accompanying drawings. 1 is a block diagram of a CPU CPU board according to an embodiment of the present invention, in which a hardware chip 10 comprising a data address register 13, a processor 11, and an interface block is a single-chip data processing operation. Designed as a custom semiconductor, the interface block 15 is connected to the processor 11 to provide a control signal, a data signal, and an address signal of the CPU 16, and the processor 11 has an instruction memory 12 ) Is composed of a 5-bit opcode and a 14-bit operand instruction.

In the embodiment of the present invention, the hardware logic operator (HLC) 10 performs a hardware logic operation on 21 types of instructions with a high frequency of use among a total of 144 types of instructions.

Table 1 below shows these 21 kinds of sequence instructions.

TABLE 1

These instructions are processed through a three-stage pipeline of recognition, interpretation, and execution.

To explain this, the program downloaded from the upper level is stored in the instruction memory 12. The instruction is a hardware logic operation instruction, the CPU 16 passes the start command to the block 15 through the control register 20 to the interface of the HLS 10, and the interface block 15 interprets the control to control the instruction. The response signal is transmitted to the CPU 16. The processor 11 clears the instruction pointer (Instruction Pointer IP) before outputting the instruction, and outputs the chip enable and read signals of the instruction memory 12. After the opcodes and operands of the instructions are fetched from the instruction memory, instruction processing is performed along the pipeline. The instruction patch step reads execution instructions from instruction memory, and instruction patch addresses are generated by instruction pointers, which have the function of program counters.

It is incremented by 1 according to the instruction pointer clock that is cleared to 0 at the hardware logic initialization stage, and becomes the instruction pointer value of the next instruction. When BIT command is executed, IP stops and the counter progresses when HLS command is met again. The IP output is used as an address in the instruction memory and the opcode of the instruction having the selected address value is patched and stored in the instruction register of the processor block. At the same time, it is stored in the operand data address register 13 of the instruction and used as the address of the operand required for the execution of the instruction. The output of the instruction register is passed to the instruction interpreter, and the output of the data address register 13 patches the operand in a period in which the output of the instruction register is interpreted. The instruction interpretation step interprets the fetched instructions to generate internal control codes required by the instruction processor, and simultaneously accesses the data memory with the operands stored in the data address register 13 to data bits required for the data in register. Save it. The interpreted instruction code is output and stored in the function register (Function Resister (FR)).

As shown in FIG. 1, the CPU is composed of the CPU 16 of the Intel80186, the hardware logical operator 10, and the memories. The program compiled by the programmer into a ladder or a list includes a hardware logic operation instruction and a BTI. Because it is composed of instruction mixed, the interface between HLS block and CPU block is important in instruction processing. It sends and receives signals using start / stop signals and data of control register. The processor block receives control signals, opcodes, operands, and data from the interface block, fetches, interprets, and executes each instruction through a pipeline to store or output a result. The data memory is shared by the CPU and the HLS, and the control signals of the instruction memory and the data memory are made by the HLS. The instruction structure consists of a 5-bit opcode and a 14-bit operand. The data is processed in 1-bit operation.

The HLS custom semiconductor chip is composed of a processor and an interface block as shown in FIG. 1, and the processor block is designed as a VHDL instruction control interpreter, a central logic operator, a master instruction controller, a stop controller, a stack instruction interpreter, and a storage controller. The data address register block allows to determine the address of the external data memory. The instruction input unit is a block that receives the opcodes, operands and data of the instructions from the instruction memory and data memory and fetches them into the instruction register and the register which is the data, respectively.

FIG. 2 is an interface block, which receives control signals from the CPU 16 to issue control commands such as processor enable, write, and read, and transfers data to 8/16 bits because the HLS uses 8 bits. When the register 20 receives data from the CPU 16, the 16-bit data is divided into 8 bits and 8 bits by using the LDS signal to the HLS. The controller 18 of the interface block receives an input signal from the CPU 16 and generates a control signal such as a data memory control signal, an instruction memory control signal, an HLS processor control signal, and the like. The control register 20 receives an HLS start / stop command from the CPU's control register and transmits the HLS command to the HLS, and sends the current state of the HLS to the CPU. The data register 19 transfers data between the data memory 14 and the processor 11, and the data selector 17 selects desired data information when transferring data from the processor 11 to the CPU 16. Pass in bits. The output unit 15 is a block for transmitting 16-bit data to the CPU 16 and may also receive an opcode from the data memory.

FIG. 3 is a block diagram of a processor, wherein an instruction analyzer includes a master instruction controller (MR_CTR) 24, an instruction analysis controller (DEC_CTL) 25, a stack instruction analyzer (DEC, STK) 26, and a logic operator 35. The master command control unit is a block that interprets MCS and MCR commands.

The DEC CTL block 25 distinguishes whether or not to interpret the input command, and the BTI command or the END command is input, and stops the HLS command. The PLS, PLF, SET, RST, and OUT commands, unlike other commands, It saves the value for a certain period of time and stops the HLS operation state for a certain time through the storage controller when a command is input. It is also used when it is necessary to reset or jump the IP 22. The BTI instruction is defined as opcode 18, and when this value is input via IR 32, it stops operating the HLS and counts the IP value. Each output value is finally passed to the state controller to control the state of the HLS.

The DEC_STK block is a block for interpreting LD, LDI, BRB, BRM, BRT, ANB, and ORB instructions. The DEC_STK block stores data in the stack A and the stack B in which the instruction is inputted so that the branch-connected instruction operates under one condition. It is required to execute several instructions under the same input condition.In case of LD, LDI, ANB, ORB instruction, the result of logical operation unit is stored in stack A (33), and BRB, BRM, BRT instruction is stored in stack B (34). Will be saved.

The staff of DEC_STK consists of 8 steps and can use up to 8 branches when arranging branches.

The logic operator 35 is a block that receives the result interpreted by the instruction interpreter and the opcode of each instruction stored in the FR and logically operates the instruction to store the result in the NR and the stack. The design was designed by circuit synthesis using VHDL.

In addition, the instruction execution unit of the processor block of FIG. 3 includes a node register 36, a stack unit 33, 34, a stop control block (SCB) 31, a storage control unit, and an operation state control unit. This includes the ability to give the interpreted output to each corresponding register or to store data on the stack. The result calculated in the logical operation unit is stored in NR or 2 stacks according to the type of each instruction. In particular, at the time of the output command, it is stored in the data memory 14 to complete execution. All instruction execution stages go through successive phases until an end instruction or BTI instruction is met, and the operation state controller generates each phase. For example, when a block command is input, the storage control unit receives a status stop signal (phold) to generate a stop signal (halt) to stop the HLS processor and to operate the CPU through an interface block. The node register (NR) 36 stores all operation result values and is stored on the stack or transferred to the data memory 14, and only the SET and RST instructions output the result without NR. The 0 bit of the control register can also be used to force a specific value. The HLS processor has three stacks (stack A, stack B and master stack). Stack A 33 stores and outputs the results of the LD, LDI, ANB, and ORB instructions, and stack B 34 processes the BRT, BRB, and BRM instructions. The master stack (MR_STACK) 29 stores the master command result. Stacks A and B consist of unit stacks, and the master stack consists of four unit stacks.

The stop control unit 31 of the processor block receives an input of the control register 21 and transmits a stop signal to the state control block of the HLS, or stops the HLS when a BTI command is input. Bit function of the control register is shown in FIG. When operating the HLS through the CPU control register, the control register passes 18 to the HLS to clear the HLS, and then sends 80 to the HLS START state. When the operation of the HLS is completed, the operating state of the HLS is transmitted to the CPU through the sixth bit of the control register. This allowed it to operate in synchronization with a clock of 4MHz.

The storage control unit STO_CTL of the processor block operates by receiving a signal as a result of interpreting an output command from DEC_CTL. When the storage signal STORE is input, a phase hold is output during the scan time, and a data memory write is performed. Sending a signal stores the result of the operation in the data memory. HLS has three phases according to a three-stage pipeline algorithm. phold0 is the step of patching the opcode to the IR, the operand and data to the DM, and transferred to phold1 when the next clock is input.

In this step, the instruction is interpreted and the data and the interpreted value are transferred to the logic operation unit and stored in the FR. The last clock is stored in the NR or stack at phold2. When the output command is input, the storage controller may store the result value in the DM. When the end instruction or the BTI instruction is input, the stop controller outputs a stop signal (halt) to stop the HLS and operate the CPU.

EXAMPLE

The HLS custom semiconductor chip was designed in a 1.2μ CMOS gate array to fabricate the chip. The design was divided into pre-stage design and post-stage design, and the circuit verification was performed by circuit design and simulation for each detailed block. The manufactured HLS custom semiconductor chip is mounted on POSFA-3A PLC system manufactured by POSCON Co., Ltd. and operated by using the program to check the execution of HLS command. Then, the operation waveform is extracted by the logic analyzer and the simulation result waveform and Compared.

As a result, the CPU initialized the HLS IP through the control register (DB7: 0) and passed the start bit to deliver the HLS start command. The IP value was counted as the LD instruction was patched to IR by receiving the opcode and operand of the instruction from the instruction memory. When an end instruction is entered to end program execution, the SCB stops HLS operation and the status register informs the HLS stop status. The CPU reads the HLS status register and takes over the initiative from the HLS and starts operation.

If there is a BTI instruction in the program, the HLS also halts and sets the stop bit by the BTI instruction in the status register, allowing the HLS operation stop and the CPU to start operation.

For example, in the case of the PLC CPU using the Intel 80186, when the HLS custom semiconductor chip is additionally installed, the instruction processing time was reduced to 250 μsec, which was several μsec when the CPU processed, and the CPU processing burden was reduced.

As described above, the present invention configures an instruction processing step into a pipeline of three stages so that the instruction recognition, interpretation, and execution proceed simultaneously on one clock, and the instruction consists of a 5-bit opcode and a 14-bit operand. By designing a circuit that processes 1 bit operation as a custom-made semiconductor circuit and embedding it in one chip, it has a structure that has high instruction processing speed and easy to design by adding functions desired by the user. Among them, 21 kinds of instructions, which are most frequently used, are processed by the hardware logic operator to reduce the burden on the main processor, thereby increasing the instruction processing speed.

In particular, since the hardware logic calculator of the system of the present invention is made of a single-chip custom semiconductor circuit, low power consumption and size reduction effect can be obtained.

Claims (1)

In the apparatus for improving the processing speed of the PID instruction for controlling the industrial equipment, the interface block 15 for the control signal and data interface with the CPU 16 of the PI, and the control signal, opi from the interface block A processor 11 for receiving code, operands and data, fetching, interpreting, and executing each instruction through a pipeline, and storing and outputting the result; and a data address register 13 for storing the operand of the instruction. The hardware logic operator 10 is designed as a single custom semiconductor chip, and the processor 11 is connected to the instruction memory 12 so as to exchange 5-bit opcodes and 14-bit operand instructions. (11) connects and configures the data memory (14), which is the main program of the PID through the hardware operation processing of frequently used instructions. Reduce the burden of standing Piel during high-speed instruction processing system which comprises improving instruction throughput.