KR19980048201A - Adaptive Switch Pullup Control Circuit - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Adaptive switch pull-up control circuit for operating the bit line pull-up transistor at high speed.

2. The technical problem to be solved by the invention

In the lead cycle, the pull-up control is changed to obtain a large bit line voltage difference, so that the sensing margin of the sense amplifier with a large voltage gain is secured. In the write cycle, the pull-up transistor is turned on with the lead-pull-bar signal soon after the word line is turned off, thereby recovering characteristics. To make things better.

3. Summary of Solution to Invention

In a semiconductor memory circuit having a bit line pull-up transistor,

Pwl means for turning on wordlines by pulses of constant width to have pull-up control pulse widths that adaptively act on the read / write cycles respectively; And the pulse detection logic of the sense amplifier and sense amplifier outputs.

4. Important uses of the invention

Fast pullup scheme for highly integrated memory devices.

Description

Adaptive Switch Pullup Control Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory integrated circuits, and more particularly, to a static random access memory (SRAM) circuit having an adaptive switch pull-up control circuit for operating a bit line pull-up transistor at high speed.

In general, as a semiconductor memory device, SRAM has a lower memory capacity than DRAM (Dynamic Random Access Memory), but is widely used in the medium and small memory fields because of its high speed and ease of use. In addition, as the integration of SRAM devices increases, the supply voltage is also decreasing. Therefore, the operating limit of the SRAM at low voltage is also an important characteristic item of the SRAM device.

1 is a circuit diagram showing the core structure of a typical four transistor cell SRAM.

As shown in FIG. 1, the core structure of a general four transistor cell SRAM includes a bit line 30 and 32 running on a cell and a cell array including two transfer transistors 20 and 22 and two load transistors 24 and 26. And Y-transfer gates 40 and 42 and pull-up transistors 50 and 52. Each cell is selected by a word line 60 and a Y-select gate 62. The eq signal 70 or the rd_pullupb signal 72 turns on the PMOS (80, 82, 84, 50, 52) transistors during equalizer or precharge operation to turn on the bit line and bit line bar (30, 32). Equalize or precharge. The PMOS transistors 50 and 52, which are opened and closed by the rd_pullupb signal 72, are usually turned on in a 5V operating device or turned on only during a read operation to control bit line sensing. However, in SRAM devices that are becoming increasingly integrated and low voltage, more consideration should be given to construct an optimal pull-up transistor scheme. This is because the core pullup structure is most important in order to secure the bit line parasitic loading problem of the highly integrated device and the stability of the chip operation.

FIG. 2 is a circuit diagram illustrating conventional pull-up control logic for controlling the pull-up transistor of FIG. 1. In the conventional logic, the rd-pullupb signal becomes high only when the web signal of the WE_BUFFER of the selected column is low, that is, in the write cycle, to turn off the pull-up transistors 50 and 52. The bit lines of the other states and unselected columns are logic to precharge to Vcc. The word line signal pwl signal of FIG. 2 is a structure in which the word line is turned on by a pulse of a constant width to implement a low static current.

Referring to the timing diagram of FIG. 3, rd_pullupb is always low in the read cycle to turn on the PMOS transistors 50 and 52, which is very useful for charging a bit / bitbar line with high parasitic capacitance to vcc. Large PMOS pullup transistors are needed. Further, by charging both bit lines, the difference bit line voltage (Δ bit voltage) is reduced to 923 mV. This is advantageous when the difference bit line voltage is large in terms of high gain sensing amplifiers, and a pull-up scheme that is always on in conventional reads is disadvantageous in this respect. And even if the word line signal pwl is turned off in the write cycle, rd-pullupb is always turned off by the web signal.

Accordingly, the technical problem of the present invention is to obtain a large bit line voltage difference by different pull-up control in the lead cycle, thereby securing a sensing margin of a sense amplifier with a large voltage gain, and leading the lead-pull-up bar after the word line is turned off in the write cycle. By turning on the pull-up transistor with a signal, it is to provide pull-up control logic to improve recovery characteristics.

1 is a circuit diagram showing a core structure of a typical four transistor cell SRAM.

2 is a circuit diagram illustrating conventional pull-up control logic for controlling the pull-up transistor of FIG.

3 is an operation timing diagram when using conventional pullup control logic.

4 is a circuit diagram showing logic for controlling a bit line pull-up transistor according to the present invention.

5 is an operation timing diagram of control logic in accordance with the present invention.

6 is a graph of a transient analysis simulation result of the control logic of the prior art and the control logic of the present invention.

7 is a graph showing a cell access transistor current simulation when using the control logic of the prior art and the control logic of the present invention.

* Explanation of symbols for the main parts of the drawings

101 ... pulse generator 103, 109 ... delay logic

105 ... sense amplifier 107 ... pulse detector

111 ... output path 121 ... Noah gate

According to the present invention for achieving the above object, in a semiconductor memory circuit having a bit line pull-up transistor, the word line is turned on by a pulse of a constant width so as to have a pull-up control pulse width that adaptively acts on the read / write cycles, respectively. pwl means; And the pulse detection logic of the sense amplifier and sense amplifier output.

The pwl means consists of a pulse generator and a delay logic.

The pulse detection logic of the sense amplifier output passes the sense amplifier output signal (so / sob) through a pulse detector configured with exclusive OR logic when the sense amplifier is operated by the pulse generator signal of the pwl means. Make

A signal having a constant pulse width generated by the pwl means is combined with a sense amplifier output detection signal to form a logic circuit.

When the sense amplifier output-detection signal is generated, the pull-up control logic reduces the pulse width of the signal having a constant pulse width by the sense amplifier output-detection signal to generate a read-pull bar signal.

The pullup control logic generates a sense amplifier output-detect signal only in the read cycle.

The pull-up control logic equalizes the sense amplifier output signal and the sense amplifier output bar signal in the write cycle so that the sense amplifier output-detection signal is not generated.

In the pull-up control logic, the unselected block blk or column ysel always precharges the read-pull-up bar signal low.

Accordingly, according to the present invention, the sensing speed can be improved by increasing the bit line voltage difference of the memory device having the full vcc sensing scheme, and the present invention provides a high-integrated memory because the random switching of the full four-up transistor has sufficient recovery margin. It can be adopted as a high speed pull-up scheme of the device.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

4 is a circuit diagram showing logic for controlling a bit line pull-up transistor according to the present invention.

The present invention obtains a large bit voltage difference by different pull-up control in the lead cycle, thereby securing a sensing margin of a sense amplifier with a large voltage gain, and turning on the PMOS with the rd-pullupb signal, which is a lead-pull-up signal soon after the word line is off in the write cycle. In this way, new pull-up control logic is constructed to improve recovery characteristics. First, the pwl schemes 101 and 103 were adopted as in the past, and in addition, the sense amplifier output pulse detection logics 105, 107, 109 and 111 were inserted. Here, the sense amplifier 105 is operated by the pse signal of the pulse generator 101 and passes the sense amplifier output signal so / sob through the pulse detector 107 composed of exclusive or logic. Create a so_detection signal that is a detection. The so / sob signals, the sense amplifier output signals, begin sensing, creating a so_detection signal that is high. Therefore, the logical sum of the block (blk) and the Y-path (ysel), the pwlb, and the so_dectection signals (121), to create the rd-pullupb control signal. 5 is a timing diagram of the control logic in accordance with the present invention.

6 is a graph of a transient analysis simulation result of the control logic of the prior art and the control logic of the present invention.

The rd-pullupb on-interval in the lead cycle is more freely adjustable than the on-hold state of normal control logic, increasing the sensing margin by increasing the bitline voltage to 1.499mV while the PMOS (50, 52) transistors are off. Can be. In the write cycle, the so_dectection signal is always low because so / sob equalizes to the same voltage. The pwlb signal was received to turn rd-pullupb off by the pwlb interval.

7 is a graph showing a cell access transistor current simulation when using the conventional pull-up control logic and the control logic of the present invention.

As the pull-up transistor of the control logic of the present invention is turned off, the current level flowing into the access transistor is shown to be low. This shows that the bit voltage difference increases as the amount of current change in a bit line with large parasitic bit line capacitance becomes larger (cdv / dt = di / dt).

Therefore, the control logic of the present invention can be employed as a pull-up scheme of a highly integrated high speed SRAM memory device, and is a control logic that operates with a variable switching time. As a result, a read operation margin can be secured compared to a conventional pull-up scheme, and sufficient recovery margin is provided during a write operation.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

Accordingly, according to the present invention, the sensing speed can be improved by increasing the bit line voltage difference of the memory device having the full vcc sensing scheme, and the present invention provides a sufficient recovery margin by arbitrarily switching the pull-up transistor. Can be adopted as a high speed pull-up scheme.

Claims (8)

In a semiconductor memory circuit having a bit line pull-up transistor, Pwl means for turning on wordlines by pulses of constant width to have pull-up control pulse widths that adaptively act on the read / write cycles respectively; And Adaptive switch pull-up control logic, including pulse detection logic on the sense amplifier and sense amplifier output. The method of claim 1, And said pwl means comprises a pulse generator and a delay logic. The method of claim 1, The pulse detection logic of the sense amplifier output passes the sense amplifier output signal (so / sob) through a pulse detector configured with exclusive OR logic when the sense amplifier is operated by the pulse generator signal of the pwl means. Adaptive switch pull-up control logic, characterized in that made. The method of claim 1, And a logic circuit comprising a signal having a constant pulse width generated by the pwl means in combination with a sense amplifier output detection signal. The method of claim 1, And the pull-up control logic generates a read-pull-up bar signal by reducing the pulse width of the signal having a constant pulse width by the sense amplifier output-detection signal when the sense amplifier output-detection signal is generated. The method of claim 1, And said pull-up control logic generates a sense amplifier output-detect signal only in a read cycle. The method of claim 1, And the pull-up control logic equalizes a sense amplifier output signal and a sense amplifier output bar signal in a write cycle so that a sense amplifier output-detection signal is not generated. The method of claim 1, The pull-up control logic of the adaptive switch pull-up control logic, characterized in that the non-selected block (blk) or column (ysel) is configured so that the read-pull-up bar signal is always low and precharged.