KR19980046376A - AU signal processing circuit and AU signal automatic recognition method - Google Patents

Abstract

In a synchronous transmission system such as a Broadband Didier Cross-Connect System (BDCS) and a Synchronous Add-Drop Multiplexer (ADM) device, the AU signal in the STM-N signal is either AU3, AU4, or AU4-4c, or a mixture of these. Even if the type of AU signal included in the received STM-N is changed, it is necessary to recognize and process the type of AU signal automatically without special control action even if the type of AU signal is changed automatically without special control action. Therefore, in the present invention, if the AU signal type is changed based on the AU3 signal processing, the circuit is changed to an automatic recognition AU4 or AU4-4c signal processing scheme so that the AU signal processing without interruption is performed without external control. In order to realize this, the automatic recognition circuit of the AU signal type, the AU pointer buffer, and the control circuit implementing the buffer control method according to the AU type are configured.

Description

AU signal processing circuit and AU signal automatic recognition method

The present invention relates to an AU signal processing circuit and a method for automatically recognizing an AU signal. More specifically, the present invention relates to an AU signal or an automatic recognition method when an AU signal type is changed based on the AU3 signal processing in an STM-N signal in a simultaneous transmission system. The present invention relates to an AU signal processing circuit and an automatic signal recognition method for processing an AU signal without interruption by changing a circuit to an AU4-4c signal processing system without any external control.

The AU signal processor that performs the AU signal frame alignment function in the STM-N signal in a synchronous transmission system such as a broadband circuit divider (BDCS) and a synchronous add-drop multiplexer (ADM) device, has an AU signal. The circuit is configured and processed according to the type, and the AU signal is processed according to the AU signal type through separate control. Therefore, when the AU signal type has a separate processing circuit for each AU signal type, There is a delay.

In the prior art, the AU signal processor configures and processes separate circuits according to the AU signal type to process the AU signal through separate control in an environment in which the AU signal type is frequently changed, that is, a line distribution device. Processing circuits must be configured separately for each signal type, and there is a problem in that a time delay occurs when the AU signal type transitions.

Accordingly, the present invention solves a buffer control method that automatically recognizes an AU signal type even when the AU signal type changes in the middle, and operates the AU pointer buffer according to the AU signal type with a common AU pointer buffer.

1 is an exemplary view to which the present invention is applied.

2 is an AU signal frame structure diagram.

3 is an AU signal processing circuit diagram of the present invention.

4 is a flow chart of automatic recognition of AU signal type according to the present invention.

5 is a diagram illustrating a buffer control method according to an AU signal type.

The present invention for achieving the above object is to process the AU signal in the STM-N signal in a simultaneous transmission system such as a Broadband Circuit Splitter (BDCS) and a Synchronous Add-Drop Multiplexer (ADM) device. In the AU signal processor, In the AU signal processing circuit included in the STM-N signal frame in the synchronous transmission equipment, an AU pointer analyzer for automatically recognizing the signal form when the received AU signal transitions, the recognition A plurality of AU pointer buffers configured to simultaneously operate for each group according to the AU signal type; One feature of the present invention is a pointer generator which controls to output AU signals stored in the plurality of pointer buffers.

Further, another feature of the present invention is that the first buffer of the plurality of pointer buffers stores data output from the pointer interpreter according to the first buffer control signal inputted therein, and according to the read timing inputted from the pointer generator. A buffer for outputting data and outputting the buffer status signal; A buffer control circuit is configured to receive each buffer status signal input from the first pointer buffer and the remaining pointer buffers, and output a buffer control signal for controlling the first pointer buffer and the remaining pointer buffers.

The remaining pointer buffers receive control signals output from the buffer control circuit and output the state signals of the corresponding pointer buffers.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is an exemplary view to which the present invention is applied.

The configuration is such that the STM-N signal receiving / demultiplexing unit 100 receiving and demultiplexing the STM-N signal, and the AU signal processor 200 in the synchronous transmission device of the present invention processes the STM-N signal and then internally It is applied to detect the AU signal multiplexed on the AU signal type automatically and to process the signal according to the AU signal type quickly.

2 is an AU signal frame structure.

As shown in FIG. 2, the AU signal frame includes an AU pointer 70 and an AU payload 80, the AU payload 80 is composed of VC3 data, and the AU pointer 70 is configured of VC3 data. It has address information. The classification of the AU signal type is divided into SS bit 85 and pointer word 90. SS bit 85 distinguishes only the difference between the synchronous transmission methods. If SS = 10, the synchronous transmission level is defined as an international standard in ITU-T. SDH method (that is, AU signal included) is defined, and SS = 0 indicates North American standard SONET method. Here, only the case where the SS bit is 10 will be described.

When the AU signal type is AU3, the AU pointer word 90 has valid values, respectively. In the case of AU4 and AU4-4c, only the word value of the first AU pointer position has a normal value and the remaining pointer word positions are 1001ss1111111111. (This is called the CONC state). Therefore, the received AU pointer word 90 is interpreted, and as shown in FIG. 4, all normal values are recognized as AU3 when the continuous three-frame NORM state is maintained, and only the first pointer word is three-frame continuous NORM state and the remaining two If the pointer word is three consecutive frames CONC state, it is recognized as AU4. If the first pointer word is three frames consecutive NORM state, and if the remaining 11 pointer words are three consecutive frames CONC state, it is recognized as AU4-4c.

3 is a configuration diagram of an AU signal processing circuit of the present invention.

As shown in FIG. 3, the pointer analyzer PI 210 performs the AU signal type recognition operation as described above, and transfers the result to each of the pointer buffers PB # 1 to PB # 12 220A to 220L. . The pointer buffers 220A to 220L operate based on the AU3 signal, and write the received VC3 data and the VC3 frame offset extracted from the pointer interpreter 210 into the buffer 221A according to the timing of the receive pointer interpreter 210. The written data is read and output in accordance with the read timing of the pointer generator PG 230.

Here, if the size of the pointer buffer 230 is 16 bytes based on AU3, 16 × 3 = 48 bytes are required for AU4, and the buffer size of AU4-4c requires 48 × 4 = 192 bytes. do. In the present invention, since these buffs operate based on the AU3 signal, the 16-byte pointer buffers 220 are operated separately.

If the reception AU signal type transitions from AU3 to AU4, the 16-byte buffer operates the same at the same timing, as if one 48-byte buffer is operating. To this end, the present invention configures a circuit according to the buffer control method as shown in FIG. Similarly, when the reception AU signal type is operated by AU4-4c, it is necessary to control the buffer as if the buffer having a size of 192 bytes is operated by one.

FIG. 5 is a method for allowing several buffers to operate as one buffer by the same control.

As elements necessary for the operation of the buffer, input data, a write clock and a write address for writing the data, output data, a read clock and a read address for reading the data are essential. In addition, the elements applied to the buffer include the buffer reset signals R1 to R12 (buffer control signals of each PB) for initializing the state of the buffers and the buffer status signals S1 to S12 for monitoring the buffer status to determine whether there is an abnormality. Buffer status signal).

Therefore, it is necessary to control the above elements in order to unify the operation of several buffers into one. That is, the write and read clocks, the address, the buffer reset signal, and the buffer status signal applied to the buffer must move in the same manner.

For this purpose, when operating with AU3, the buffer operates without any action. When operating with AU4, the elements applied to the first buffer, that is, the clock, address, and reset signals are equally applied to the remaining three buffers. At this time, four buffers are controlled based on the status signal monitored in the first buffer. Likewise, when operating with the AU4-4c signal, the elements applied to the first buffer, that is, the clock, address, and reset signals, are equally applied to the other 11 buffers. Apply.

In the AU signal processor which is mixed with the AU signal form through the present invention, it automatically recognizes the shape change without separate external control and processes the AU signal continuously without interruption, thereby forming a separate processing circuit according to the separate AU form. It is not necessary to minimize the time delay caused by the transition of the AU signal type.

An object of the present invention is to perform the AU signal frame alignment and AU signal switching in the synchronous transmission equipment that requires line division or insertion function of the AU signal unit or less signal branching and insertion function, when the AU signal type is received in transition, When the signal type is changed from AU3 to AU4 or AU4-4c, it is automatically recognized and all AU signal processing procedures can be automatically processed according to the AU signal type accordingly.

Claims (5)

In the AU signal processing circuit included in the STM-N signal frame in a synchronous transmission equipment, An AU pointer interpreter for automatically recognizing the signal type when the received AU signal type transitions; A plurality of AU pointer buffers controlling to simultaneously operate in groups corresponding to the recognized AU signal types; And a pointer generator for controlling to output AU signals stored in the plurality of pointer buffers. The method of claim 1, wherein the first buffer of the plurality of pointer buffers, A buffer for storing data output from the pointer analyzer according to the first buffer control signal inputted therein, and outputting the data according to a read timing inputted from the pointer generator, and outputting the buffer status signal; And a buffer control circuit which receives each buffer status signal input from the first pointer buffer and the remaining pointer buffers and outputs a buffer control signal for controlling the first pointer buffer and the remaining pointer buffers. The method of claim 2, wherein the remaining pointer buffer is And a control signal output from each of the buffer control circuits to output a state signal of a corresponding pointer buffer. The method of claim 1, wherein the pointer buffer is When the AU signal type received from the pointer interpreter is an AU3 signal, the three pointer buffers are controlled to operate separately, when the AU4 signal is controlled to simultaneously operate four buffers as one buffer, and when the AU4-4c signal, 12 buffers are controlled. AU signal processing circuit characterized in that the control to operate as one buffer. An AU signal recognition method of an AU signal processing circuit having a pointer analyzer for receiving an AU signal in an STM-N signal, When the received AU pointer word is interpreted and all have normal values and maintain three consecutive frames of NORM, it is recognized as an AU3 signal. If only the first printer word is in three consecutive NORM states and the other two pointer words are in three consecutive CONC states, it is recognized as AU4. If only the first pointer word is 3 frames continuous NORM state and the remaining 11 pointer words 3 times continuous CONC state, it is recognized as AU4-4c.