KR19980045262A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- KR19980045262A KR19980045262A KR1019960063440A KR19960063440A KR19980045262A KR 19980045262 A KR19980045262 A KR 19980045262A KR 1019960063440 A KR1019960063440 A KR 1019960063440A KR 19960063440 A KR19960063440 A KR 19960063440A KR 19980045262 A KR19980045262 A KR 19980045262A
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- oxide film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 12
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
본 발명은 반도체장치 및 그의 제조방법에 관한 것으로서 반도체기판과, 상기 반도체기판 상의 소정 부분에 형성되어 활성영역을 한정하는 필드산화막과, 상기 반도체기판 내에 이 반도체기판과 반대 도전형의 불순물이 도핑되어 형성되며 채널영역을 한정하는 불순물영역과, 상기 반도체기판 상에 채널영역 보다 불순물영역 상에 두껍게 형성되어 단차를 갖는 게이트산화막과, 상기 게이트산화막 상에 양측 끝 부분이 이 게이트산화막의 두꺼운 부분과 중첩되게 형성된 게이트를 포함한다. 따라서, 게이트산화막의 두께를 채널영역 상에서 증가시키지 않고 게이트와 불순물영역이 중첩되는 부분에서만 증가시키므로 전류 구동 능력을 저하시키지 않고 기생 커패시턴스를 감소시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, wherein a semiconductor substrate, a field oxide film formed on a predetermined portion of the semiconductor substrate to define an active region, and doped with impurities of a conductivity type opposite to that of the semiconductor substrate in the semiconductor substrate An impurity region defining a channel region, a gate oxide film formed on the semiconductor substrate to be thicker on the impurity region than the channel region, and having a step difference, and both ends of the gate oxide film overlap with the thick portion of the gate oxide film. And a gate formed to be. Therefore, the thickness of the gate oxide film is increased only at the portion where the gate and the impurity region overlap, without increasing the thickness on the channel region, so that the parasitic capacitance can be reduced without lowering the current driving capability.
Description
제1도는 종래 기술에 따른 반도체장치의 단면도1 is a cross-sectional view of a semiconductor device according to the prior art.
제2도(A) 내지 (B)는 종래 기술에 따른 반도체장치의 제조공정도2A to 2B are manufacturing process diagrams of a semiconductor device according to the prior art.
제3도는 본 발명에 따른 반도체장치의 단면도3 is a cross-sectional view of a semiconductor device according to the present invention.
제4도는 본 발명과 종래 기술에 따른 반도체장치의 드레인전류(Id)의 양을 비교한 그래프.4 is a graph comparing the amount of drain current Id of a semiconductor device according to the present invention and the prior art.
제5도는 본 발명과 종래 기술에 따른 반도체장치의 기생 커패시턴스를 비교한 그래프5 is a graph comparing parasitic capacitances of semiconductor devices according to the present invention and the prior art.
제6도(A) 내지 (C)는 본 발명의 일실시예에 따른 반도체장치의 제조공정도6A to 6C are manufacturing process diagrams of a semiconductor device according to an embodiment of the present invention.
제7도(A) 내지 (C)는 본 발명의 다른 실시예에 따른 반도체장치의 제조공정도7A to 7C are manufacturing process diagrams of a semiconductor device according to another embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
21:반도체기판23:필드산화막21: semiconductor substrate 23: field oxide film
25:게이트산화막26:감광막25: gate oxide film 26: photosensitive film
27:게이트29:불순물영역27: gate 29: impurity region
31:마스크층31: mask layer
본 발명은 반도체장치 및 그의 제조방법에 관한 것으로서, 특히, 소오스 및 드레인영역을 이루는 불순물영역과 게이트 사이의 기생 커패시턴스를 감소시켜 동작 속도를 향상시킬 수 있는 반도체장치 및 그의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same, which can improve an operation speed by reducing parasitic capacitance between an impurity region and a gate forming a source and drain region.
반도체장치가 고집적화 됨에 따라 게이트의 면적 및 길이가 짧아진다. 그러므로, 반도체장치의 전류 구동 능력을 저하시키지 않기 위해 게이트산화막의 두께를 감소시킨다.As semiconductor devices become more integrated, the area and length of the gate become shorter. Therefore, the thickness of the gate oxide film is reduced so as not to lower the current driving capability of the semiconductor device.
제1도는 종래 기술에 따른 반도체장치의 단면도이다.1 is a cross-sectional view of a semiconductor device according to the prior art.
종래 기술에 따른 반도체장치는 반도체기판(11) 상에 트랜지스터가 형성되는 활성영역을 한정하는 필드산화막(13)이 선택산화방법인 LOCOS(Local Oxidation of Silicon)방법에 의해 형성된다. 그리고, 반도체기판(11) 상의 활성영역에 게이트산화막(15)가 형성되고, 이 게이트산화막(15)상에 게이트(17)가 형성된다. 그리고, 게이트(17) 양측의 반도체기판(11)에 이 반도체기판(11)과 반대 도전형의 불순물이 고농도로 도핑되어 소오스 및 드레인영역으로 사용되는 불순물영역(19)이 형성된다. 상기에서 게이트(17) 하부의 불순물영역(19) 사이는 전자가 흐르는 채널 영역이 된다.In the semiconductor device according to the related art, a field oxide film 13 defining an active region in which a transistor is formed on a semiconductor substrate 11 is formed by a local oxidation of silicon (LOCOS) method, which is a selective oxidation method. A gate oxide film 15 is formed in the active region on the semiconductor substrate 11, and a gate 17 is formed on the gate oxide film 15. The impurity regions 19 used as source and drain regions are formed on the semiconductor substrates 11 on both sides of the gate 17 by being heavily doped with impurities of a conductivity type opposite to that of the semiconductor substrate 11. In the above, the impurity region 19 under the gate 17 becomes a channel region through which electrons flow.
제2도(A) 내지 (B)는 종래 기술에 따른 반도체장치의 제조공정도이다.2A to 2B are manufacturing process diagrams of a semiconductor device according to the prior art.
제2도(A)를 참조하면, 반도체기판(11) 표면의 소정 부분에 통상의 선택산화방법인 LOCOS 방법에 의해 필드산화막(13)을 형성하여 소자의 활성영역을 한정한다. 그리고, 반도체기판(11)의 필드산화막(13)이 형성되지 않은 부분을 열산화시켜 게이트산화막(15)을 형성한다.Referring to FIG. 2A, the field oxide film 13 is formed on a predetermined portion of the surface of the semiconductor substrate 11 by the LOCOS method, which is a conventional selective oxidation method, to define the active region of the device. The gate oxide film 15 is formed by thermally oxidizing a portion where the field oxide film 13 of the semiconductor substrate 11 is not formed.
제2도(B)를 참조하면, 게이트산화막(15)상에 불순물이 도핑된 다결정실리콘을 증착하고, 이 다결정실리콘을 포토리쏘그래피(photolithography) 방법으로 패터닝하여 게이트(17)를 형성한다. 그리고, 게이트(17)를 마스크로 사용하여 반도체기판(11)에 반대 도전형의 불순물을 이온 주입하고 열처리하여 불순물영역(19)을 형성한다.Referring to FIG. 2B, a polysilicon doped with impurities is deposited on the gate oxide film 15, and the polysilicon is patterned by photolithography to form a gate 17. The impurity region 19 is formed by ion implantation and heat treatment of the opposite conductivity type impurities into the semiconductor substrate 11 using the gate 17 as a mask.
상술한 종래의 반도체장치는 게이트에 전압을 인가하면 게이트산화막 하부가 반전되어 채널영역이 형성되는데, 이 때, 소오스 및 드레인영역으로 이용되는 불순물영역 사이에 바이어스(bias)를 인가하면 캐리어들이 가속되어 전류가 흐르게 된다. 이러한 반도체장치는 고집적화 됨에 따라 전류 구동 능력을 저하시키지 않기 위해 게이트산화막의 두께를 감소시킨다.In the above-described conventional semiconductor device, when a voltage is applied to a gate, a lower portion of a gate oxide film is inverted to form a channel region. At this time, carriers are accelerated by applying a bias between an impurity region used as a source and a drain region. Current will flow. As the semiconductor device is highly integrated, the thickness of the gate oxide film is reduced so as not to lower the current driving capability.
그러나, 상술한 종래의 반도체장치는 불순물영역을 형성하기 위해 주입된 불순물을 열처리하면 이 불순물이 채널 영역으로 확산된다. 그러므로, 전도성의 게이트와 불순물영역 사이에 절연체인 게이트산화막이 있으므로 기생 커패시턴스가 존재하여 소자의 동작 속도를 저하시키는 문제점이 있었다.However, in the above-described conventional semiconductor device, when the impurity implanted to form the impurity region is heat treated, the impurity diffuses into the channel region. Therefore, since there is a gate oxide film as an insulator between the conductive gate and the impurity region, parasitic capacitance is present, which causes a problem of lowering the operation speed of the device.
따라서, 본 발명의 목적은 게이트와 불순물영역 사이의 기생 커패시턴스를 감소시켜 소자의 동작 속도가 저하되는 것을 방지할 수 있는 반도체장치를 제공함에 있다.Accordingly, it is an object of the present invention to provide a semiconductor device capable of reducing the operating speed of an element by reducing parasitic capacitance between the gate and the impurity region.
본 발명의 다른 목적은 게이트와 불순물영역 사이에 기생 커패시턴스를 감소시킬 수 있는 반도체장치의 제조방법을 제공함에 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing parasitic capacitance between a gate and an impurity region.
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치는 반도체기판과, 상기 반도체기판 상의 소정 부분에 형성되어 활성영역을 한정하는 필드산화막과, 상기 반도체기판 내에 이 반도체기판과 반대 도전형의 불순물이 도핑되어 형성되며 채널영역을 한정하는 불순물영역과, 상기 반도체기판 상에 채널영역 보다 불순물영역 상에 두껍게 형성되어 단차를 갖는 게이트산화막과, 상기 게이트산화막 상에 양측 끝 부분이 이 게이트산화막의 두꺼운 부분과 중첩되게 형성된 게이트를 포함한다.A semiconductor device according to the present invention for achieving the above object is a semiconductor substrate, a field oxide film formed in a predetermined portion on the semiconductor substrate to define an active region, and the semiconductor substrate is doped with impurities of a conductivity type opposite to that of the semiconductor substrate. And an impurity region defining a channel region, a gate oxide film formed on the semiconductor substrate to be thicker than the channel region on the impurity region, and having a step height, and both ends of the gate oxide film having a thick portion of the gate oxide film; It includes a gate formed to overlap.
상기 다른 목적을 달성하기 위한 본 발명에 따른 반도체장치의 제조방법은 반도체기판 상의 소정 부분에 소자의 활성영역을 한정하는 필드산화막을 형성하고 상기 반도체기판 상의 활성영역에 게이트산화막을 형성하는 공정과, 상기 게이트산화막 상의 소자 활성영역 내에 채널영역을 한정하는 감광막을 형성하는 공정과, 상기 감광막을 마스크로 사용하여 게이트산화막의 노출된 부분을 소정 두께 식각하고 상기 감광막을 제거하는 공정과, 상기 게이트산화막의 식각된 부분 상에 위치하며 양측 끝 부분이 시각되지 않은 부분과 중첩되도록 게이트를 형성하는 공정과, 상기 게이트를 마스크로 사용하여 상기 반도체기판에 불순물영역을 형성하는 공정을 구비한다.According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, including forming a field oxide film defining an active region of a device in a predetermined portion on a semiconductor substrate, and forming a gate oxide film in an active region on the semiconductor substrate; Forming a photoresist film defining a channel region in the device active region on the gate oxide film, etching the exposed portion of the gate oxide film by a predetermined thickness using the photoresist film as a mask, and removing the photoresist film; And forming a gate on the etched portion so that both ends thereof overlap with the unvisible portion, and forming an impurity region on the semiconductor substrate using the gate as a mask.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제3도는 본 발명에 따른 반도체장치의 단면도이다.3 is a cross-sectional view of a semiconductor device according to the present invention.
본 발명에 따른 반도체장치는 반도체기판(21)에 트랜지스터가 형성되는 활성영역을 한정하는 필드산화막(23)이 선택산화방버인 LOCOS(Local Oxidation of Silicon)방법에 의해 형성된다. 그리고, 반도체기판(21) 상의 활성영역에 게이트산화막(25)가 형성되고, 이 게이트산화막(25) 상에 게이트(27)가 형성된다. 그리고, 게이트(27) 양측의 반도체기판(21)에 이 반도체기판(21)과 반대 도전형의 불순물이 고농도로 이온주입되고 열처리되어 소오스 및 드레인영역으로 사용되는 불순물영역(29)이 형성된다. 그러므로, 게이트(27) 하부의 불순물영역(29) 사이는 전자가 흐르는 채널 영역이 된다. 상기에서, 게이트산화막(25)은 게이트(27)이 양측 끝 부분과 중첩되는 부분이 가운데 부분의 채널 영역과 중첩되는 부분 보다 두껍게 형성되어 단차를 이룬다.In the semiconductor device according to the present invention, a field oxide film 23 defining an active region in which a transistor is formed on the semiconductor substrate 21 is formed by a local oxidation of silicon (LOCOS) method, which is a selective oxidation barrier. A gate oxide film 25 is formed in the active region on the semiconductor substrate 21, and a gate 27 is formed on the gate oxide film 25. Impurities of opposite conductivity type to the semiconductor substrate 21 on both sides of the gate 27 are ion-implanted at high concentration and heat-treated to form an impurity region 29 for use as the source and drain regions. Therefore, between the impurity regions 29 under the gate 27 becomes a channel region through which electrons flow. In the above, the gate oxide film 25 has a step where the portion of the gate 27 overlapping with both end portions is formed thicker than the portion overlapping the channel region of the center portion.
상기에서, 불순물영역(29) 형성시 이온 주입된 불순물은 열처리할 때 게이트(27) 하부의 채널 영역으로 확산되어 게이트(27)의 양측 끝 부분과 중첩된다. 그러므로, 게이트(27)와 불순물영역(29)이 중첩되는 부분에 기생 커패시터가 형성되는데, 게이트산화막(25)은 게이트(27)와 불순물영역(29)이 중첩되는 부분이 중첩되지 않은 채널 영역 보다 두껍게 형성된다.In the impurity region 29, the implanted impurities are diffused into the channel region under the gate 27 when the heat treatment is performed, and overlap with both ends of the gate 27. Therefore, a parasitic capacitor is formed at a portion where the gate 27 and the impurity region 29 overlap each other, and the gate oxide film 25 has a portion where the gate 27 and the impurity region 29 overlap each other than a channel region where the overlapping portion is not overlapped. It is formed thick.
즉, 게이트산화막(25)은 게이트(27)와 불순물영역(29)이 중첩되지 않는 채널 영역에서 두께(d1)가 70~130Å 정도이며, 중첩되는 부분에서 500~1000Å 정도의 폭(w)을 가지고 두께(d2)가 100~200Å 정도로 통상적인 두께 보다 30~70Å 정도가 두껍다. 그러므로, 게이트산화막(25)의 두께를 채널영역 상에서 증가시키지 않고 게이트(27)와 불순물영역(29)이 중첩되는 부분에서만 증가시키므로 전류 구동 능력을 저하시키지 않고 기생 커패시턴스를 감소시킬 수 있다.That is, the gate oxide film 25 has a thickness d1 of about 70 to 130 microns in a channel region where the gate 27 and the impurity region 29 do not overlap, and a width w of about 500 to 1000 micrometers in an overlapping portion. It has a thickness (d2) of 100-200Å about 30 ~ 70 30 thicker than normal thickness. Therefore, since the thickness of the gate oxide film 25 is increased on the channel region without increasing the thickness on the channel region, parasitic capacitance can be reduced without lowering the current driving capability.
제4도는 본 발명과 종래 기술에 따른 반도체장치의 드레인전류(Id)의 양을 비교한 그래프이고, 제5도는 기생 커패시턴스를 비교한 그래프이다.4 is a graph comparing the amount of the drain current (Id) of the semiconductor device according to the present invention and the prior art, and FIG. 5 is a graph comparing the parasitic capacitance.
제4도 및 제5도는 게이트산화막(25)이 게이트(27)와 불순물영역(29)이 중첩되지 않는 채널 영역에서 두께(d1)가 80Å이고, 중첩되는 부분에서 두께(d2)가 130Å 정도이며, 중첩되는 부분의 폭(w)이 700Å일 때 게이트(27)에 인가되는 전압을 변화시키면서 드레인전류(Id)와 기생커패시턴스를 측정한 것이다.4 and 5 show that the gate oxide film 25 has a thickness d1 of 80 kPa in the channel region where the gate 27 and the impurity region 29 do not overlap, and the thickness d2 of the gate oxide film 25 is about 130 kPa. The drain current Id and the parasitic capacitance are measured while varying the voltage applied to the gate 27 when the width w of the overlapping portion is 700 mW.
상기에서 드레인전류(Id)는 제4도에 도시된 바와 같이 게이트(27)에 인가되는 전압이 0V에서 3V 정도로 변할 때까지 차이가 없다가 5V 정도가 되면 본 발명에 따른 반도체장치는 종래 기술에 따른 것 보다 매우 작은 양이 감소된다. 그러나, 기생커패시턴스는 제5도에 도시된 바와 같이 매우 큰 폭으로 감소되는데, 게이트(27)에 인가되는 전압이 0V일 때 4.3×1016에서 3.1×1016F/cm로 감소된다.As shown in FIG. 4, the drain current Id does not differ until the voltage applied to the gate 27 is changed from 0V to about 3V, and then becomes about 5V. A very small amount is reduced than followed. However, the parasitic capacitance is greatly reduced, as shown in FIG. 5, from 4.3 × 10 16 to 3.1 × 10 16 F / cm when the voltage applied to the gate 27 is 0V.
제6도(A) 내지 (C)는 본 발명의 일 실시예에 따른 반도체장치의 제조공정도이다.6A to 6C are manufacturing process diagrams of a semiconductor device according to one embodiment of the present invention.
제6도(A)를 참조하면, 반도체기판(21) 표면의 소정 부분에 통상의 선택산화방법인 LOCOS(Local Oxidation of Silicon) 방법에 의해 필드산화막(23)을 형성하여 소자의 활성영역을 한정한다. 그리고, 반도체기판(21)의 필드산화막(23)이 형성되지 않은 부분을 열산화하여 100~200Å 정도 두께의 게이트산화막(25)을 형성한다.Referring to FIG. 6A, a field oxide film 23 is formed on a predetermined portion of the surface of the semiconductor substrate 21 by a local oxidation of silicon (LOCOS) method, which is a conventional selective oxidation method, to define an active region of the device. do. Then, a portion of the semiconductor substrate 21 in which the field oxide film 23 is not formed is thermally oxidized to form a gate oxide film 25 having a thickness of about 100 to 200 占 퐉.
제6도(B)를 참조하면, 필드산화막(23) 및 게이트산화막(25) 상에 감광막(26)을 형성한다. 그리고, 게이트산화막(25)이 노출되도록 감광막(26)을 노광 및 현상하여 소자의 활성영역 내에 채널영역을 한정한다. 그 다음, 감광막(26)을 마스크로 사용하여 게이트산화막(25)의 노출된 부분을 30~70Å 정도의 두께를 식각하여 단차를 이루도록 한다.Referring to FIG. 6B, a photosensitive film 26 is formed on the field oxide film 23 and the gate oxide film 25. Then, the photoresist layer 26 is exposed and developed to expose the gate oxide layer 25 to define a channel region in the active region of the device. Next, using the photosensitive film 26 as a mask, the exposed portion of the gate oxide film 25 is etched to a thickness of about 30 ~ 70Å to form a step.
제6도(C)를 참조하면, 감광막(26)을 제거한다. 그리고, 게이트산화막(25)상에 불순물이 도핑된 다결정실리콘을 화학기상증착(Chemical Vapor Deposition:이하, CVD라 칭함) 방법으로 증착한 후 포토리쏘그래피(photolithography) 방법으로 패터닝하여 게이트(27)를 형성한다. 이 때, 게이트(27)를 가운데 부분이 게이트산화막(25)의 식각된 부분에 위치하며 양측 끝 부분이 식각되지 않은 부분과 500~1000Å 정도로 중첩되도록 형성한다. 그리고, 게이트(27)를 마스크로 사용하여 반도체기판(21)에 이 반도체기판(21)과 반대 도전형의 불순물을 이온 주입하고 열처리하여 소오스 및 드레인영역으로 사용되는 불순물영역(29)을 형성한다. 이 때, 불순물영역(29)은 불순물이 게이트(27) 하부의 채널영역으로 확산되어 게이트산화막(25)이 식각되지 않은 부분까지 중첩되도록 한다.Referring to FIG. 6C, the photosensitive film 26 is removed. In addition, the polycrystalline silicon doped with impurities on the gate oxide layer 25 is deposited by chemical vapor deposition (hereinafter, referred to as CVD) method, and then patterned by photolithography to form the gate 27. Form. At this time, the gate 27 is formed so that the center portion is located in the etched portion of the gate oxide film 25 and both ends thereof overlap with the unetched portion at about 500 to 1000 kPa. Then, using the gate 27 as a mask, the semiconductor substrate 21 is ion-implanted with impurities of the opposite conductivity type to the semiconductor substrate 21 and heat-treated to form the impurity region 29 used as the source and drain regions. . In this case, the impurity region 29 diffuses the impurities into the channel region under the gate 27 so that the gate oxide layer 25 overlaps with the non-etched portion.
제7도(A) 내지 (C)는 본 발명의 다른 실시예에 따른 반도체장치의 제조공정도이다.7A to 7C are manufacturing process diagrams of a semiconductor device according to another embodiment of the present invention.
제7도(A)를 참조하면, 반도체기판(21) 표면의 소정 부분에 통상의 선택산화방법인 LOCOS(Local Oxidation Of Silicon)방법에 의해 필드산화막(23)을 형성하여 소자의 활성영역을 한정한다. 그리고, 반도체기판(21)의 필드산화막(23)이 형성되지 않은 부분을 열산화하여 70~130Å 정도 두께의 제1 게이트산화막(25a)을 형성한다.Referring to FIG. 7A, a field oxide film 23 is formed on a predetermined portion of the surface of the semiconductor substrate 21 by a local oxidation of silicon (LOCOS) method, which is a conventional selective oxidation method, to define an active region of the device. do. A portion of the semiconductor substrate 21 on which the field oxide film 23 is not formed is thermally oxidized to form a first gate oxide film 25a having a thickness of about 70 to 130 Å.
제7도(B)를 참조하면, 필드산화막(23) 및 제1 게이트산화막(25a) 상에 질화실리콘을 증착하여 마스크층(31)을 형성한다. 그리고, 마스크층(31)에 필드산화막(23) 및 제1 게이트산화막(25a)이 노출되도록 포토리쏘그래피 방법으로 패터닝하여 소자의 활성영역 내에 채널영역을 한정한다. 그 다음, 제1 게이트산화막(25a)의 노출된 부분을 30~70Å 정도의 두께로 산화하여 제2 게이트산화막(25b)을 형성한다. 이 때, 마스크층(31)에 의해 채널영역을 한정하는 제1 게이트산화막(25a)의 노출되지 않은 부분은 산화되지 않아 제2 게이트산화막(25b)가 형성되지 않는다.Referring to FIG. 7B, a silicon nitride is deposited on the field oxide film 23 and the first gate oxide film 25a to form a mask layer 31. The channel region is defined in the active region of the device by patterning the photolithography method to expose the field oxide layer 23 and the first gate oxide layer 25a on the mask layer 31. Next, the exposed portion of the first gate oxide film 25a is oxidized to a thickness of about 30 to 70 Å to form a second gate oxide film 25b. At this time, the unexposed portions of the first gate oxide film 25a defining the channel region by the mask layer 31 are not oxidized, so that the second gate oxide film 25b is not formed.
제7도(C)를 참조하면, 마스크층(31)을 제거한다. 그리고, 제1 게이트산화막(25a) 상에 제2 게이트산화막(25b)과 양측 끝 부분이 500~1000Å 정도로 중첩되도록 게이트(27)를 형성한다. 그리고, 게이트(27)를 마스크로 사용하여 반도체기판(21)에 이 반도체기판(21)과 반대 도전형의 불순물을 이온 주입하고 열처리하여 소오스 및 드레인영역으로 사용되는 불순물영역(29)을 형성한다.Referring to FIG. 7C, the mask layer 31 is removed. Then, the gate 27 is formed on the first gate oxide film 25a such that the second gate oxide film 25b and both ends thereof overlap each other at about 500 to 1000 microseconds. Then, using the gate 27 as a mask, the semiconductor substrate 21 is ion-implanted with impurities of the opposite conductivity type to the semiconductor substrate 21 and heat-treated to form the impurity region 29 used as the source and drain regions. .
따라서, 본 발명은 게이트산화막의 두께를 채널영역 상에서 증가시키지 않고 게이트와 불순물영역이 중첩되는 부분에서만 증가시키므로 전류 구동 능력을 저하시키지 않고 기생 커패시턴스를 감소시킬 수 있는 이점이 있다.Therefore, the present invention increases the thickness of the gate oxide film only in the region where the gate and the impurity region overlap without increasing the thickness of the gate oxide layer, thereby reducing the parasitic capacitance without degrading the current driving capability.
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