KR19980041578A - Boost circuit of semiconductor memory device - Google Patents

Abstract

The booster circuit of the present invention boosts the booster circuit to a level of an external power supply voltage provided from the outside of the semiconductor memory device for the high-speed level-up of the booster voltage when the power-up circuit is pumped up and output through the booster voltage output node. And a power-up precharge unit for precharging the voltage output node.

Description

Boost circuit of semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit applied to a semiconductor memory device, and more particularly to a boosting circuit of a semiconductor memory device capable of increasing the pumping efficiency of voltage and suppressing the occurrence of latch-up.

In a typical volatile semiconductor memory device, a voltage booster circuit is adopted that develops a voltage charged in a memory cell to a bit line without lowering a level, or boosts a voltage boosted to a predetermined high voltage for high speed operation. Such a boost circuit typically receives an internal power supply voltage provided from an internal power supply voltage generation circuit and performs a pumping operation. The internal power supply voltage generation circuit receives the reference voltage from the reference voltage generation circuit that receives the external voltage and makes a reference voltage to generate the internal power supply voltage. The booster circuit performs a pumping operation to boost the internal power supply voltage by about 2 volts, and the following problems are often caused by the level up of the internal power supply voltage during power supply.

First, when the pumping capability of the boosting circuit is insufficient, if the boosted voltage is precharged by subtracting the threshold voltage of the NMOS transistor from the level of the external power supply voltage, the section to be precharged at power-up becomes large. In order to reduce this section, pumping capacity must be increased by increasing the pumping capacitance in the boosting circuit, which causes a problem that the layout of the chip is increased. If the layout is limited, the pumping capacity is insufficient, so that the time taken for the boosted voltage level to reach the target level becomes longer, and at a low power supply voltage, the high voltage, which is the set boosted voltage, cannot be output.

Second, when the pumping capacity is insufficient, there is a problem that the latch-up occurs when the boost voltage is precharged by subtracting the threshold voltage of the NMOS transistor from the level of the external power supply voltage. That is, as shown in FIG. 1, source and drain regions are formed in the N type well 20 on the substrate 10 to form a PMOS transistor, and then a boosted voltage VPP is applied to one node of the source or drain and an internal power source is supplied to the other node. When the voltage IVC is provided and the bias voltage is applied to the bias stage 22 at VPP, parasitic bipolar transistors exist in the N type well 20 to generate a latchup. More specifically, latch-up will inevitably occur if the voltage between the emitter and the base of the parasitic bipolar transistor has a difference of about 0.7 volts. In other words, the N-type MOS transistor formed directly on the substrate 10 is a precharge transistor. If the threshold voltage of the transistor is 0.7 volt or more, the latch-up condition is satisfied. FIG. 2 illustrates a circuit configuration in which latch up may occur in the structure of the morphed MOS transistor as shown in FIG. 1. When there are two shaped MOS transistors P1 and P2 and a voltage is applied to each node as shown in FIG. 2, a layer of PNPN or NPNP is formed inside the MOS transistor to take a thyristor structure, thereby satisfying a condition in which the thyristor is turned on. The latch-up phenomenon occurs at the time of interrupting the operation of the circuit.

Figure 3 shows a boost circuit according to the prior art. The structure of FIG. 3 consists of a plurality of inverters 30,31,35,36,37 consisting of p-type and N-type transistors, pumping MOS capacitors 32,38, and N-type transistors 33,34,39,50,51. have. In the boosting circuit having the configuration as shown in FIG. 3, when the boost voltage is precharged by subtracting the threshold voltage of the NMOS transistor from the level of the internal voltage, the precharged section is increased during power-up. 5 and 7 respectively show graphs showing boosted voltage levels during power-up according to the circuit of FIG. 3 and timing diagrams of boosted voltage pumping. Referring to this, a section in which the VPP level becomes lower than the IVC level during power-up is shown. This is quite long, and you can see that there is a high probability of causing latchup.

As described above, there is a problem in that the pumping efficiency of the voltage is low and a latchup phenomenon is often caused.

SUMMARY OF THE INVENTION An object of the present invention is to provide a boosting circuit of a semiconductor memory device which can solve the above-mentioned conventional problems.

Another object of the present invention is to provide a boosting circuit of a semiconductor memory device capable of increasing pumping efficiency of voltage and suppressing occurrence of latch-up.

1 is a cross-sectional view of a MOS transistor having a parasitic bipolar transistor structure in which latch up may occur.

2 is a circuit diagram of a MOS transistor in which latchup may occur.

Figure 3 is a boost circuit diagram according to the prior art.

4 is a boost circuit diagram according to the present invention.

FIG. 5 is a diagram illustrating a boosted voltage level during power up according to the circuit of FIG. 3. FIG.

FIG. 6 is a diagram illustrating a boosted voltage level during power up according to the circuit of FIG. 4. FIG.

7 is a timing diagram of boosted voltage pumping in accordance with the circuit of FIG.

8 is a timing diagram of boosted voltage pumping in accordance with the circuit of FIG.

A boost circuit according to the present invention for achieving the above objects, the power-up to precharge the boost voltage output node to the level of the external power supply voltage provided from the outside of the semiconductor memory device for the high-speed level-up of the boost voltage at power-up It is characterized by having a precharge section.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 shows a boost circuit according to the present invention. FIG. 6 is a view illustrating a boosted voltage level during power-up according to the circuit of FIG. 4 in comparison with FIG. 5. 8 is a timing diagram of boosted voltage pumping according to the circuit of FIG. 4.

Referring to FIG. 4, the boosting circuit of the semiconductor memory device according to the present exemplary embodiment may basically include a first pumping capacitor 32 having one side plate connected to an internal clock OSC that is not inverted through inverters 30 and 31 as in the configuration of FIG. 3. And a first pumping transistor 33 in which the internal power supply voltage IVC is commonly received as a drain and a gate terminal, and a source terminal of which is connected to the other plate of the first pumping capacitor 32, and a drain and a gate terminal of the source terminal of the first pumping transistor 33. The second pumping transistor 34 which is connected in common and outputs the first pumping voltage to the source terminal, the second pumping capacitor 38 having one plate connected to the internal clock inverted through the inverters 35, 36 and 37, and the internal power supply voltage IVC are drained. And a third pumping transistor 39 which is commonly received by a gate terminal and whose source terminal is connected to the other plate of the second pumping capacitor 38, and the second and third pumping pumps. A fourth pumping transistor 40 for outputting the final pumped voltage as a boosted voltage to a boosted voltage output node, which is a source terminal, having a drain and a gate terminal commonly connected to the source terminal of the jitter, and receiving an external power supply voltage as a drain and gate terminal. And a precharge transistor 41 for precharging the boosted voltage output node.

In the above configuration, one side plate of the second pumping capacitor 38 and the boosted voltage output node VPP for precharging the boosted voltage output node to the level of the external power supply voltage such that the boosted voltage is rapidly leveled up during power-up. Power-up precharge portions 100 connected therebetween are provided to achieve the inherent object of the present invention. The power-up precharge unit 100 is connected to the other plate in response to the inverted internal clock in order to precharge the boosted voltage output node to the level of the external power supply voltage so that the boosted voltage is at a high level. A pumping capacitor C1 for boosting the connected boosting node, a pumping transistor T5 for providing an internal power supply voltage to the boosting node, a power-up pre-received by the drain terminal, and having a source terminal connected to the boosted voltage output node. A charge transistor T1, an inverter I1 that inverts the signal provided at power-up, a drive transistor T3 that receives the output of the inverter I1 as a drain terminal and receives the internal power supply voltage as a gate terminal; A gate terminal is connected to the source terminal of the transistor and a drain terminal is connected to the boosting node. And a source terminal receiving the transfer transistor T2 connected to the gate of the power-up precharge transistor and the signal VCCH provided at power-up as a gate terminal, and the drain source channel being connected to the gate terminal of the power-up precharge transistor. And a precharge inhibiting transistor T4 connected between grounds to prohibit the boosted voltage output node from precharging to the external power supply voltage after the end of the power-up period.

With the above configuration, the operation in the power-up section in which the boosting circuit starts operation is as follows. The boosted voltage output node VPP is precharged to the level of the external power supply voltage EVC while the signal VCCH provided at power up is at a low level as shown by the waveform VCCH of FIG. 8. This is because the boosting node B is precharged to IVC-Vtn by the transistor T5 and the gate terminal C of the transistor T2 is precharged to IVC-Vtn while the internal clock OSC is output as a high pulse, and thus the gate terminal of the transistor T1. After D appears once as the level of IVC-2Vtn, the one side plate of the capacitor C1 receives high through the inverter 37 while the internal clock OSC is output as a low pulse, so the boosting node B acts as the pumping capacitor. Is boosted to 2IVC-Vtn and the transistor T1 is pulled up on the gate terminal D of the transistor T1 at a level of 2IVC-2Vtn, so that the boosted voltage output node VPP is precharged as the level of the external power supply voltage EVC. Aji. Here, in order to precharge the output node to the level of the external power supply voltage EVC normally, at least the IVC level is preferably 3 Vtn or more. When the signal VCCH transitions to a high level like the waveform VCCH of FIG. 8, the transistor T4 is turned on to bring the node D to the ground level and the transfer transistor T2 is turned off, so precharge operation to the EVC level is further performed. It doesn't happen anymore. At this point, the boost circuit starts normal operation and outputs the high voltage VPP to the target level, so that further precharge operation is prohibited. The power-up precharge unit 100 performing such an operation is useful when the pumping capability of the boosting circuit is insufficient and has a merit that a conventional circuit can be solved by only a simple circuit configuration.

As described above, the present invention has the effect of increasing the pumping efficiency of the voltage and suppressing the occurrence of latch-up at power-up.

Claims (6)

A boosting circuit for pumping an internal power supply voltage in a semiconductor memory device and outputting the same through a boosted voltage output node, wherein the boosted voltage is at a level of an external power supply voltage provided from the outside of the semiconductor memory device for a high level-up of the boosted voltage at power-up. And a power-up precharge section for precharging the output node. A first pumping capacitor having one side plate connected to the non-inverted internal clock, a first pumping transistor commonly receiving an internal power supply voltage as a drain and a gate terminal, and a source terminal having a source terminal connected to the other plate of the first pumping capacitor; A second pumping transistor having a drain and a gate terminal connected to the source terminal of the pumping transistor and outputting a first pumping voltage to the source terminal, a second pumping capacitor having one plate connected to the inverted internal clock, and an internal power supply voltage And a third pumping transistor commonly connected to the gate terminal and having a source terminal connected to the other plate of the second pumping capacitor, and a drain terminal and a gate terminal commonly connected to a connection point of the source terminals of the second and third pumping transistors. A fourth pumping transistor which outputs the final pumped voltage as the boosted voltage to the boosted voltage output node; In the emitter, and a step-up circuit of the semiconductor memory device that includes receiving an external supply voltage to the drain and gate terminal of the precharge transistor of the charge-free to the step-up voltage output node: A power-up precharge connected between one side plate of the second pumping capacitor and the boosted voltage output node to precharge the boosted voltage output node to a level of the external power supply voltage so that the boosted voltage is rapidly leveled up at power-up; A circuit characterized by having a branch. 3. The power up precharge unit of claim 2, wherein a pumping capacitor boosts a boosting node connected to the other plate in response to the inverted internal clock, a pumping transistor that provides an internal power supply voltage to the boosting node, and a drain terminal. A power-up precharge transistor connected to the boosted voltage output node and receiving the external power supply voltage; and a boosted voltage level on the boosting node in response to a signal provided at power-up. And a transfer unit provided to a gate of a transistor to achieve a high level level-up of the boosted voltage upon power-up. 4. The driving circuit of claim 3, wherein the transmission unit is an inverter for inverting the signal provided at power up, a driving transistor for receiving an output of the inverter as a drain terminal and receiving the internal power supply voltage as a gate terminal; And a transfer transistor connected to a source terminal of the transistor, a drain terminal connected to the boosting node, and a source terminal connected to a gate of the power-up precharge transistor. The voltage boosting voltage output node of claim 3, wherein the signal provided at power-up is received through a gate terminal, and a drain source channel is connected between the gate terminal of the power-up precharge transistor and ground. And a precharge inhibiting transistor for inhibiting precharging with the external power supply voltage. A first pumping capacitor having one side plate connected to the inverted internal clock, a first pumping transistor in which an internal power supply voltage is commonly received by a drain and a gate terminal, and a source terminal of which is connected to the other plate of the first pumping capacitor, and the first pumping capacitor A second pumping transistor having a drain and a gate terminal commonly connected to a source terminal of the transistor and outputting a first pumping voltage to a source terminal, a second pumping capacitor having one plate connected to a non-inverted internal clock, and an internal power supply voltage And a third pumping transistor commonly connected to the gate terminal and having a source terminal connected to the other plate of the second pumping capacitor, and a drain terminal and a gate terminal commonly connected to a connection point of the source terminals of the second and third pumping transistors. A fourth pumping transistor which outputs the final pumped voltage as the boosted voltage to the boosted voltage output node; In the emitter, and a step-up circuit of the analog dynamic random access memory device comprising receiving an external power supply voltage to the drain and gate terminal of the precharge transistor of the charge-free to the step-up voltage output node: A pumping capacitor that boosts the boosting node connected to the other plate in response to the inverted internal clock to precharge the boosted voltage output node to the level of the external power supply voltage so as to quickly level up the boosted voltage upon power-up. A pumping transistor for providing an internal power supply voltage to the boosting node, a power-up precharge transistor for receiving the external power supply voltage to a drain terminal and having a source terminal connected to the boost voltage output node; An inverter for inverting a signal, a driving transistor for receiving the output of the inverter as a drain terminal and receiving the internal power supply voltage as a gate terminal, a gate terminal connected to a source terminal of the driving transistor, and a drain at the boosting node. The terminal is connected and the source terminal is the power-up precharge A transmission transistor connected to a gate of a transistor and the signal provided at power-up are received as a gate terminal, and a drain source channel is connected between a gate terminal of the power-up precharge transistor and a ground to terminate the power-up period. And a precharge inhibiting transistor for prohibiting a voltage output node from being precharged to the external power supply voltage.