KR19980039917A - Non-collision low power consumption static latch circuit - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Non-collision low power consumption static latch circuit.

2. The technical problem to be solved by the invention

It is intended to prevent data collision, which is a problem of the conventional static circuit, and thus to reduce power consumption.

3. Summary of Solution to Invention

Controlling the external clock signal and the clock bar signal, the transfer gate transfers the input data to the data holding node, the inverter for inverting and outputting the potential value of the data holding node, and the control of the external clock signal and the clock bar signal. A static latch circuit having a feedback circuit for outputting an output value of the inverter fed back by a data holding node, comprising: a clock signal and a clock input to the pitback circuit compared to a clock signal and a clock bar signal input to the transfer gate; And change the timing of the bar signal quickly so that the feedback circuit is cut off before the transfer gate becomes conductive.

4. Important uses of the invention

Used in low power latch circuits.

Description

Non-collision low power consumption static latch circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static latch circuit. In particular, a timing of a clock supplied to a feedback circuit and a clock supplied to a transfer gate is different so that a signal collision does not occur and static power is reduced. It relates to a latch circuit.

The latch circuit is a basic circuit that is used a lot in a large scale integrated circuit (LSI) chip, and it is always operated by a clock, so that the ratio of power consumption in the chip is very large. Therefore, one of the methods for reducing the power consumption of a large scale integrated circuit (LSI) chip is a power consumption reduction of the latch circuit.

1 is a configuration diagram of a conventional static latch circuit, in which M1 and M2 denote transfer gates in which a PMOS transistor and an NMOS transistor are coupled to each other, M3 and M4 denote PMOS transistors, and M5 and M6 denote NMOS transistors, respectively.

As shown in FIG. 1, the transfer gates M1 and M2 of the conventional static latch circuit have two complementary clock signals CLK and clock bar signals in which an NMOS transistor and a PMOS transistor are used. By conducting at the same time (On) or at the same time (Off) at the same time to transfer the input value to the data holding node (D _C ).

The inverter then inverts the potential value of the data holding node and transfers it to the output node QC.

The first PMOS transistor M3 connected to the reference voltage Vdd is controlled by receiving the value of the output node at the gate electrode, and the first NMOS transistor M6 connected to the ground potential is also controlled by receiving the value of the output node at the gate electrode. .

In addition, the second PMOS transistor M4 connected to the first PMOS transistor M3 is controlled by receiving the same clock signal CLK as the clock input to the transfer gates M1 and M2 to the gate electrode. The second NMOS transistor M5 is connected to the same clock bar signal as the clock transferred to the transfer gates M1 and M2. Is controlled by receiving the gate electrode.

Therefore, the feedback circuit composed of two PMOS transistors M3 and M4 and two NMOS transistors M5 and M6 has a clock signal CLK and a clock bar signal. This function feeds back the value outputted to the output node to the data maintenance node under the control of.

The clock signal CLK and the clock bar signal supplied to the conventional static latch circuit as described above. Since is generally generated by the inverter chain (chain) or the like, the timing of change of the two clock signals are slightly different.

Therefore, these two clock signals CLK and An overlap period in which the second PMOS transistor M4 and the second NMOS transistor M5 and the transfer gates M1 and M2 of the feedback circuit operate at the same time occurs.

The data input from the outside that data held in the latch circuit until the node (D _C) when maintained data and different in this point the new input data and the feedback circuit via a transfer gate (M1, M2) in the data holding nodes There is a conflict between the data fed back.

Such a collision of data generates unnecessary through current in the latch circuit, resulting in increased power consumption.

That is, the conventional static latch circuit has a problem in that a data collision occurs when the data transfer gate and the feedback circuit are simultaneously connected to each other and the input data is different from the stored data, thereby increasing power consumption.

Accordingly, the present invention devised to solve the above problems of the prior art, the timing of the clock signal input to the data transfer gate and the clock signal input to the pitback circuit is different from each other, which is a problem of the conventional static circuit data. It is an object of the present invention to provide a static latch circuit capable of preventing a collision and thus reducing power consumption.

1 is a configuration diagram of a conventional static latch circuit,

2 is a block diagram of a static latch circuit according to the present invention;

3 is an operation timing diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

M1, M2: transfer gate

M3, M4: PMOS transistor

M5, M6: NMOS transistor

In order to achieve the above object, the present invention provides a transfer gate and a potential value of the data holding node including a PMOS transistor and an NMOS transistor for transferring data inputted by an external clock signal and a clock bar signal to a data holding node. A static latch circuit having an inverter for inverting and outputting to an output node and a feedback circuit for outputting an output value of the inverter fed back by a control of an external clock signal and a clock bar signal to a data holding node, wherein the transfer gate is connected to the transfer gate. Compared to the input clock signal and the clock bar signal, the timing of the clock signal and the clock bar signal input to the pitback circuit is changed quickly so that the feedback circuit is blocked before the transfer gate becomes conductive.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3.

2 is a configuration diagram of the static latch circuit according to the present invention, Figure 3 shows the operation timing diagram accordingly.

The configuration of the static latch circuit according to the present invention is the same as that of the conventional static latch circuit.

However, according to the present invention, the timing of the clock signal input to the feedback circuits M3, M4, M5, and M6 and the clock signals input to the transfer gates M1 and M2 is prevented in order to prevent data collision, which is a problem of the conventional static latch circuit. Different.

That is, two clock signals T _M input to the transfer gate and The clock signals T _F and which are input to the feedback circuits M3, M4, M5, and M6 than the timing of The timing of the data is changed quickly so that no data collision occurs at the data holding node D _N.

The operation of the present invention will be described in more detail with reference to FIG. 3.

Clock signals T _F and input to the feedback circuits M3, M4, M5, and M6 at time t _A ; The timing of the clock signal T _M and the By changing earlier than the timing of, the NMOS transistor M5 and the PMOS transistor M4 of the feedback circuit are first blocked before the data transfer gates M1 and M2 are turned on.

Accordingly, unlike the related art, an overlap period in which the feedback circuits M3, M4, M5, and M6 and the data transfer gates M1 and M2 are simultaneously conducted does not occur.

Therefore, even when the data input from the outside is different from the data stored in the data holding node, there is no collision between the input signal and the holding signal in the data holding node, so that unnecessary through current is not generated.

In addition, before the output node QC changes, the second PMOS transistor M4 and the second NMOS transistor M5 of the feedback circuit are completely turned off so that no current penetrating through the transistor in the feedback circuit is generated. .

Next, when the operation of the present invention is performed at time t _B , there is a section in which the data transfer gates M1 and M2 and the second PMOS transistor M4 and the second NMOS transistor M5 of the feedback circuit are simultaneously connected. In this case, since the input data from the outside is already stabilized, the output to the data holding node of the feedback circuit has a positive logic relationship with the external input data so that no data collision occurs and only the feedback operation is performed.

The present invention described above is capable of various substitutions, modifications, and changes within the scope without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains, and thus is limited to the above-described embodiments and drawings. It is not.

The circuit simulation results of the power consumption of the present invention as described above are as follows.

The transistor size and load capacity (fanout = 1) of each latch circuit are the same, and the data input is changed by one ratio every two clock cycles. As a result of simulation, the power consumption during operation of the non-collision static latch circuit is It is about 90% of the power consumption of the conventional static latch circuit. That is, the present invention can reduce the power consumption by about 10% compared with the conventional latch circuit, and this value is almost halfway between the dynamic latch, which is considered to operate at the lowest power consumption under the same conditions, and the conventional static latch circuit power consumption. As a precision, it has the characteristic of excellent low power consumption.

Claims (1)

An inverter having a PMOS transistor and an NMOS transistor to transfer data inputted by an external clock signal and a clock bar signal to a data holding node, and an inverter for inverting the potential value of the data holding node to an output node; A static latch circuit having a feedback circuit for outputting an output value of the inverter fed back by control of an external clock signal and a clock bar signal to a data holding node, Compared to the clock signal and the clock bar signal input to the transfer gate, the timing of the clock signal and the clock bar signal input to the pitback circuit is changed quickly so that the feedback circuit is blocked before the transfer gate becomes conductive. Static latch circuit.