KR19980039535A - Picture Synchronizer for MPEG Video Decoder - Google Patents

Abstract

The present disclosure relates to an apparatus for synchronizing a picture of an MPEG video decoder which enables decoding of bitstream data input to a bit buffer in a MPEG video decoder in picture units. When the picture is output from the bit buffer before counting is completed while counting the buffer delay time interval of the picture when any one picture bitstream data starts to be input to the bit buffer, the decoding stops until the end of counting. When the counting ends and the predetermined threshold is delayed and the picture is output from the bit buffer, the decoding is skipped for the picture. Accordingly, the present invention provides an effect that can be decoded by synchronizing in picture units in an MPEG video decoder.

Description

Picture Synchronizer for MPEG Video Decoder

The present invention relates to a system for controlling decoding according to a buffer state in an MPEG video decoder, and in particular, stops or skips decoding according to a buffer delay time interval (vbv_delay) and a buffer output time of an encoded bitstream in a picture unit. The present invention relates to an apparatus capable of synchronizing an MPEG video decoder on a picture basis by controlling the video data decoder.

In the video decoder of the MPEG (moving picture experts group) standard, which is a standard of the video compression method, as shown in FIG. 1, image data in the form of a compression-coded bitstream having a constant bit rate is obtained by using a bit buffer (Bit-Buffer). 11), the variable length decoder (VLD) 12 reads the bitstream video data stored in the bit buffer 11 and performs variable length decoding. The variable-length decoded data is inverse quantized and inverse discrete cosine transformed by an inverse quantization and inverse discrete cosine transformer (IQ / IDCT) 13, and is output as image data that is compensated by the compensator 14 and reconstructed.

In the MPEG video decoder as described above, if the decoding timing of each picture is not correct while decoding the encoded bitstream data, the bit buffer overflows or underflows and thus normal decoding cannot be performed. Therefore, in the bitstream data, there is a 16-bit buffer delay time interval (vbv_delay) counting the bit buffer state at the time when each picture starts to be decoded by 90 ms clock for each picture. The time difference from the time point at which one picture bitstream data is input to the bit buffer to the time point at which the picture bitstream data is output should be equal to the buffer delay time interval (vbv_delay) existing for each picture.

However, when an error occurs in the bitstream data in the MPEG video decoder, the bit buffer cannot be normally maintained when abnormally decoded or decoded quickly or slowly due to hardware structure. As a result, the decoding timing of each picture does not match, and overflow or underflow occurs in the bit buffer.

Accordingly, an object of the present invention is to compare the time interval from the time at which the picture input to the received bit buffer to the output from the bit buffer to decode the encoded bitstream data to the buffer delay time interval for the picture. MPEG video decoders that determine whether they are decoded in time and either stop the decoding operation until on time or skip the picture without decoding the picture can prevent overflow or underflow of the bit buffer. The present invention provides a picture synchronization device of an MPEG video decoder which synchronizes in units.

1 is a block diagram schematically showing a typical MPEG video decoder;

2 is a block diagram schematically showing an MPEG video decoder to which a picture synchronization device of the present invention is applied;

3 is a detailed view showing a picture start code detection unit of the picture synchronization device of FIG. 2;

4 is a detailed diagram illustrating a buffer delay time interval and a buffer input / output comparison unit of the picture synchronization device of FIG. 2;

5 is a detailed view illustrating a counter enable signal generation unit of the picture synchronization device of FIG. 2;

6 is a timing diagram for describing an operation of each component of FIGS. 3 to 5;

7 is a detailed view illustrating a buffer output picture delay signal generation unit of the picture synchronization device of FIG. 2;

8 is a detailed view illustrating a system clock count value detection unit of the picture synchronization device of FIG. 2;

9 is a detailed view showing an offset calculator of the picture synchronization device of FIG. 2;

10 is a detailed view showing a hold signal generator of the picture synchronization device of FIG. 2;

FIG. 11 is a timing diagram for describing an operation of the hold signal generator of FIG. 10; FIG.

12 is a detailed view illustrating a skip signal generator of the picture synchronization device of FIG. 2;

FIG. 13 is a timing diagram for describing an operation of a skip signal generator of FIG. 12. FIG.

Explanation of symbols for main parts of the drawings

20: bit buffer 25: picture synchronization device

30: Picture start code detection unit 40: Buffer delay time interval and buffer input / output comparison unit

50: counter enable signal generator 70: buffer output picture delay signal generator

80: system clock count value detection unit 90: offset calculation unit

100: hold signal generator 120: skip signal generator

The picture synchronization apparatus of the MPEG video decoder according to the present invention for achieving the above object, in the MPEG video decoder to receive the decoded bitstream video data of a constant bit rate and output the decoded video data, the bitstream video data input A system clock count value and a predetermined clock that receive and output a bit buffer, and are connected in parallel to the bit buffer and receive the input and output bitstream video data of the bit buffer, and count the synchronization information as a reference for a predetermined clock. Decode until the end of counting when the picture is output from the bit buffer before counting, while counting the buffer delay time interval of the picture when any picture unit bitstream video data starts to be input to the bit buffer. It generates a stop signal and preset after counting. Picture synchronization means for generating a decoding skip signal when the picture is outputted from the bit buffer and decoded by synchronizing in units of pictures when the picture is delayed by a threshold value; and reading and decoding bitstream image data from the bit buffer, and decoding the picture. And decoding means for stopping decoding or discarding the bitstream image data of the picture according to the decoding stop signal and the decoding skip signal generated by the synchronization means.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram schematically illustrating an MPEG video decoder to which the picture synchronization device of the present invention is applied. As shown, the MPEG video decoder of the present invention includes a bit buffer 20 for buffering input bitstream video data in a predetermined bit unit. In addition, it is connected in parallel to the bit buffer 20 receives the input and output bit stream data of the bit buffer 20, and receives the system clock count value (stc_count_value) and the clock (sclk, clk90㎑) from the outside of the variable length of the rear stage A picture synchronization device 25 for synchronizing on a picture-by-picture basis by outputting a hold signal hold_vld for stopping decoding of the decoder VLD (see FIG. 1) and a skip signal skip_vld for discarding one picture without decoding. It is configured to have. The internal structure of the picture synchronization device 25 is shown separately in FIGS. 3 to 12, which will be described later.

In FIG. 2, the encoded bitstream image data is input to the bit buffer 20 at a constant data rate, and is variably output from the bit buffer 20 according to a request of the variable length decoder VLD. In this case, the variable length decoder VLD stops decoding or skips the picture without decoding the picture according to the hold signal hold_vld to skip signal skip_vld generated by the picture synchronization device 25 of the present invention. The picture synchronization device 25 receives the input / output bitstream data and the system clock count value stc_count_value of the bit buffer 20 together with the clocks sclk and clk90 ms. Here, the system clock count value (stc_count_value) corresponds to a synchronization time (STC; System Time Clock) that is a reference of the decoding playback time of video data in an MPEG video decoder, that is, a 27 MHz clock synchronized by a PLL circuit (not shown). This value is counted as 90Hz divided by '1/300'. This system clock count value (stc_count_value) is represented by 33 bits and is input from the outside. Then, the picture synchronization device 25 synchronizes the operation of each component in accordance with an arbitrary system clock sclk inputted, and the counter 44 shown in FIG. 4 operates in accordance with an input clock of 90 kHz. . The picture synchronization device 25 receives input / output bitstream data of the bit buffer 20 and detects a picture start code (picture_start_code), which will be described in more detail with reference to FIG. 3.

Fig. 3 is a detailed view showing the picture start code detection section 30 in the picture synchronization device 25 (see Fig. 2) of the present invention. As shown, the picture start code detection unit 30 receives three input and output bitstream data of the bit buffer (see FIG. 2) in a predetermined bit unit and sequentially outputs three D-type flip-flops that are sequentially delayed and output. (DFF1 to DFF3) are provided. In addition, comparators 31 to 34 for comparing a predetermined bit of input data and output data of each of the flip-flops DFF1 to DFF3 and matching the picture start code designated according to the MPEG standard, and the comparators 31 to 34. And an AND (35) for outputting a binary signal indicating whether or not the picture start code is detected by performing an AND operation on the output of the signal 34). The logical multiplication device 35 is configured such that four D-type flip-flops DFF4 to DFF7 for sequentially delaying and outputting the picture start code detection signal are connected in series.

The picture start code detector 30 of the picture synchronization device 25 configured as described above generates 8 input / output bitstream data of the bit buffer (see FIG. 2) according to an arbitrary clock (see the sclk waveform of FIG. 6). It is input in bit units (see bitstream in Fig. 6) and sequentially outputs through three flip-flops DFF1 to DFF3. In addition, 29-bit bitstream data including 5 bits of the input 8-bit data and 8-bit data output from the three flip-flops DFF1 to DFF3 are output. Comparators 31 to 34 respectively connected to the input side and the output terminals of the three flip-flops DFF1 to DFF3 compare each input 8-bit data with 100 ₁₆ of the picture start code indicated by '00000100 ₁₆ ' specified by the MPEG standard. If it is equal, it outputs binary signal 1. If it is not equal, it outputs binary signal 0. That is, when the bit streams 0 → 0 → 1 → 0 in 8-bit units are input as shown in the timing diagram shown in FIG. 6, the AND product 35 compares the binary signals 1 in all four comparators 31 to 34. FIG. The result signal is input and logical-operated to indicate that the picture start code is detected. Thus, when the picture start code is detected, the logical multiplication element 35 sets and outputs the picture start code detection signal (see the pic_start waveform in FIG. 6) to 1, or resets the picture start code detection signal to 0 and outputs it. . The picture start code detection signal is delayed and outputted in turn through the four flip-flops DFF4 to DFF7 (see the Fig. 6 pic_start3d waveform).

FIG. 4 is a detailed view showing the buffer delay time interval and the buffer input / output comparison unit 40 in the picture synchronization device 25 (see FIG. 2) of the present invention. As shown, the buffer delay time interval and the buffer input / output comparison unit 40 receives the bitstream image data input to the bit buffer 20 (see FIG. 2) and receives a first picture start code for detecting a picture start code. A detector 41 and a second picture start code detector 42 for receiving the bitstream video data output from the bit buffer 20 (see Fig. 2) and detecting the picture start code are provided. Here, the detailed configurations of the first picture start code detector 41 and the second picture start code detector 42 are as shown in FIG. In addition, a comparison unit 43 for comparing the buffer delay time interval (vbv_delay) with respect to the picture input to the bit buffer 20 and the buffer input / output time interval of the picture is provided. The comparator 43 counts a clock of a specific frequency to check a buffer delay time interval, and a picture start code is added by the first picture start code detector 41 and the second picture start code detector 42. Latches (L1, L2) and comparators (433, 434) for determining whether the input bitstream data and the output bitstream data of the bit buffer 20 are time intervals in the same picture by comparing the picture additional information which appears continuously when detected. ) The comparator 433 is connected to a count end signal generator 44 which generates a count end signal vbv_count_end based on a result of comparing the count value of the counter 431 with the buffer delay time interval vbv_delay. The count end signal generator 44 includes a D flip-flop (DFF8) for delaying the comparison result signal, an AND product 441 for performing logical AND operation on the state inversion of the comparison result signal and the delayed comparison result signal, and The D-type flip-flop DFF9 outputs the count end signal vbv_count_end by delaying the output of the AND device 441. The comparator 434 is connected to a buffer output start signal generator 45 for generating a buffer output start signal (vbv_pic_start) for the case where the buffer I / O pictures are the same. The buffer output start signal generator 45 includes a D flip-flop (DFF10) for delaying the comparison result signal, an AND (451) for performing logical AND operation on the state inversion of the comparison result signal and the delayed comparison result signal, And a D flip-flop DFF11 generated by the buffer output start signal vbv_pic_start by delaying the output of the AND product 451. The buffer output start signal generator 45 is sequentially connected with three D-type flip-flops DFF12 to DFF14 for delaying the buffer output start signal vbv_pic_start by 3 clocks.

In FIG. 4, a 29-bit bitstream output through the first picture start code detector 41 is input to the first latch L1, and the picture start code detection signal (Fig. 6 pic_start3d1 waveform) is a logical multiplication device ( 432). The AND device 432 receives the counter enable signal (Fig. 6 vbv_count_enable waveform) and inverts the state. The AND device 432 performs an AND operation on the input picture start code detection signal pic_start3d1 to input the enable signal of the first latch L1. output as (ena) Thus, the AND product 432 detects the picture start code and enables the first latch L1 when the counter enable signal vbv_count_enable is zero. Here, when the picture start code is detected, the 29-bit bitstream output from the first picture start code detector 41 has 10 bits of temporal_reference information and a value indicating the picture coding mode (picture type) (picture_coding_type). ) 3 bits and 16 bits of buffer delay time (vbv_delay). On the other hand, even when the picture start code is detected from the output of the bit buffer 20 by the second picture start code detector 42, a value indicating 10 bits of the screen order information (temporal_reference) and the picture coding mode (picture type) (picture_coding_type) ) A bitstream of 29-bit units consisting of 3 bits and 16 bits of buffer delay time (vbv_delay) is input to the second latch L2. At this time, the second latch L2 is enabled by the picture start code detection signal pic_start3d2 and latches the 29-bit bitstream. The second comparator 434 compares the outputs of the first latch L1 and the second latch L2 to determine whether the bitstream input to the bit buffer 20 and the output bitstream are the same picture. The reason for not comparing only the screen order information (temporal_reference) or the buffer delay time interval (vbv_delay) is because the screen order information (temporal_reference) or the buffer delay time interval (vbv_delay) of two consecutive pictures may be the same. For example, when one frame is encoded into two field pictures, the screen order information (temporal_reference) of the two pictures is the same. In this case, when the previous picture is a B picture, the next picture is also a B picture. And, there is a possibility that the buffer delay time interval (vbv_delay) of two consecutive random pictures may be the same at any time. Therefore, it is necessary to compare all of the screen order information (temporal_reference), the picture encoding mode (picture_coding_type), and the buffer delay time interval (vbv_delay) to distinguish that the picture starts to be output from the bit buffer 20. If the two latched 29-bit bitstreams in the second comparator 434 are the same, the input / output bitstreams of the bit buffer 20 are determined to be the same picture, and a comparison result signal of the binary signal 1 is output. Output the signal. The buffer output start signal generator 45 sets the buffer output start signal vbv_pic_start to 1 at the rising edge at which the output of the second comparator 434 becomes 1. That is, the flip-flop DFF10 receives the output of the second comparator 434 from the buffer output start signal generator 45 and outputs the result to the logical product 451 by one clock delay, and the logical product 451 is flipped. The output of the flop DFF10 is inverted in state to perform an AND operation on the output of the second comparator 434. The flip-flop DFF11 receives the logical product operation result and delays one clock to output the buffer output start signal (vbv_pic_start). The buffer output start signal vbv_pic_start is sequentially delayed by three clocks through three serially connected flip-flops DFF12 to DFF14. On the other hand, the counter 431 counts the 90 kHz clock by 1 and outputs the count value in 16 bit units. The first comparator 433 compares the count value with the buffer delay time interval (vbv_delay) of 16 bits of the 29-bit output of the first latch L1, and if the count value is equal to the buffer delay time interval, the high level signal of the binary signal 1 Outputs The count end signal generator 44 causes the count end signal vbv_count_end to be 1 at the rising edge at which the output of the first comparator 433 is 1. Here, the picture start code detection signal pic_start3d1 of the first picture start code detector 41 and the count end signal (vbv_count_end) of the count end signal generator 44 are inputted to the counter enable signal generator 50 of FIG. 5. do.

5 is a detailed diagram showing the counter enable signal generation unit 50 in the picture synchronization device 25 of the present invention. As shown in the drawing, the counter enable signal generation unit 50 feeds back the counter enable signal vbv_count_enable, the picture start code detection signal pic_start3d1 of the first picture start code detector 41, and the count end signal vbv_count_end. ) And a counter enable signal (vbv_count_enable) by inputting the output of the AND product 51 to the s terminal and the count end signal (vbv_count_end) to the r terminal. SR flip-flop (SRFF1) for outputting.

In FIG. 5, the logical multiplication element 51 of the counter enable signal generator 50 includes the counter enable signal vbv_count_enable before the clock input and the count end signal generated by the count end signal generator 44. The vbv_count_end waveform of FIG. 6 is inverted, and the picture start signal detection signal (Fig. 6 pic_start3d1 waveform) delayed outputted from the first picture start code detector 41 is logically multiplied to receive the s of the flip-flop SRFF1. Output to the terminal. The count end signal vbv_count_end is also input to the r terminal of the flip-flop SRFF1. Here, if the counter enable signal vbv_count_enable is 0, it means that the buffer count for the next picture may be started. In this case, the picture start code detection signal pic_start3d1 is 1 and the count end signal (vbv_count_end) is set. Is 0, 1 is applied to the s terminal of the flip-flop SRFF1 to control the enable state of the counter 431 and the first latch L1 shown in FIG. 4 in the flip-flop SRFF1. A valid counter enable signal (vbv_count_enable) is applied to. The flip-flop SRFF1 disables the counter enable signal when a valid count end signal (vbv_count_end) is applied to the r terminal. The counter enable signal vbv_count_enable is input to the counter 431 and the logical product 432 of FIG. 4, and also to the buffer output picture delay signal generator 70 of FIG. 7.

4, the counter enable signal vbv_count_enable generated by the counter enable signal generation unit 50 of FIG. 5 is input to the enable terminal ena, and the state is reversed through the inverter INV to clear the terminal. The counter 431, which is inputted at (clr), counts a clock generated at 90 Hz while a valid counter enable signal (vbv_count_enable) is input and counts a buffer delay time interval (vbv_delay) in picture units. In addition, the logical multiplication device 432 that receives the counter enable signal vbv_count_enable inverts the state and performs a logical multiplication with the picture start code detection signal pic_start3d1 of the first picture start code detector 41 to perform the first latch ( The first latch L1 is disabled while the counter 431 counts by applying to the enable terminal ena of L1.

Fig. 7 is a detailed diagram showing the buffer output picture delay signal generation unit 70 in the picture synchronization device 25 of the present invention. As shown, the buffer output picture delay signal generator 70 includes the buffer output start signal vbv_pic_start generated by the buffer output start signal generator 45 of FIG. 4 and the counter enable signal generator 50 of FIG. 5. Logical multiplying the logic enable element 71 which inverts the state of the counter enable signal (vbv_count_enable) generated by the logic operation, and the state of the counter enable signal (vbv_count_enable) and the buffer output start signal (vbv_pic_start3d) delayed by three clocks. Comprising a logical multiplication device 72, and the two logical multiplication devices (71, 72) connected to the s terminal and r terminal is composed of a flip-flop (SRFF2) for outputting the buffer output picture delayed signal (delayed_vbv) .

In FIG. 7, the logical product element 71 of the buffer output picture delay signal generator 70 receives the buffer output start signal (vbv_pic_start) generated by the buffer output start signal generator 45 of FIG. The counter enable signal generator 50 receives the counter enable signal vbv_count_enable, and the state is reversed. The AND device 71 performs an AND operation on the buffer output start signal vbv_pic_start and the state enable counter enable signal vbv_count_enable, and applies it to the s terminal of the flip-flop SRFF2. The AND device 72 performs an AND operation on the counter-inverted signal enable signal vbv_count_enable and the buffer output start signal vbv_pic_start3d delayed by three clocks, and applies it to the r terminal of the flip-flop SRFF2. Thus, the flip-flop SRFF2 maintains and outputs the buffer output picture delayed signal delayed_vbv as 0 while the counter enable signal vbv_count_enable is 1, and outputs the counter enable signal vbv_count_enable 0 and the buffer output start signal If vbv_pic_start) is 1, it is set to 1 and output. On the other hand, the flip-flop SRFF2 resets the buffer output picture delayed signal delayed_vbv to 0 after three clocks, that is, when the three clock delayed buffer output start signal vbv_pic_start3d becomes one. Here, the buffer output picture delayed signal delayed_vbv is a signal indicating whether the detected picture among the bit stream data currently output from the bit buffer 20 is delayed, and is applied to the skip signal generator 120 of FIG. 12.

8 is a detailed diagram showing the system clock count value detection unit 80 in the picture synchronization device 25 of the present invention. As shown, the system clock count value detection unit 80 is composed of a plurality of latches L3 and L4 for detecting the system clock count value stc_count_value at the count end time and the buffer output start time.

In FIG. 8, the third latch L3 receives the count end signal vbv_count_end generated by the count end signal generator 44 through the enable terminal ena and ends the count when the count end signal vbv_count_end becomes 1. Latches and outputs a 33-bit system clock count value (stc_count_value) input from the outside. The fourth latch L4 receives the buffer output start signal vbv_pic_start generated by the buffer output start signal generator 45 as an enable terminal ena and has a bit buffer 20 at which the buffer output start signal vbv_pic_start becomes 1. ) Outputs by latching the system clock count value (stc_count_value) in 33-bit units inputted from the outside when the corresponding picture is output. The system clock count value (vbv_end_stc_value) (vbv_pic_stc_value) respectively output from the third latch L3 and the fourth latch L4 is output to the offset calculator 90 of FIG. 9.

9 is a detailed view showing the offset calculator 90 in the picture synchronization device 25 of the present invention. As shown, the offset calculator 90 subtracts the system clock count value (vbv_end_stc_value) at the end of the count from the system clock count value (vbv_pic_stc_value) at the buffer output start point and calculates the difference with the first adder 91. And an absolute value converter 92 which takes an absolute value of the difference. The absolute value converter 92 is configured to be coupled to a second adder 93 which obtains an offset by subtracting the absolute difference abs_diff from a preset threshold.

In FIG. 9, the first adder 91 subtracts the system clock count value (vbv_end_stc_value) at the end of count from 33 bits from the system clock count value (vbv_pic_stc_value) at the start of buffer output in 33 bit units to obtain the difference. The difference is output to the absolute value converter 92 with 34 bits including a sign bit. The absolute value converter 92 receives a difference value in units of 34 bits, takes an absolute value, and outputs an absolute difference value in units of 33 bits to the second adder 93. The second adder 92 outputs a 34-bit offset including a sign bit by subtracting an absolute difference value abs_diff in 33-bit units input from a preset 33-bit unit threshold. Here, when the sign bit of the offset is 1, it means that the delay degree of the picture output from the bit buffer 20 is larger than the preset threshold.

10 is a detailed view of the hold signal generator 100 in the picture synchronization device 25 of the present invention. As shown, the hold signal generator 100 may include a buffer output start signal (vbv_pic_start) generated by the buffer output start signal generator (see FIG. 4) 45 and a counter enable signal generator (see FIG. 5) (50). A logical multiplication device 101 for receiving a counter enable signal (vbv_count_enable) generated from the input signal, receiving a count end signal (vbv_count_end) generated from the count end signal generator 44, and performing logical multiplication by inverting the state; A flip that receives the output of the logical multiplication device 101 as the s terminal, receives the count end signal (vbv_count_end) generated by the count end signal generator 44 as the r terminal, and outputs a hold signal (hold_vld) for holding decoding. It consists of a flop SRFF3.

Referring to the operation of the hold signal generation unit 100 configured as described above with reference to the timing diagram of FIG. 11, first, the AND device 101 performs a buffer output start signal (vbv_pic_start) according to an arbitrary clock (sclk). And the counter enable signal (vbv_count_enable) are input. The logical multiplication device 101 receives the count end signal vbv_count_end and inverts the state, and logically multiplies the counted inverted count end signal vbv_count_end, the input buffer output start signal vbv_pic_start, and the counter enable signal vbv_count_enable. The calculation is performed to the s terminal of the flip-flop SRFF3. The count end signal vbv_count_end is also input to the r terminal of the flip-flop SRFF3. Thus, the flip-flop SRFF3 is shown in FIG. 11 while the buffer buffer time interval vbv_delay is counted, that is, while the counter enable signal vbv_count_enable is 1 and the count end signal vbv_count_end is 0. When it is detected that the picture of the corresponding count is output in step 20), that is, when the buffer output start signal (vbv_pic_start) becomes 1, the bitstream data of the corresponding picture is quickly output from the bit buffer 20. In VLD, the hold signal hold_vld is set to 1 so that the decoding operation is suspended. The flip-flop SRFF3 resets the hold signal hold_vld to 0 when the count for the buffer delay time interval vbv_delay ends (vbv_count_end = 1) to set the decoding time in picture units.

12 is a detailed view of the skip signal generator 120 in the picture synchronization device 25 of the present invention. As illustrated, the skip signal generator 120 receives a plurality of flip-flops DFF15 and DFF16 that delay and output the code bits of the offset obtained by the offset calculator 90 of FIG. 9, and the flip-flop DFF15. Delays the output of the logical AND (AND) 121 and the logical AND (121) logic AND operation of the offset code bit (offset_sign_bit) and the buffer output picture delayed signal (delayed_vbv) output from DFF16) by one clock delay. And a flip-flop DFF17 that is output as a skip signal skip_vld.

Referring to the operation of the skip signal generator 120 configured as described above with reference to the timing diagram of FIG. 12, first, the flip-flop DFF15 is the bit code of the offset calculated by the offset calculator 90 of FIG. The offset_sign_bit is input and delayed by one clock to output the logical product element 121 and the flip-flop DFF16. The flip-flop DFF16 delays the one-delayed offset code bit by one clock and outputs the result to the logical product element 121. The logical product element 121 receives the two-clock delayed offset code bit and inverts the state, and logically inverts the two-clock delayed offset code bit and the one-clock delayed offset code bit and the buffer output picture delay signal (Fig. 13 delayed_vbv waveform). Multiply and output the flip-flop (DFF17). Here, the logical multiplication device 121 outputs the skip signal skip_vld to 1 at the rising edge of the offset code bit and outputs the skip signal to 1 at the rising edge of the offset code bit. This speeds up the decoding time of delayed pictures by allowing them to be discarded without decoding.

As described above, the present invention relates to an apparatus for synchronizing a picture of an MPEG video decoder. Even if an error occurs in a bitstream data input to the video decoder, it is decoded abnormally or decoded quickly or slowly due to hardware structure of the video decoder. The bitbuffer state can be adjusted so that overflow or underflow does not occur in the bitbuffer.

Claims (14)

In the MPEG video decoder that receives the bitstream video data of a constant bit rate and decodes the video output to the decoded video data, A bit buffer for receiving and outputting bitstream image data; It is connected to the bit buffer in parallel to receive the input and output bitstream image data of the bit buffer, and receives a system clock count value and a predetermined clock that counts the synchronization information that is the reference for decoding with a predetermined clock unit and a predetermined picture unit When the bitstream video data starts to be input to the bit buffer, counting the buffer delay time interval of the picture is generated, and before the counting ends, the decoding stop signal is generated until the counting ends when the picture is output from the bit buffer. Picture synchronization means for delaying a predetermined threshold value after the end and generating a decoding skip signal when the picture is output from the bit buffer to synchronize and decode the picture unit; And Decoding means for reading and decoding bitstream image data from the bit buffer and stopping decoding or discarding the bitstream image data of the picture without decoding according to the decoding stop signal and the decoding skip signal generated by the picture synchronization means. Picture synchronization device for MPEG video decoder. The apparatus of claim 1, wherein the picture synchronization means A picture start code detector for detecting a picture start code from the input and output bitstream data of the bit buffer; A buffer delay time interval for generating a count end signal and a buffer output start signal by comparing a buffer delay time interval of bitstream data for any picture input to the bit buffer with an input / output time interval of the bit buffer for the picture; and Buffer input / output comparison unit; A counter enable signal generator for receiving a feedback enable signal, a picture start code detection signal for the input bitstream data of the bit buffer, and the count end signal and generating a counter enable signal; A buffer output picture that receives the buffer output start signal, the counter enable signal, and the buffer output start signal delayed by a predetermined clock, and generates a buffer output picture delay signal indicating whether a picture corresponding to the output bitstream of the bit buffer is delayed A delay signal generator; A system clock count value that receives a system clock count value from an external source, receives the count end signal and the buffer output start signal, and detects the system clock count value at the end of the count and the system clock count value at the start of the buffer output. Detection unit; The system clock count value of the detected count end point and the system clock count value of the buffer output start point are input to obtain an absolute difference value between the two system clock count values, and the offset between the absolute difference value and the preset threshold value is calculated. An offset calculator; A hold signal generator which receives the buffer output start signal, the count enable signal and the count end signal, and generates a hold signal for stopping decoding until the count ends when the buffer output starts before the count ends; And And a skip signal generator which receives the buffer output picture delay signal and the code bit of the offset and generates a skip signal according to the sign of the offset when the buffer output is delayed. Device. 3. The picture start code detection unit of claim 2, wherein the picture start code detection unit A plurality of flip-flops that receive bitstream data input to the bit buffer in predetermined bit units and sequentially delay and output the bitstream data; A plurality of comparators for detecting a picture start code by comparing the input constant bit data and the constant bit data output from the plurality of flip-flops with data preset by a picture start code according to MPEG standards; A first logical element configured to perform an AND operation on the comparison result signal of the comparator and output a picture start code detection signal indicating whether a picture start code is detected; And A first picture start code detector comprising a plurality of flip-flops for sequentially delaying and outputting a picture start code detection signal of the first logical element, and the same as the first picture start code detector, which is output from the bit buffer And a second picture start code detector for detecting a picture start code with respect to bitstream data. The method of claim 3, wherein the buffer delay time interval and the buffer input and output comparison unit Comparing the picture start signal detection signals of the first picture start code detector and the second picture start code detector with the constant bit data appearing after the picture start code, the input and output bitstream data of the bit buffer are identical to each other. A comparison unit for counting a clock of the same frequency used in the system clock count value and comparing the count value with a buffer delay time interval defined in some of the predetermined bits; And A buffer output start signal generator for generating a buffer output start signal if the input and output pictures of the bit buffer are identical as a result of the comparison of the comparison unit; A count end signal generator for generating a count end signal if the count value equals a defined buffer delay time interval as a result of the comparison of the comparator; And And a plurality of flip-flops for sequentially delaying and outputting the buffer output start signal. The method of claim 4, wherein the comparison unit An inverter that receives the counter enable signal and reverses its state; The counter enable signal is input to the enable terminal, the counter enable signal inverted state by the inverter is input to the clear terminal, and the clock of the same frequency used for the system clock count value is counted and counted in the enable state. A counter for outputting a value; Receiving a counter enable signal and inverting the state; performing a logical AND operation on the picture start code detection signal delayed by the first picture start code detector to output an enable signal to the enable terminal of the first latch; Logical multiplication device; A first latch for latching and outputting predetermined bit data subsequent to the picture start code detected by the first picture start code detector according to the enable signal of the second logical element; A second picture output signal being delayed output from the second picture start code detector as an enable terminal; a second bit for latching and outputting constant bit data subsequent to the picture start code detected by the second picture start code detector; Latch; A first comparator for comparing whether the buffer delay time interval is equal by comparing the count value of the counter with some data among the predetermined bits latched in the first latch; And And a second comparator for checking whether the constant bit data latched in the first latch and the constant bit data latched in the second latch check whether the same picture is the same. 6. The method of claim 5, wherein the constant bit data latched in the first latch and the second latch comprises: 10-bit screen order information (temporal_reference), 3-bit picture encoding mode (picture type), and 16-bit unit. A picture synchronization device of an MPEG video decoder, characterized in that it is a buffer delay time interval (vbv_delay). The method of claim 5, wherein the count end signal generator A flip-flop for delaying and outputting the comparison result signal of the first comparator; A count end signal valid when the count result is equal to the buffer delay time interval in the constant bit data by performing a logical multiplication with the comparison result signal of the first comparator, by inverting the comparison result signal delayed by the flip-flop. A third logical element for outputting a; And And a flip-flop for delaying and outputting the count end signal of the third logical element. The method of claim 5, wherein the buffer output start signal generator A flip-flop for delaying and outputting the comparison result signal of the second comparator; Inverting the comparison result signal delayed output from the flip-flop state, and the result of performing a logical multiplication with the comparison result signal of the second comparator to output a valid buffer output start signal when the input and output bitstream data of the bit buffer A fourth logical element; And And a flip-flop for delaying and outputting the buffer output start signal of the fourth logical element. The method of claim 7, wherein the counter enable signal generation unit A fifth logical element configured to receive a feedback of the feedback enable signal and the count end signal and invert a state thereof, and to logically multiply the result with a picture start code detection signal delayed by the first picture start code detector; And Picture start code in the bitstream data of the picture inputted to the bit buffer in the buffer count start enable state for the next picture by receiving the output of the fifth logical element as the s terminal and the count end signal as the r terminal. And a flip-flop for generating a counter enable signal until counting ends when the signal is detected. The method of claim 9, wherein the buffer output picture delay signal generation unit A sixth logical element receiving the counter enable signal and inverting the state and performing an AND operation on the buffer output start signal; A seventh logical element that receives the counter enable signal and inverts its state, and performs an AND operation on the picture start code detection signal delayed by the second picture start code detector; And A picture of an MPEG video decoder comprising a flip-flop which receives the output of the sixth logical element as an s terminal and receives the output of the seventh logical element as an r terminal to generate a buffer output picture delay signal. Synchronizer. The system of claim 7 or 8, wherein the system clock count value detection unit A third latch configured to receive the count end signal as an enable terminal and to latch and output a system clock count value input from the outside at the end of count; And And a fourth latch for receiving the buffer output start signal as an enable terminal and latching and outputting a system clock count value inputted from the outside at the buffer output start point of the buffer output start signal. The method of claim 11, wherein the offset calculation unit A first adder for subtracting the system clock count value output from the third latch from the system clock count value output from the fourth latch to obtain a difference; An absolute value converter for outputting an absolute difference value by taking an absolute value with respect to the difference value obtained by the first adder; And And a second adder for subtracting an absolute difference value of the absolute value converter from a preset threshold to obtain an offset. The method of claim 8 or 9, wherein the hold signal generating unit An eighth logical element that receives the count end signal and inverts its state, and receives the buffer output start signal and the counter enable signal and performs an AND operation; And A flip-flop which receives the output of the eighth logical element as the s terminal and receives the count end signal as the r terminal and generates a hold signal for stopping decoding the picture output from the bit buffer before the end of the count. And a picture synchronization device for an MPEG video decoder. The skip signal generator of claim 10 or 12. A plurality of flip-flops for delaying and outputting the offset code bits; Inverts the two-clock delayed code bits outputted from the plurality of flip-flops, and performs an AND operation on the one-bit delayed code bit and the buffer output picture delay signal and offsets the pictures delayed from the bit buffer. A ninth logical element for generating a skip signal to decode the picture at a predetermined edge portion of the bit; And And a flip-flop for delaying and outputting a skip signal output from the ninth logical element.