KR19980037921A - Sensing Amplifier Circuit of Nonvolatile Semiconductor Memory Device - Google Patents

Abstract

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a sensing amplifier circuit of a nonvolatile semiconductor memory device for securing an effective sensing margin during a program verifying operation. The present invention relates to a cell for storing data. A first pair of bitlines electrically connected to the array; A second bit line pair respectively corresponding to the first bit line pair; First precharge and equalization means for precharging the first pair of bit lines to a predetermined level in response to first and second signals applied from the outside; Separating means for electrically insulating said first bit line pair and said second bit line pair in response to third and fourth signals applied from the outside; First sensing amplification means for sensing a voltage difference of a predetermined level charged in the first bit line pair, amplifying the voltage difference, and transferring the amplified signal to the second bit line pair; Second sense amplifying means for detecting and amplifying a voltage difference of a predetermined level transferred to the second bit line pair through the first sense amplifying means; Second precharge and equalization means for precharging and equalizing the second bit line pair to a predetermined level in response to a fifth signal and a sixth signal applied from the outside; In response to the seventh signal applied from the outside, discharge means for discharging the first and second bit line pairs sufficiently to the ground voltage during the program verify operation.

Description

(A circuit of sensing and amplifing of non volatile semiconductor memory device)

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a sensing amplifier circuit of a nonvolatile semiconductor memory device for securing an effective sensing margin during a program verifying operation.

1 is a block diagram illustrating a configuration of a sense amplifier circuit of a nonvolatile semiconductor memory device according to the prior art.

The nonvolatile semiconductor memory device according to the related art shown in FIG. 1 includes a cell array 10, a first precharge and equalizer 30, a separator 40, a first sense amplifier 50, and a second sense. It consists of an amplification part 60 and the precharge and equalization part 70. The cell array 10 is an area for storing data, and first and second sub bit lines SBL and SBLB are electrically connected to the cell array 10. Insulation means 20 for separating the bit line in the cell array 10 and the bit line of the amplifier stage are connected. The first precharge and equalizer 30 precharges and equalizes the first and second sub-bit lines SBL and SBLB to a predetermined voltage level before sensing data stored in the cell array 10. It is for. A precharge PMOS transistor M5 and a second precharge enabled in response to a first precharge signal PiSBLPBe to precharge the first and second sub-bit lines SBL and SBLB to a predetermined voltage level. A precharge PMOS transistor M6 is enabled in response to the charge signal PiSBLPBo. The PMOS transistor M17 is enabled in response to an equalization signal PiSBLEQ applied from the outside to equalize the first bit line pairs SBL and SBLB precharged to a predetermined level.

The first and second latch bit lines LBL and LBLB corresponding to the first and second sub bit lines SBL and SBLB are respectively electrically insulated through the separating means 40. The separating means 40 isolates and insulates the sub and latch bit lines SBL, SBLB, LBL, and LBLB in response to the first and second separation signals PiISOe and PiISOo applied from the outside, and an NMOS transistor. (M8, M9). The NMOS transistor M8 has a gate connected to a signal line 7 to which the first isolation signal PiISOe is applied, and a channel is connected between the first sub bit line SBL and the first latch bit line LBL. . The NMOS transistor M8 has a gate connected to a signal line 8 to which the second isolation signal PiISOo is applied, and a channel is connected between the second sub bit line SBL and the second latch bit line LBLB. .

The first sense amplifier 50 directly senses the difference between the voltage levels charged in the first and second sub-bit lines SBL and SBLB, respectively, and amplifies the first and second latch bit lines. Pass in (LBL, LBLB). The first sense amplifier 50 operates in response to a sense enable signal PiSAE and a sense amplifier voltage VSA applied from the outside, and includes NMOS transistors M10 through M13. The NMOS transistors M10 and M11 are connected in series between the first latch bit line LBL and the signal line 10 to which the sense amplifier voltage VSA is applied, and the first sub bit line SBL is connected in series. Gates are connected to signal lines 9 to which the sense enable signal PiSAE is applied. Each of the NMOS transistors M12 and M13 is connected in series between the second bit line LBL and the signal line 10 to which the sense amplifier voltage VSA is applied, and the second sub bit line SBLB and the second sub bit line SBLB are connected in series. Gates are respectively connected to the signal lines 9 to which the sense enable signal PiSAE is applied.

The second sense amplifier 60 detects and amplifies a difference between voltage levels transmitted to the first and second latch bit lines LBL and LBLB, respectively, and latches the NMOS transistors. (M14, M15) and PMOS transistors (M16, M17). The second precharge and equalization means 70 precharges and equalizes the first and second latch bit lines LBL and LBLB to a predetermined voltage level before sensing data stored in the cell array 10. It is to. PMOS transistors M18 and M19 that are enabled in response to a first equalization signal PiSAEQB to precharge the first and second latch bit lines LBL and LBLB to a predetermined voltage level. An NMOS transistor M20 is enabled in response to the second equalization signal PiSAEQ to equalize the second pair of bit lines LBL and LBLB.

FIG. 2 is a timing diagram of an operation according to the prior art, and FIG. 3 is a diagram illustrating a development state of transistors of the first sensing amplification unit during program verification according to the prior art. Referring to Figures 1 to 3, the program verification operation according to the prior art will be described.

In general, in a nonvolatile semiconductor memory device, a program refers to a process of making a threshold voltage of a cell positive. In contrast, erasing refers to a process of making a threshold voltage of a cell negative. In general, program verification refers to determining whether a program is performed by applying a '0' volt to a gate terminal of a programmed cell and determining the amount of current through the channel of the cell. The conventional program verification operation is described as follows.

First, when the signal PIPGMVFB indicating that the program verification is started is enabled, the first and second sub bit lines SBL and SBLB of the cell array stage and the first and second latch bit lines LBL, of the sense amplifier stage. LBLB) is precharged to a predetermined level. At this time, the first and second sub-bit lines SBL and SBLB on the side of the cell array 10 are PMOS of the first precharge and equalization means 30 by control signals PiSBLPe and PiSBLPo applied from the outside. Transistors M5 and M6 are turned on. As a result, the first and second sub-bit lines SBL and SBLB are precharged to the power supply voltage Vcc through the signal line 3 to which the precharge voltage VSBL of the power supply voltage Vcc is applied. The first and second latch bit lines LBL and LBLB of the sense amplifier stage are connected to the PMOS transistors M18 and M19 of the second precharge and equalization means 70 by a control signal PiSAEQB applied from the outside. Is turned on. Accordingly, the first and second latch bit lines LBL and LBLB are precharged to the threshold voltage level Vtp of the transistors.

Thereafter, the corresponding word line is enabled to select any memory cell of the cell array 10 electrically connected to the first sub bit line SBL. As a result, the first sub-bit line SBL is developed. Here, the development refers to a phenomenon in which the precharged bit line level is discharged by the cell current and its level drops. In addition, a reference cell is automatically selected to the opposite bit line of the second sense amplification means 60, and the reference cell is the amount of current when '0' volts are biased to the gates of the programmed and erased cells. Refers to a cell adjusted in half. Thereafter, when the first and second sub-bit lines SBL and SBLB develop during a predetermined period, an operation of transferring the level of development of the first sub-bit line SBL to the first latch bit line LBL. This is done. To this end, the NMOS transistors M11 and M13 of the first sense amplifier 50 are turned on while the control signal PiSAE applied from the outside is enabled in the form of a pulse.

That is, the one having the higher voltage level among the first and second sub-bit lines SBL and SBLB turns on any one of the NMOS transistors M10 and M12 of the first sense amplifier 50. It will be made. As a result, the precharge signal VSA applied to the power supply voltage Vcc is transmitted to the second sense amplifier 60 of the latch type, and a sub bit line having a low level is connected to the first sense amplifier 50. It will not turn on the transistor and will not deliver it. Referring to FIG. 2, if there is a cell programmed in the first sub bit line SBL, the first latch bit line LBL is latched with a power supply voltage, and the second latch bit line LLBB is latched with a ground voltage. On the contrary, when the program is less, there is less development than the reference cell so that the ground voltage is latched to the second sense amplifier 60 through the first sense amplifier 50. The program verification was performed through the above process.

However, according to the sensing amplification circuit of the nonvolatile semiconductor memory device as described above, the first and second latch bit lines LBL and LBLB of the sensing amplification stage are precharged at a predetermined level in the program verifying operation. Through the PMOS transistors M18 and M19 of the two precharge and equalization means, the ground voltage level is not completely transferred to the latch bit lines, but is precharged to its threshold voltage level Vtp. As a result, when the voltage level charged in the first sub bit line SBL is transferred to the first latch bit line corresponding thereto, the amount of current is increased by the body effect of the NMOS transistors M10 and M12 of the first sensing amplification means. Decreases. In addition, the threshold voltage of the transistors M10 and M12 is relatively increased due to a body effect, thereby sensing the voltage level of the existing developed first and second sub-bit lines SBL and SBLB. The difficulty in doing so has caused a problem in that the sensing margin and the sensing speed decrease.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to provide a sense amplification circuit of a nonvolatile semiconductor memory device for securing an effective sensing margin during a program verifying operation.

1 is a block diagram showing a configuration of a sense amplifier circuit of a nonvolatile semiconductor memory device according to the prior art;

2 is an operation timing diagram according to the prior art;

3 shows a state in which the transistors of the first sense amplifying means are developed during program verification;

4 is a block diagram showing a configuration of a sense amplifier circuit of a nonvolatile semiconductor memory device according to the present invention;

FIG. 5 is a view illustrating a state in which transistors of the first sense amplifier are develped during program verification;

* Explanation of symbols on the main parts of the drawings

10 cell array 30 first precharge and equalization means

40 separation means 50 first detection amplification means

60 second sensing amplification means 70 second precharge and equalization means

80: discharge means

According to one aspect of the present invention for achieving the above object, a first bit line pair electrically connected to a cell array for storing data; A second bit line pair respectively corresponding to the first bit line pair; First precharge and equalization means for precharging the first pair of bit lines to a predetermined level in response to first and second signals applied from the outside; Separating means for electrically insulating said first bit line pair and said second bit line pair in response to third and fourth signals applied from the outside; First sensing amplification means for sensing a voltage difference of a predetermined level charged in the first bit line pair, amplifying the voltage difference, and transferring the amplified signal to the second bit line pair; Second sense amplifying means for detecting and amplifying a voltage difference of a predetermined level transferred to the second bit line pair through the first sense amplifying means; Second precharge and equalization means for precharging and equalizing the second bit line pair to a predetermined level in response to a fifth signal and a sixth signal applied from the outside; And discharge means for sufficiently discharging the first and second bit line pairs to a ground voltage in a program verifying operation in response to a seventh signal applied from the outside.

In this embodiment, the discharge means is constituted by a PMOS transistor enabled in response to the seventh signal synchronized with the sixth signal.

Such a circuit not only improves the sensing margin by precharging the bit lines of the sense amplifier stage to the ground voltage sufficiently, but also prevents the sensing loss and the reduction of the sensing speed.

Hereinafter, reference will be made in detail with reference to FIGS. 4 to 5 according to an embodiment of the present invention.

In Figs. 4 to 5, the same reference numerals are given to the components having the same functions as the components shown in Figs.

The present invention is to sufficiently discharge the first and second latch bit lines LBL and LBLB of the sense amplifier stage to the ground voltage Vss level at the low level in the program verify mode. That is, when precharging in synchronization with the PiSAEQ signal, which is a main signal for precharging the first and second latch bit lines LBL and LBLB, during program verification through the PMOS transistor M21 of the discharge means according to the present invention. The first and second latch bit lines LBL and LBLB are discharged to the ground voltage level Vss through the transistor M21. Therefore, through this implementation, the NMOS transistors M10 and M12 of the first sensing amplification means do not look at the body effect and have a better sensing margin, and also prevent the reduction of the sensing loss and the sensing speed in the related art. Can be.

4 is a block diagram illustrating a configuration of a sense amplifier circuit of a nonvolatile semiconductor memory device according to an exemplary embodiment of the present invention.

In the sense amplifier circuit according to the present invention shown in FIG. 4, the cell array 10, the first precharge and equalization means 30, the separation means 40, the first sense amplifier 50, the second sense amplifier means (60), the second precharge and equalization means (70), and the dossier means (80). First bit line pairs SBL and SBLB are electrically connected to the cell array 10 for storing data. The second bit line pairs LBL and LBLB respectively corresponding to the first bit line pairs SBL and SBL are separated through the separating means 40. The first precharge and equalization means 30 precharges the first bit line pair SBL and SBLB to a predetermined level in response to precharge signals PiSBLPe and PiSBLPo applied from the outside. The separating means 40 electrically connects the first bit line pairs SBL and SBLB and the second bit line pairs LBL and LBLB in response to control signals PIISOe and PIISOo applied from the outside. Insulate The first sensing amplification means 50 senses a voltage difference of a predetermined level charged in the first bit line pairs SBL and SBLB, respectively, and amplifies the voltage difference to transfer the voltage difference to the second bit line pairs LBL and LBLB. .

The second sense amplifier 60 detects and amplifies a voltage difference of a predetermined level transferred to the second bit line pair LBL and LBLB through the first sense amplifier 40. The second precharge and equalization means 70 precharges and equalizes the second bit line pair LBL and LBLB to a predetermined level in response to precharge signals PISAEQB and PiSAEQ applied from the outside. . In addition, the discharge means 80 discharges the first and second bit line pairs LBL and LBLB to a sufficient ground voltage Vss during a program verifying operation in response to a control signal PiISOSC applied from the outside. It is responsible for charging. Here, the discharge means 80 includes a PMOS transistor M21 enabled in response to the control signal PiSOSC synchronized with the precharge signal PiSAEQB.

FIG. 5 is a diagram showing the development of transistors of the first sense amplifying means during program verification according to a preferred embodiment of the present invention. 4 to 5, the program verification operation according to the present invention will be described. First, when the signal PIPGMVFB indicating that the program verification is started is enabled, the first and second sub bit lines SBL and SBLB of the cell array stage and the first and second latch bit lines LBL, of the sense amplifier stage. LBLB) is precharged to a predetermined level. At this time, the first and second sub-bit lines SBL and SBLB on the side of the cell array 10 are PMOS of the first precharge and equalization means 30 by control signals PiSBLPe and PiSBLPo applied from the outside. Transistors M5 and M6 are turned on. As a result, the first and second sub-bit lines SBL and SBLB are precharged to the power supply voltage Vcc through the signal line 3 to which the precharge voltage VSBL of the power supply voltage Vcc is applied.

The first and second latch bit lines LBL and LBLB of the sense amplifier stage are connected to the PMOS transistors M18 and M19 of the second precharge and equalization means 70 by a control signal PiSAEQB applied from the outside. Is turned on. Accordingly, the first and second latch bit lines LBL and LBLB are precharged to the threshold voltage level Vtp of the transistors. At this time, the control signal (synchronized to the control signal PiSAEQ applied to the first and second precharge and equalization means 70 to the gate terminal of the PMOS transistor M21 of the discharge means 80 according to the present invention) PiISOSC) is applied. Accordingly, the transistor M21 is turned on so that the first and second latch bit lines LBL and LBLB can be completely discharged to the ground voltage, that is, precharged to a desired level of '0'V. It became. Thereafter, the verification operation is performed through the same process as in the prior art. Accordingly, the body effect of the tenth and eleventh NMOS transistors M10 and M11 is eliminated when the voltage difference between the first and second sub-bit lines SBL and SBLB is sensed through the first sense amplifier 50. As a result, the threshold voltage can be prevented from rising. As a result, according to the conventional body effect of the transistors (M10, M12) of the first sense amplification means 50 it can be prevented that the sensing is not made.

As described above, when the program verification is performed through the PMOS transistor of the discharge means according to the present invention, the transistor is driven through the transistor when the bit line is precharged in synchronization with the PiSAEQ signal, which is a main signal that precharges the first and second latch bit lines. The first and second latch bit lines are discharged to the ground voltage level. Therefore, through this implementation, the NMOS transistors of the first sensing amplification means do not look at the body effect and have a better sensing margin, and also prevent the reduction of the sensing loss and the sensing speed in the related art.

Claims (2)

First bit line pairs SBL and SBLB electrically connected to a cell array 10 for storing data; Second bit line pairs LBL and LBLB respectively corresponding to the first bit line pairs SBL and SBL; First precharge and equalization means 30 for precharging the first pair of bit lines SBL and SBLB to a predetermined level in response to externally applied first and second signals PiSBLPe and PiSBLPo; ; Separation means for electrically insulating the first bit line pairs SBL and SBLB and the second bit line pairs LBL and LBLB in response to externally applied third and fourth signals PiISOe and PiISOo. 40; First sensing amplification means 50 for sensing a voltage difference of a predetermined level charged in the first bit line pairs SBL and SBLB, amplifying the voltage difference, and transferring the voltage difference to the second bit line pairs LBL and LBLB; ; Second sense amplification means (60) for sensing and amplifying a voltage difference of a predetermined level transferred to the second bit line pair (LBL, LBLB) through the first sense amplification means (40); Second precharge and equalization means for precharging and equalizing the second bit line pair LBL and LBLB to a predetermined level in response to a fifth signal PiSAEQB and a sixth signal PiSAEQ applied from the outside. 70 and; The discharge means 80 for discharging the first and second bit line pairs LBL and LBLB to the ground voltage Vss sufficiently during the program verify operation in response to the seventh signal PiISOSC applied from the outside. Detection amplifier circuit of a nonvolatile semiconductor memory device including a. The method of claim 1, And said discharge means (80) comprises a PMOS transistor (M21) enabled in response to said seventh signal (PiSOSC) synchronized with said sixth signal (PiSAEQ).