KR19980037643A - Transmission method of DM controller - Google Patents

Abstract

The present invention relates to a main computer, and in particular, in a direct memory access (DMA) transmission method of an input / output processor, even a data that is not aligned in units of 64 bytes does not necessarily need to be transmitted by the CPI, but is processed by the DM itself. It is an object of the present invention to provide a transmission method of a DM controller such that a single transmission can be performed. The above object is a first step of determining whether the data is aligned in a predetermined byte unit when a system address is input; A second step of performing block transmission and single transmission if it is determined that the alignment is made by a predetermined byte unit by the first process, and performing a single transmission until the alignment is performed by a predetermined byte unit if not aligned by a predetermined byte unit; If the system address is arranged in a predetermined byte unit during the second process, the process is performed by including a third process of performing block transmission and single transmission accordingly.

Description

Transmission method of DM controller

The present invention relates to a main computer, and in particular, in a direct memory access (DMA) transmission method of an input / output processor, even a data that is not aligned in units of 64 bytes is processed by the DM itself without performing a single transmission by the CPI. The present invention relates to a transmission method of a DM controller such that a single transmission can be performed.

In general, as shown in FIG. 1, the main computer records data stored in the internal memory 200 of the main computer on various recording media (for example, a hard disk, a magnetic disk, a magnetic tape, etc.) or a peripheral device (for example, a console). , A modem, a printer, etc.) to display or to transmit over a long distance, or to transmit over a bus in a relatively short distance, the microprocessor unit 100 controls the memory 200 to upload data on the system bus 300.

If the data loaded on the system bus 300 is recorded through the recording medium 500, the input / output processor 400 converts the data into a form of data suitable for recording and uploads the data on the SCSI-2 bus. By placing them, they are recorded on each recording medium, i.e., a hard disk or a magnetic tape.

In addition, when displaying the data loaded on the system bus 300, the SCM 600 is displayed through the printer or console of the peripheral device 800, and when the long distance transmission is desired, the data is controlled on the trunk line by controlling the modem. Put it on.

On the other hand, when the transmission is to be transmitted through the communication network 700 for relatively short distance, the SCM 600 is also transmitted by the WAN controller, LAN controller, terminal controller, etc. by putting the data on the VME64 bus.

In order to record the data loaded on the system bus 300 on various recording media, the data is converted into a unit of an appropriate form, and the conversion thereof is performed by the direct memory access (DMA) in the input / output processor 400. Is made by.

2 shows a peripheral block diagram of the DM controller. The DM controller 410 receives a system bus address loaded on the system bus by a control signal output from the system bus controller 420, and then a memory controller ( The control signal output from 430 determines whether to perform a 64-byte block transfer or a 16-byte single transfer, and aligns the data size accordingly to temporarily store the data in the data buffer memory 440.

When the data size is arranged and temporarily stored in the memory 440, the data is transferred to the local bus through the buffer 45 and recorded on each recording medium connected thereto.

The data sorting process of the DM controller 410 will be described in more detail as follows.

The DM controller 410 supports 64 bytes of block transmission and 16 bytes of single transmission. The criterion for distinguishing the block transmission from the single transmission is determined by the size of the system bus address data to be transmitted.

In other words, if the size of the system bus address data exceeds 64 bytes, the block transfer is performed, whereas a single transfer is performed for data not exceeding 64 bytes.

FIG. 3 is a diagram illustrating a state flow of the DM controller 410. It is determined whether to perform block transmission or single transmission in the state of ARB2. A signal for distinguishing the signal is Transfer_mode.

If this Transfer_mode signal is 0, single transmission is performed, and if 1, block transmission is performed, and this is expressed as a hardware description language (HDL) as follows.

IF wcount 64 bytes THEN

Transfer_mode = 0;

ELSE

Transfer_mode = 1;

END IF

Where wcount is the size of data to be transmitted.

That is, if wcount, the size of data to be transmitted, is greater than or equal to 64 bytes, Transfer_mode is assigned to 1 to perform block transfer, whereas if less than 64 bytes, Transfer_mode is assigned to 0 to perform single transfer.

At this time, whether to perform block transmission or single transmission, after one transmission (64 bytes for block transmission and 16 bytes for single transmission) is finished, wcount is decreased by the number of bytes transferred and the number of bytes remaining The transmission operation is repeated until 0.

Therefore, wcount, that is, the size of data must always be a multiple of 16 bytes.

For example, if the total size of system address data to be transmitted is 175 bytes, that is, two 64-byte data for block transmission, and three 16-byte data for single transmission, two (64 bytes * 2) The data transfer is completed by block transmission and 3 single transmissions (16 bytes * 3).

By the way, in the case of performing block transmission instead of single transmission, the size of system address data to be transmitted must always be a multiple of 64 bytes, that is, 0, 64, 128, 192,...

If the system address data is not a multiple of 64 bytes, block transmission cannot be performed and only single transmission can be performed.

4A shows a 64 byte alignment of the system address. As shown in FIG. 4A, when the system addresses SA [5] and SA [4] are all zeros, that is, multiples of 64 bytes, block transmission is performed. Where multiples of 64 remain, a single transfer is performed, aligned in 64 byte increments.

That is, for example, in the case of transmitting the system address data of 176 bytes, if the address is a multiple of 64 bytes, it is performed by two 64 byte blocks and three 16 byte blocks, but the address is not a multiple of 64 bytes. In the case of address transfer to, 32, ..., etc., first transfer the data directly, not the multiple of 64 bytes, so that the CPU of the microprocessor unit is a multiple of 64 bytes so that the address to be transferred is a multiple of 64 bytes. Block DM transmission is then performed for the subsequent data.

4B shows an incorrect alignment of an address in 64-byte units for its block transfer. In the processor, the DRAM processor checks whether the address data to be transmitted is aligned with 64 bytes, and if it is not aligned, it is not aligned with 64 bytes. CPI directly transmits the address data portion, and then the DM performs block transmission and single transmission for the 64 byte broken portion.

In the general DM transmission method described above, if the system address data to be transmitted is not aligned in units of 64 bytes, it is necessary to check this and that the burden of the CPI increases accordingly. have.

Accordingly, in the present invention, in order to improve the conventional problem, the DM performs a single transmission until the system address is aligned to 64 bytes, and then performs a block transmission, and then, even for a system address not aligned by 64 bytes, It is an object of the present invention to provide a transmission method of the DM controller to reduce the burden of CPI by the transmission is made by the DM controller itself.

1 is an internal block diagram showing a general main computer.

FIG. 2 is a peripheral block diagram of a DM controller inside the input / output processor of FIG. 1; FIG.

3 is a diagram illustrating a state flow of the DM controller of FIG. 2.

4 is a diagram illustrating a transmission method of a general DM controller.

A is a diagram showing correct alignment of system addresses to be transmitted.

B is a diagram showing incorrect alignment of system addresses to be transmitted.

5 is a diagram illustrating a transmission method of a DM controller according to a transmission method of a DM controller of the present invention.

6 is a flowchart illustrating a transmission method of a DM controller of the present invention.

* Description of the symbols for the main parts of the drawings *

410: DM controller 420: system bus controller

430: memory controller 440: memory

450, 460: Buffer

In accordance with another aspect of the present invention, there is provided a transmission method of a DM controller, comprising: a first step of determining whether data is sorted by a predetermined byte unit when a system address is input; A second step of performing block transmission and single transmission if it is determined by the first process to be arranged in a predetermined byte unit, and performing a single transmission until sorting in a predetermined byte unit if not aligned in a predetermined byte unit; If the system address is arranged in a predetermined byte unit during the second process, the method includes a third process of performing block transmission and single transmission according to the system address.

This invention made in this way is demonstrated in detail with reference to FIG.

If the system address is input to the DM controller in step 100 (ST100), the DM controller checks in step 200 (ST200) whether the data is sorted by a predetermined byte unit, that is, in 64 byte units. ST500) performs a block transfer of 64 bytes and a single transfer of 16 bytes as in the general DM transmission method. However, if the data is not arranged in units of 64 bytes, the data is arranged in predetermined bytes by step 300 (ST300). Until a single transmission is performed.

In step 400 (ST400), the system address is continuously determined to be aligned by a predetermined byte during the single transmission, and when it is aligned by 64 bytes, block transmission and single transmission are finally performed (ST500).

In order to perform such a process, the present invention should modify a signal called Transfer_mode in the state flow diagram of the DM controller of FIG. 3 to distinguish block transmission from single transmission.

IF wcount 64 bytes or (SA [5] == 1 or SA [4] == 1) THEN

Transfer_mode = 0;

ELSE

Transfer_mode = 1;

END IF

Here, SA [5] and SA [4] are addresses provided by the DM controller to the system memory.

When these two system addresses, that is, SA [5] and SA [4] are both aligned in 64 byte units only, it is determined in step 200 (ST200) that block transmission and single transmission are performed in a general manner. If any one is 1, it is determined that the data is not aligned, and as shown in Fig. 5, a single transfer is performed before the block transfer is performed.

At this time, the SA [5] and SA [4] are incremented by 1 each time one single transmission is performed.

In other words, CPI does not transmit data directly to the data unaligned part as in the prior art, but once the DM controller performs a single transmission in units of 1 byte, the block is then transmitted to the portion arranged in units of 64 bytes. And to perform a single transmission.

This will be described as an example.

If it is assumed that 180 bytes of data are transmitted, conventionally, 4 bytes of data other than two block transmissions of 64 bytes and three single transmissions of 16 bytes are directly processed and transmitted, but in the present invention, DM The controller checks the total number of bytes of data of 180 bytes to determine the alignment of the data. Since the data is 180 bytes, it is determined that the data is not aligned in units of 64 bytes.

At this time, the system addresses SA [5] and SA [4] are increased by 1 each time a single transmission is performed.

When the value of the increased system address reaches 4, the data is sorted in 64 byte units. Therefore, the data transfer is terminated by performing two block transfers and three single transfers (in this case, 16 single byte transfers). .

As described in detail above, in the transmission method of the DM controller of the present invention, when the system address is misaligned, the burden of the CPI can be reduced by directly performing the transmission by the DM controller in charge of a single transmission part that was previously in charge of the CPI. It is possible to perform a more efficient transmission of the DM, thereby improving the performance of the overall host computer.

Claims (2)

A first step of determining whether the data is sorted by a predetermined byte unit when a system address is input; A second step of performing block transmission and single transmission if it is determined by the first process that the data is arranged in a predetermined byte unit, and performing a single transmission until the data is arranged in a predetermined byte unit if not aligned in the predetermined byte unit; If the system address is arranged in a predetermined byte unit during the second process, the third process includes performing a block transmission and a single transmission according to the method. The method of claim 1, Determination of the alignment state of the data transmission method of the DM controller, characterized in that it is determined only when the system address is all zero.