KR19980032692A - Floating gate memory device and its memory device manufacturing process - Google Patents

Abstract

The present invention relates to a floating gate memory device and a process for fabricating the device. The device has an erasable structure at a low voltage (5 volts or less) for a short time (about 1 ms or less). The device of the present invention has a structure of either a stacked structure or a split gate structure. A dielectric material layer (referred to as IPD) is inserted in the floating gate and the control gate. The dielectric constant of the dielectric material is twice the dielectric constant of the gate dielectric material. For devices in which the gate dielectric material is SiO ₂ , the dielectric constant of the IPD is greater than about 5, with dielectric constants greater than about 10 being preferred. The dielectric layer interposed between the floating gate electrode and the control gate electrode has at least as much thickness as a layer of gate oxide interposed between the floating gate and the substrate. The dielectric materials that meet these requirements include Al ₂ O ₃ , Zr-doped Al ₂ O ₃ , Y ₂ O ₃ , Zr-doped Y ₂ O ₃ , Zr-doped Ta ₂ O ₅ , Si-doped Al ₂ O ₃ , Si-doped Y ₂ O ₃ , and Si-doped Ta ₂ O ₅ .

Description

Floating gate memory device and its memory device manufacturing process

This application claims priority to provisional application Serial No. 60 / 027,612 filed October 10, 1996.

The present invention relates to a floating gate memory cell and a process for fabricating the floating gate memory cell.

Nonvolatile memory is a type of memory that keeps stored data when power is removed. Such non-volatile memory may be implemented in a variety of ways including read only memories (ROMs), programmable read only memories (PROMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs) There is a form. The EPROM is erased during ultraviolet radiation, and the EEPROM is erased using an electrical signal. Electrical signals are used to record EPROMs and EEPROMs. In conventional flash EEPROMs (flashes representing all memory cells or sectors of a cell can be erased simultaneously), the memory cells can be erased simultaneously with a low threshold voltage, and then individually or in small groups, with a high threshold voltage .

EPROMs and EEPROMs are commonly used in data processing systems that require non-volatile memory that is programmable. For convenience, EEPROMs and EPROMs are all referred to herein as EPROMs.

A typical device structure for EPROMs consists of a floating-gate polysilicon transistor. A typical floating gate structure has a floating gate interposed between two insulating layers. The insulating-floating gate-insulator structure is between the device substrate and the normal select gate electrode.

There are n-channel and p-channel devices having such a structure. In an n-channel device, the source and drain are doped with an n-type dopant and the substrate is doped with a p-type dopant. In a p-channel device, the source and drain comprise a p-type dopant and the substrate comprises a p-type dopant. Suitable substrates for such devices include silicon-based substrates and III-V semiconductor substrates such as indium-phosphorous (InP) and gallium-arsenic (GaAs). For silicon-based substrates such as silicon or silicon-germanium (SiGe), an example of a p-type dopant is boron and suitable n-type examples are arsenic (As) and phosphorus (P).

The EPROMs are programmed by applying a series of bias voltages to the device shown in FIG. The voltage applied to the select-gate (hereinafter, the control gate) is V _C , the voltage applied to the drain is V _D , and the voltage applied to the source is V _S. The voltage difference referred to as the normal bias between the various terminals is, for example, V _CS = V _C -V _S ; V _DS = V _D -V _S or the like.

Whether their bias is positive or negative, the device is dependent on one of the n-channel or p-channel when programming the floating gate. When the n-channel is programmed, V _CS and V _DS are positive values. When the p-channel is programmed, V _CS and V _DS are negative values.

For convenience, their bias polarity will be described below with respect to the n-channel device.

These write biases typically result in a high control gate-source voltage (V _CS ) and / or a high drain-source voltage (V DS). These programming voltages must move electrons to the floating gate where they are trapped in most device (channel and / or source and / or drain) regions, thereby charging the floating gate to a larger value. Since the floating gate is electrically insulated from the select gate by the insulating oxide layer and is electrically insulated from the drain-source-substrate region by another thin-film oxide insulating layer, the charge is trapped in the floating gate. The effect of trapping electrons on the floating gate is to raise the threshold voltage VT to a slightly predetermined level. Also, since their programmable voltage is outside the range of normal read bias conditions, careless write does not occur during read.

EPROMs typically include an array of floating-gate transistors. The V _T of a given cell may be determined by the sense amplifier when read and decoded to a logic value. For example, in a conventional two-state memory, a high V _T achieved by writing as described above is decoded as a logic one, and a unique V _T [negative charge is added to the floating gate 22 V _T ] of the non-device is decoded to a logic zero. Because the floating gate is isolated, the cell can remain programmed or erased for periods of up to 10 years or more. This is referred to as charge retention.

In current devices, a control gate bias of about (-) 12 volts to about (-) 15 volts (e.g., a bias between one of the source or drain of the device and the control gate) (Also, the specified polarity is for an n-channel device). If these high voltage memory devices are used in low voltage applications, for example, in systems where the operating voltage is 5 volts or less, a charge pump is needed to raise the voltage from a lower voltage to a higher voltage. The need for such a charge pump increases the cost of the system and reduces the reliability of the system due to the need to insert high voltage transistors in low voltage technology. Thus, memory devices such as flash and EPROM devices that can be erased by the application of a 5 volt or smaller operating voltage are desirable.

The present invention relates to a memory device such as a flash memory device or an EPROM device that can be erased by application of an operating voltage of 5 volts or less. It is advantageous if the device is erased in about 1 millisecond (m seconds) or less. The device of the present invention has a stacked structure with a floating gate below the control electrode in which a layer of dielectric material is inserted between the control gate and the floating gate. Because both the control gate and the floating gate are typically made of polysilicon, the dielectric material layer is commonly referred to as an inter-poly dielectric (IPD).

The floating gate overlies the channel of the device and at least a portion of the source and drain regions. A dielectric material layer is interposed between the channel, source and drain regions of the device and the floating gate. The dielectric serves both as a tunneling layer and as a gate layer of the device. In the current device, the gate dielectric material is silicon dioxide (SiO _2). Hereinafter, the gate dielectric is referred to as a gate oxide.

In the present invention, the IPD material and the IPD layer thickness are selected such that the device can be erased or written at a low voltage (5 volts or less) and at high speed (1 msec or less). In the context of the inventive device, the opposite bias is used to read and write the device. As a result, a smaller voltage is used as an absolute value, for example a voltage less than (-) 5 volts becomes negative (-) 5 volts or less.

The dielectric constant of the IPD material and the IPD layer thickness provide an electric field across the tunnel / gate oxide where the device can be erased under certain conditions. The required electric field is provided by the fact that the IPD is a material having a high dielectric constant, e.g., a dielectric constant of at least two of the dielectric constant of the gate dielectric material. Since the dielectric constant of SiO ₂ is about 3.8, the value of the gate dielectric is about 8 or greater in a device with SiO ₂ . It is advantageous if the dielectric constant of the IPD material is at least about 10. The IPD material must be a low leakage material in order for the device to retain charge on the floating gate for an acceptable period of time. Currently, a device that holds charge on the floating gate for at least about 10 years is desirable.

The device of the present invention is formed using conventional processing techniques to form flash EPROM devices. First, a gate oxide layer is formed on a silicon substrate. Typically, the substrate is shallowly doped with a p-type dopant such as boron. The gate oxide layer is formed on the substrate using conventional techniques well known to those skilled in the art. It is advantageous if the gate oxide layer thus formed has a thickness of at least about 3 nm. However, since leakage must be considered, a thickness of at least about 5 nm is considered. Further, the gate oxide functions as a tunnel region. Thus, the oxide layer must be thick enough to perform the function of the gate oxide, but must be thin enough to allow the electron's Fowler-Nordheim tunneling through its thickness.

A polysilicon layer is formed on the tunneling region to form the floating gate. The polysilicon is doped with an n-type dopant such as arsenic and has a thickness of about 50 nm to about 100 nm. Thereafter, an IPD layer is formed on the floating gate. The IPD layer is formed of one or more layers. If the IPD layer is composed of multiple layers, the layers are composed of a material having a sufficiently high dielectric constant that is at least about 8 for the effective dielectric constant of the IPD layer. In the context of the present invention, the effective dielectric constant of the IPD layer is such that, regardless of whether the IPD layer is of a single layer or a multi-layer structure, the effective dielectric constant of the IPD layer is the dielectric constant of the whole layer. Examples of suitable high dielectric constant material is aluminum oxide (Al ₂ O _3), yttrium oxide (Y ₂ O _3), zirconium (Zr) - doped with aluminum oxide (Al ₂ O _3), zirconium (Zr) - doped tantalum (Ta ₂ O ₅ ), Zr-doped Y ₂ O ₃ , silicon (Si) -doped aluminum oxide (Al ₂ O ₃ ), Si-doped Ta ₂ O ₅ and Si-doped Y ₂ O ₃ . In the non-volatile memory devices (EPROMs) of the present invention that retain charge on the floating gate for a previously specified time, the thickness of the IPD layer is required to be at least as thick as, or thicker than, the gate oxide layer.

Thereafter, a control gate is formed on the IPD layer. The control gate layer is typically polysilicon, an n-type dopant such as arsenic is doped for the n-channel device, and a p-type dopant is doped for the p-channel device. The thickness of the control gate layer is about 100 nm to about 300 nm. After their layers are formed, the gate stack of the device is formed using conventional lithographic or etching techniques well known to those skilled in the art, and then a MOS (metal-oxide-semiconductor) Followed by other processing steps commonly used for manufacturing. Although the device of the present invention has been described through a stacked gate structure, devices with a split gate structure are also contemplated.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view schematically illustrating the apparatus of the present invention.

2 is a graph illustrating the effect of the dielectric constant of the IPD material on the electric field of the gate oxide at different control gate voltages.

3 is a graph illustrating the effect of dielectric constant on the control gate bias (V _CS ) for devices having different IPD thicknesses.

4 is a graph to illustrate the effect of the dielectric constant of the IPD material with the erase time of the floating gate at three different source-drain voltages (V _DS ).

Description of the Related Art [0002]

12: source 14: drain

16: channel region 10: substrate

20: gate oxide layer 22: polysilicon floating gate

24: IPD26: control gate

The present invention relates to a flash EPROM device in which the characteristics of the IPD are controlled in such a way as to provide a device for erasing for less than 1m second when an operating voltage of less than 5 volts is applied to the control gate of the device. As previously described, the apparatus of the present invention is a flash memory or EPROM having a stacked structure. The device of the present invention has an IPD layer with a dielectric constant of at least 8, preferably at least 10. In addition, the device of the present invention has a gate oxide thickness as previously described. This is advantageous when the gate oxide thickness is from about 5 nm to about 8 nm. In the device of the present invention, the thickness of the IPD layer is at least increased or becomes greater than the thickness of the gate oxide layer.

One embodiment of the apparatus of the present invention is described with reference to Fig. The device has a layer of silicon dioxide (SiO ₂₎ formed on a substrate 10 having a source 12, drain 14 and channel region 16 therein. The oxides are formed by conventional techniques such as furnace oxidation and rapid thermal oxidation in environments such as O ₂ and N ₂ O that are well known to those skilled in the art.

A polysilicon floating gate 22 is formed on the gate oxide layer 20. The polysilicon layer 22 is formed using conventional techniques such as chemical vapor deposition (CVD). The thickness of the polysilicon layer 22 becomes a big problem in the design design. The typical thickness of the floating gate is from about 50 nm to about 100 nm.

The IPD 24 is formed on the floating gate using conventional techniques. Typically, techniques such as sputtering, chemical vapor deposition, or oxidation are used to form the IPD 24. As previously described, it is desirable if the IPD layer has a dielectric constant of at least about 8, but does not allow a large leakage of current from the floating gate. Examples of suitable materials include Al ₂ O ₃ ; Zr-doped Al ₂ O ₃ ; Y ₂ O ₃ ; Zr-doped Y ₂ O ₃ ; Zr-doped Ta ₂ O ₅ ; Si-doped Al ₂ O ₃ ; Si-doped Y ₂ O ₃ , and Si-doped Ta ₂ O ₅ . The proposed zirconium (Zr) or silicon (Si) component of the doped aluminum oxide is from about 1 wt% to about 5 wt%. In this embodiment, the IPD is Zr-doped Al ₂ O ₃ , with zirconium dopant concentrations of up to 50 wt% being considered. However, due to its dopant concentration, the material must not cause unacceptably high leakage and should not cause unacceptably low breakdown strength.

For devices to maintain charge for at least about 10 years, the charge leakage through the IPD layer should be less than or equal to about 10 ^-14 A / cm ² . As previously described, since a low leakage material is desirable, its charge is held in the floating gate. The above-mentioned dielectric materials have examples of materials suitable for the above conditions.

The control gate 26 is a layer of conductive material formed over the IPD 24 layer. The control gate is a conventional material such as doped polysilicon, metal silicide, titanium nitride, or a bi-layer of polysilicon and metal suicide. This control gate layer is formed and patterned using conventional techniques for fabricating MOS devices.

In the device of the present invention, the material and thickness of the IPD layer are selected to provide an apparatus for operating at low voltages and still maintaining charge on the floating gate for a reasonably long period of time. In the apparatus of the present invention, the material and thickness of the tunnel oxide thickness (TO) of the IPD is selected to be K _{IPO IPO} ≒ E K E _{TO TO.} In this formula, the dielectric constant of the material is denoted by K, and the electric field of the layer is denoted by E. In the context of the present invention, it is advantageous if the E _TO is increased to provide an environment where the device is quickly erased. In this regard, the _TO E is advantageous if at least about 8MV (mega volt) / cm. Further, it is advantageous if the E _TO E is less because the _IPD obtaining a greater reliability, the smaller is smaller. In this regard, the _TO E is advantageous if less than approximately 5MV / cm. Since K _TO is fixed, an increase in K _TO results in an increase in E _TO for a given bias of the control gate and for a given thickness of tunnel oxide and IPD.

Figure 2 illustrates the effect of dielectric constant along the electric field of gate oxide at different control gate voltages. Full-lattice EPROM devices with a gate oxide thickness of 5.5 nm, a VDS of 2 V, and a floating gate area of 0.8 μm × 0.5 μm were modeled analytically. The dielectric constant of the IPD material is varied from about 3 to about 10,000. The thickness of the IPD is 15 nm. Figure 2 shows that for a very low voltage (less than 5 volts) applied to the control gate, a high electric field across the gate oxide (about 10 MV / cm) is produced by an apparatus comprising an IPD layer having an effective dielectric constant of 8 or more Can be achieved.

FIG. 3 shows the effect of the dielectric constant of the IPD material on the thickness of the IPD as the control gate voltage bias (V _CG ) required to remove charge from the floating gate decreases.

In this example, a flash EPROM device having a gate oxide thickness of 5.5 nm, a V _{DS of} 3.3 V, and a floating gate region of 0.8 [mu] m x 0.5 [mu] m was modeled as previously described. The dielectric constant of the inter-poly dielectric constant varies from about 3 to about 10,000. The thickness of the IPD is varied from one to two times to three times the thickness of the gate oxide. The modeled performance of the device with a thickness of 5.5 nm (the same thickness as the gate oxide) is indicated by a line in circle 100. The modeling performance of the device with an IPD thickness of 11 nm (twice the thickness of the gate oxide) is indicated by a line of rectangles 110.

The modeling performance of the device with an IPD thickness of 16.5 nm (three times the thickness of the gate oxide) is indicated by the line of the triangle 120.

Figure 3 shows the bias reduction rate (with respect to SiO ₂ ) as a function of the dielectric constant of the IPD layer. The bias reduction rate is obtained by modeling V _CS on a device having a value of K _IPD in the range of 3 to 10,000 standardized with a device in which IPD is SiO ₂ . By increasing the dielectric constant of the IPD layer from 3.82 to 8 or more, the applied bias is reduced by 40 to 50%. The effect of increasing the dielectric constant of the IPD layer appears more than in a thicker layer.

Figure 4 shows the effect of the IPD dielectric constant over the erase time of the floating gate at different V _DS . 5.5 nm gate oxide A flash EPROM device with an IPD thickness of 15 nm and a floating gate region with a width of 0.8 [mu] m and a length of 0.5 [mu] m was modeled using an analytical model. The dielectric constant of the IPD material is varied from about 3 to about 10,000.

The performance of the device was modeled at three different values for V _DS , 5V, 3.3V and 2V. At all three voltages, the erase time is reduced as an increased dielectric material until the dielectric constant of the IPD increases by more than 100. Thereafter, the increase in erase time due to the increasing dielectric constant is observed due to the loading effect of the capacitance.

A floating gate memory device such as a flash memory device or EPROM device is provided so that it can be erased or written at a low voltage (5 volts or less) and at high speed (1 msec or less).

Claims (11)

A stacked floating gate memory device comprising: A semiconductor substrate having a source region, a drain region, and a channel region interposed between the source region and the drain region; A gate dielectric layer formed over the source, drain, and channel regions of the substrate; A floating gate electrode formed over the channel region and at least a portion of the source and drain regions of the substrate; A dielectric material layer formed on the floating gate electrode; Wherein the dielectric layer is interposed between the floating gate and the substrate and wherein the effective dielectric constant of the dielectric layer is at least about two times greater than the dielectric constant of the gate dielectric material and the dielectric material layer is at least as large as the thickness of the gate dielectric layer, Wherein the thickness of the dielectric material layer is selected to provide a device that will erase the floating gate upon application of an operating voltage (V _DS ) of less than about 5 volts for a time less than 1 millisecond. 2. The floating gate memory device of claim 1 wherein the gate dielectric is a gate oxide and the effective dielectric constant of the dielectric layer is at least about 8. 3. The floating gate memory device of claim 2, wherein the thickness of the gate oxide is at least about 3 nm and the thickness of the dielectric material layer is equal to or greater than the gate oxide. 4. The floating gate memory device of claim 3, wherein the thickness of the gate oxide is from about 3 nm to about 8 nm. The dielectric material is Al ₂ O _3, Zr- doped Al ₂ O _3, Y ₂ O _3, Zr- doped Y ₂ O _3, Zr- doped Ta ₂ O _5, Si- doped Al ₂ O _3, Si-doped Y ₂ O ₃ , and Si-doped Ta ₂ O ₅ . 6. The floating gate memory device of claim 5, wherein the dielectric material has a sufficiently low leakage to the floating gate to retain charge for at least about 10 years. 5. The floating gate memory device of claim 4, wherein the substrate material is selected from the group consisting of silicon, silicon germanium alloy, indium, and gallium arsenide. 3. The floating gate memory device of claim 2, wherein the layer of dielectric material comprises more than one layer of dielectric material. 3. The floating gate memory device of claim 2, wherein the effective dielectric constant of the layer of dielectric material is at least about 10. 3. The method of claim 2, wherein the device is one of an n-channel or p-channel and the operating voltage is negative (-) 5 volts or less when applied to the control gate of the n- (+) 5 volts or less when applied to the control gate of the p-channel device. 3. The method of claim 2, wherein the device is one of an n-channel or a p-channel and the operating voltage is (+) 5 volts or less when applied to the control gate of the n- (-) 5 volts or less when applied to the control gate of the channel device.