KR19980028592A - Synchronous signal detection device for multi-bit N-jet interface - Google Patents

Abstract

The present invention relates to a synchronization signal detecting apparatus for efficiently detecting a synchronization signal in a multi-bit input NRL (hereinafter referred to as NRZ) interface in a hard disk drive. The synchronization signal detecting circuit of the present invention converts NRZ input data into parallel data of a predetermined bit, compares the converted data with a predetermined reference address mark, determines whether the synchronization signal is detected as the compared signals, and determines the address mark detection signal ( AMFOUND). After the address mark signal is detected, the synchronized 8-bit data is finally output as byte data. If pre-synchronized NRZ data is input, a separate comparison means is used.

The synchronization signal detection device of the multi-bit input NRZ interface of the present invention can detect the synchronization signal quickly enough in response to a high speed data transfer in the hard disk drive. In addition, by using an error-tolerant comparator as a comparison means, the function of the synchronization signal detection apparatus is improved so that the synchronization signal can be detected even if an error of 3 bits or less occurs.

Description

Synchronous Signal Detection Device for Multi-Bit NRZ Interface

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a SYNC signal detection apparatus used for a hard disk drive, and more particularly, to a multi-bit input NZ (None Return to Zero) required as the transmission speed in the hard disk drive increases. The present invention relates to a synchronization signal detection device for efficiently detecting an address mark, that is, a synchronization signal, at an interface.

1 shows a schematic configuration diagram of a synchronization signal detection circuit for NRZ1 data and NRZ0 data in a conventional 2-bit input line NRZ interface. Here, the 2-bit input line means that NRZ data is input in parallel through two input lines. The conventional synchronization signal detecting circuit includes data converting means (100) for outputting NRZ data input to a 2-bit input line as 12-bit parallel data in synchronization with a predetermined clock signal, and the tenth to third consecutive bits of the parallel data. First comparison means 111 which receives the data of the first data and compares it with predetermined reference address data to determine whether or not it is the same, and outputs the first comparison signal EQ1; Second comparison means 112 for outputting a second comparison signal EQ2 by comparing the predetermined reference address data with the predetermined reference address data and outputting the second comparison signal; A logic latch operation means 170, a first latch means 120 for latching and outputting an output signal of the logic calculation means 170 as a predetermined reference address detection signal in synchronization with a clock signal; Second latch means 130 for latching and outputting a second comparison signal, a divider means 160 for dividing and outputting a clock signal at a predetermined division ratio corresponding to a predetermined reference address mark, and continuous 12 to 5 in parallel data. A selection means 140 for receiving data of the first bit and data of the 11th to 4th bits to selectively output one of the two input data according to the latch output signal of the second latching means 130, and the selection means ( The third latch means 150 receives the output of the output 140 and latches the output signal in synchronization with the output signal of the dispensing means 160.

The first latch means 120 includes first flip-flop means 121 for latching and outputting an output signal of the logic operation means 170 in response to a clock signal, and a latch output signal of the first flip-flop means 121. First flip-flop means 121 for outputting a logic high signal in synchronization with the control unit. The second latch means 130 is logic high in synchronization with the latch output signal of the third flip-flop means 131 and the third flip-flop means 131 for latching the second comparison signal in response to a clock signal. The fourth flip-flop means 132 outputs a signal.

The detailed operation of the conventional synchronization signal detection apparatus for 2-bit input line NRZ data is disclosed in Korean Patent Application No. 95-2835, filed on February 15, 1995 by the present applicant, Described in the address mark detection apparatus.

2 shows an embodiment of an error-tolerant comparator in a conventional synchronization signal detection apparatus. The detection apparatus adopting the error tolerance comparator shown in FIG. 2 is for detecting an address mark pattern regardless of occurrence of data errors of two consecutive bits or less when reading data of a section in which a reference address mark is recorded. Details of the error-tolerant synchronization signal detection circuit are described in Korean Patent Application No. 94-29360, filed on November 9, 1994, by the present applicant, in the address mark pattern detector of a disc drive device.

The synchronization signal detection circuit described above was able to detect the synchronization signal when the NRZ input was a single bit input or a two bit input. However, in response to the trend of increasing the transmission speed of the hard disk drive, there was a problem in that the transfer capacity of the 2-bit input line NRZ data was not used up to the limit. In addition, as the transmission method of the hard disk is changed to an 8-bit NRZ interface, an appropriate synchronization signal detection device is required.

Accordingly, an object of the present invention is to provide an apparatus capable of detecting a synchronization signal for a multi-bit input NRZ interface in consideration of such a conventional problem.

It is still another object of the present invention to provide an 8-bit NRZ direct detection circuit which speeds up the detection of a synchronization signal when using an 8-bit NRZ interface inputted with synchronization.

1 is a synchronization signal detection circuit of a conventional 2-bit input line NRZ interface,

2 is a conventional error tolerance comparator in a detection circuit of a synchronization signal;

3 is a synchronization signal detection circuit for NRZ data used in the present invention;

4 is a circuit diagram of eight comparators in the first comparing means in the synchronization signal detecting circuit of the present invention;

5 is a detailed circuit diagram of a fault tolerant comparator used for the first comparing means and the second comparing means in the synchronization signal detecting apparatus of the present invention;

6 is a detailed circuit diagram of priority determination means in the synchronization signal detecting apparatus of the present invention;

7 is an input signal timing diagram of a synchronization signal detecting apparatus in the preferred embodiment of the present invention.

8 is an output signal timing diagram of the synchronization signal detection apparatus in the preferred embodiment of the present invention.

Explanation of symbols on the main parts of the drawing>

200: data conversion means 210, 220: comparison means

230: priority determination means 231: third register

240, 250: multiplexer means 260: fourth register

270: latch means 280: logical operation means

The multi-bit input NRZ interface synchronization signal detection circuit for achieving the object of the present invention comprises a data conversion means 200 for converting the predetermined bit input line NRZ data into 16-bit parallel data in synchronization with a predetermined clock signal, and First comparing means 210 for comparing the predetermined address mark in order of 8 bits from the most significant bit among the 16 bit data output from the data converting means 200 and the first outputted from the first comparing means 210. A logic summation operation for receiving the ˜8 comparison signal and performing logical sum operation upon receiving the priority determination means 230 for checking the priority and the first to eighth comparison signals DT1 to DT8 output from the first comparison means 210. Means 280, latch means 270 for outputting the output signal of the logical operation means 280 as an address mark detection signal AMFOUND in synchronization with the predetermined clock signal, and the priority judging means 230. Synchronized 8-bit data Select and output one of the first multiplexer means 240 for selecting and outputting the 8-bit data BYTE2 (7: 0) which is input in synchronization with the 8-bit data output from the first multiplexer means 240 from the beginning; And a fourth register 260 for outputting the synchronized NRZ byte data output from the second multiplexer means 250 as byte data.

In addition, the multi-bit input NRZ interface synchronous signal detection circuit for achieving the object of the present invention, in particular in the 8-bit input line NRZ interface, in order to improve the detection speed of the synchronization signal when the pre-synchronized NRZ data is input. Characterized in that it comprises two comparison means (220).

3 shows a synchronization signal detection apparatus for NRZ data used in the present invention.

The synchronization signal detecting apparatus of the present invention includes data conversion means 200 for outputting 8-bit input line NRZ data input in synchronization with a predetermined clock signal as 16-bit parallel data, and 16 output from the data conversion means 200. The first comparison means 210 which compares the corresponding 8 bits among the bit data with a predetermined address mark, and the first to eighth comparison signals DT1 to DT8 output from the first comparison means 210 are first received. Priority judging means 230 for checking the figure, separate second comparison means 220 for immediately detecting an address mark when the NRZ data input is 8-bit data inputted in synchronization with the first comparison means, and a first comparison A logic sum calculating means 280 for receiving the first to eighth comparison signals DT1 to DT8 output from the means 210 and the ninth comparison signal DT0 output from the second comparing means 220 and performing an OR operation; Synchronizing the predetermined clock signal with the output signal of the logic Latch means 270 for outputting the address mark detection signal AMFOUND, and first multiplexer means 240 for selecting and outputting 8-bit data that is synchronized after priority is determined by the priority judging means 230. And second multiplexer means 250 for selecting and outputting one of the 8-bit data BYTE2 (7: 0) inputted in synchronization with the 8-bit data output from the first multiplexer means 240, and It consists of a fourth register 260 which outputs the synchronized byte data output from the multiplexer means 250.

The data converting means 200 is composed of two shift registers 201 and 202 which operate with the same predetermined clock in order to extend the input predetermined data into 16 bits. The first comparator 210 compares the eight-bit data shifted by one bit of consecutive two-byte input data with an address mark and outputs eight comparators DT1 to DT8. 211 ~ 218).

FIG. 4 shows an embodiment of a circuit composed of eight comparators within the first comparing means 210 of FIG. 3. FIG. 5 is an embodiment of error-tolerant comparators 211 to 218 and 221 used in the first comparing means 210 and the second comparing means 220 of FIG. 2. 6 is an embodiment of the priority determining means 230 of FIG.

Hereinafter, the operation of the present invention will be described in detail with reference to FIGS. 3 to 8. In the preferred embodiment, the predetermined number of bits of the NRZ input data is 8 bits. First, the NRZ data NRZ8 (7: 0) of the 8-bit input line is input to the data converting means 200. The data converting means 200 increases the input 8-bit NRZ data NRZ8 (7: 0) to 16 bits to find the start position of the synchronization signal in response to the predetermined clock BYTECK. This is executed by the first and second registers in the data converting means 200, and converted into 16-bit data D0 to D15 composed of previously input 8-bit data and the currently input 8-bit data, so that one comparison means 210 ) Is entered. The first comparing means 210 includes first to eight comparators 211 to 218. The first comparator 211 is for checking a synchronization signal, and the most significant bit of the 16-bit data rearranged in the input order by the data converting means 200 in the descending order, that is, the first to the ninth to nineteenth bits first input. Compares the first byte data BD1 (7: 0) with an address mark with one byte, and outputs the first comparison signal DT1 if it is equal. In general, the address mark uses A5H (10100101B for binary data), which is a hexadecimal value, for NRZ data of 8 input bits. The second comparator 212 outputs a second comparison signal DT2 by comparing the address mark with the second byte data BD2 (7: 0) having one to fifteenth to eighth bits among the aligned 16-bit data. . Similarly, the remaining third to eighth comparators 213 to 218 use the third to eighth byte data BD3 (7: 0) to BD8 (7) having eight bits shifted downward by one bit in the aligned 16-bit data. : 0 and the address mark are compared to output third to eighth comparison signals DT3 to DT8. In the first to eighth comparators 211 to 218, the error tolerance enable bit FAULTENI must match all the bits when comparing the NRZ data input to the first to eighth comparators 211 to 218 with the synchronization signal pattern that is an address mark. To determine whether to operate with an error-tolerant comparator that is considered synchronized even if an error occurs up to 3 bits or less as a result of comparing the NRZ data input to the first to eighth comparators 211 to 218 and the address mark. It is a signal. In the preferred embodiment of the present invention, the error-tolerant enable bit is set to 0 for the first to eight comparators as a normal case in which all the bits must match.

Thereafter, the priority judging means 230 receives the first through eighth comparison signals DT1 through DT8 output from the first comparing means 210 and makes the first synchronization signal valid. For example, when the first comparison signal DT1 and the second comparison signal DT2 both show the synchronization signal, the priority determining means 230 first synchronizes the first comparison signal DT1 since the first comparison signal DT1 has a high priority. Is determined to have been detected. Therefore, all synchronization signals generated after the first comparison signal DT1 are ignored. That is, in the priority determining means 230, the priority is synchronized with the first input bit in time because the first comparison signal DT1 is the highest and the second comparison signal DT8 is the lowest. In FIG. 3, the power on reset signal PORB is for initializing all related logics when power is first applied. The power on reset PORB is a signal made to be logic low at first and then to logic high after a certain time. When the power initialization signal PORB is initially applied, the DTO (7: 0), DIRSB, AMFOUND, BYTED (7: 0) signals in the circuit of FIG. 3 are cleared.

As a special embodiment, when the NRZ data input is an 8-bit length, i.e., a pre-synchronized signal in bytes, a second comparison means 220 is used to reduce the delay of the comparison operation time performed by the first comparison means. . The second comparator 220 includes a ninth comparator 221. When the ninth comparator 221 receives the synchronized NRZ data, the second comparator 221 can immediately determine whether to detect the sync signal by comparing the address mark data. The output signal DIRSB of the second comparing means 220 is used as a control signal of the second multiplexer means 250 to be described later.

In the first multiplexer means, if the synchronization signal is input from the first comparison means 210 and the second comparison means 220, the priority of the synchronization signal is determined by the priority determination means 230, and then the synchronization position is corrected. This is for outputting the rearranged data of the data. The corrected data after being synchronized among the 8-bit BD1 to BD8 outputs of the data conversion means 200 using the signal output from the priority judging means 230 as a control signal. Select to output the rearranged data to the second multiplexer means.

The second multiplexer means is for immediately outputting the NRZ input when the synchronized signal enters the NRZ input as described above, and is 8 bits of the first multiplexer means by the output signal DIRSB of the second comparing means 220. The 8-bit output BYTE2 (7: 0) of the output and the first shift register 201 is immediately sent to the synchronized 8-bit output BYTED (7: 0) through the fourth register 260.

In a preferred embodiment, it is assumed that NRZ8 (7: 0), which is NRZ data of an 8-bit input line, is input to the data converting means 200 in the order of 0AH, 50H, 10H, 20H. Then, the NRZ8 (7: 0) is first converted into 8-bit BYTE2 (7: 0) data by the first shift register 201 operating in response to a predetermined clock BYTECK. This byte data BYTE2 (7: 0) ) Is again connected to the input of the second shift register 202 in response to the same clock BYTECK to make byte data BYTE1 (7: 0) one clock later than byte data BYTE2 (7: 0). After that, two bytes of byte data BYTE2 (7: 0) and byte data BYTE1 (7: 0) are increased to 16 bits from bit 7 of BYTE 1 to bit 0 of BYTE 2 in order of inputting to find the synchronization signal. It is checked at which position among the 16-bit data input to the synchronous signal. Referring to the comparators shown in FIGS. 3 and 5, the byte data having the upper eight bits of the 16-bit data, that is, the 16th to 9th bits, as one byte in the first comparing means is compared with a predetermined reference address mark. Next, the first comparison signal DT1 is output, and then byte data having eight bits shifted by one bit in descending order, that is, the byte of the 15th to 8th bits as one byte, is compared with a predetermined reference address mark, and then the second comparison signal DT2 Outputs and continuously shifts by one bit in the same way to check where the synchronization signal is input. The result of comparing the 8-bit data inputted in this way with the address mark is the first to eighth comparison signals DT1 to DT8 which are outputs of the first comparison means 210. These comparison signals are input to the logic operation circuit 280. It is determined whether an address mark has been detected. The output signal of the logic sum circuit 280 is connected to the latch means 270, and if the address mark is detected in the comparing means, the first flip-flop 271 in the latch means 270 is synchronized with a predetermined clock BYTECK. The output signal of the logic operation circuit 280 is latched out to produce a signal AMF1. The output signal AMF1 of the first flip-flop 271 is input to the third flip-flop 222 in the second comparing means 220 as a clock signal to control the output of the DIRSB signal indicating that an address mark of 8-bit synchronous data has been detected. do. The signal AMF1, once active high, is cleared when the signal AMSEN goes low. The high signal AMF1 is input to the second flip-flop 272 to make the output signal AMFOUND high. At this time, the signal AMFOUND is cleared when the input signal RG of the AND gate 274 becomes low.

Meanwhile, another first flip-flop 272 output signal CON1 corresponding to the output signal of the logic operation circuit 280 is input to the third register 231 as a control signal and is 8 bits output from the priority judging means 230. The signal DTI (7: 0) is connected to the input of the first multiplexer means 240 as an 8-bit signal DTO (7: 0). When the CON1 signal, which is one of the output signals of the first flip-flop 272, is activated low, the byte data DTO (7: 0) having the start position information of the synchronized data output from the priority determining means 230 is stored in the third register. 231 is connected to the input terminal of the first multiplexer means, wherein one 8-bit data that is synchronized among the 8-bit data BD1 to BD8 is selected by the decoding result of the priority judging means 230, so that the first multiplexer means ( Outputted as output S01 of 240). At this time, if the output signal DIRSB of the second comparing means 220 is active, that is, if the NRZ data string of the 8-bit input line is already synchronized, the second multiplexer means 250 is BYTE2 which is the input NRZ data. Immediately output (7: 0). On the contrary, since the DIRSB signal is not active, i.e., the data is not synchronized, the second multiplexer means 250 is the first multiplexer means 240 which is the synchronized byte data determined by the priority determining means 230. Outputs S01 as the output S02 of the second multiplexer means 250. Thereafter, the fourth register 260 receives the output S02 of the second multiplexer means 250 and outputs the byte output BYTED (7: 0) synchronized with the predetermined clock signal BYTECK. In the above preferred embodiment, the NRZ data input signal NRZ8 (7: 0), the byte clock BYTECK, the output signal S01 of the first multiplexer means 240, the output signal S02 of the second multiplexer means 250, and the synchronized byte output. The timing for the data BYTED (7: 0) and the reference address mark detection signal AMFOUND is as shown in the input signal timing diagram of FIG. 7 and the output signal timing diagram of FIG. 8. In the above embodiment, since the sync signal is detected in the fifth comparator and DT5 is generated, the DTO (7: 0) maintains 08H.

As described above, in the above-described preferred embodiment, the NRZ data input is limited to 8 bits of byte data, but the Korean Patent Application No. 95-2835, which is referred to above, in the address mark detection apparatus of the dual bit N-jet data transmission type disk drive device. The synchronization signal detecting apparatus of the present invention can also be applied to a 2-bit input line or existing 1-bit and 4-bit input line data. That is, in the case described above, the synchronization signal detection of the present invention is performed by adding a known circuit for converting NRZ data of 1-bit input line or 4-bit input line into 8-bit input line in front of the data conversion means 200 of the present invention. It is possible to use the device. At this time, the predetermined clock BYTECK should be determined to suit the bit input line of the corresponding NRZ data.

In addition, it will be appreciated by those skilled in the art that the synchronous signal detection apparatus of the present invention can be further extended to apply to NRZ data inputs such as 16-bit input lines to 32-bit input lines.

As described above, the synchronous signal detection device of the multi-bit input NRZ interface enables the synchronous signal to be detected quickly enough in response to a request for high-speed data transfer in the hard disk drive. In addition, by providing a separate comparison means for the case that the 8-bit synchronized data is the input of the NRZ data, it is possible to ensure a faster transmission speed.

In addition, by using an error-tolerant comparator, even when an error of 3 bits or less occurs, the synchronization signal detection device can be improved by detecting the synchronization signal.

In addition, by adding a known additional circuit, there is an advantage that the detection apparatus of the present invention can be used as it is for the existing 1-bit input lines or 4-bit input lines.

Claims (6)

In the address mark pattern detection apparatus of a disc drive recording apparatus having predetermined reference address data of a hard disc drive, Data conversion means for outputting multi-bit input line NRZ data as 16-bit parallel data, first comparison means for comparing a predetermined 8-bit of the parallel data with a predetermined reference address mark, and outputted from the first comparison means. Priority judging means for receiving the first to eighth comparison signals and checking the priority, Logical summation means for receiving the first to eighth comparison signals output from the first comparison means and performing logical sum operation, and Output of the logical summation means Latch means for outputting a signal as an address mark detection signal AMFOUND, multiplexer means for selecting and outputting 8-bit data synchronized by the priority determining means, and synchronous NRZ output from the second multiplexer means. An address mark detection device for a multi-bit NRZ interface, comprising: a fourth register for outputting byte data as byte data . The method of claim 1, And the multi-bit input line NRZ data is 8-bit input line NRZ data. The method of claim 2, The first comparator includes eight comparators, that is, first to eight comparators, and outputs first to eighth comparison signals after comparing with a predetermined reference address mark, respectively. Mark detection device. The method of claim 3, wherein And said comparators are fault tolerant comparators. The method of claim 2, When the 8-bit input line NRZ data is synchronized 8-bit NRZ data, the address mark for the multi-bit NRZ interface further comprises a second comparing means for detecting the synchronization signal immediately without time delay. Detection device. The method of claim 5, When the 8-bit input line NRZ data is synchronized 8-bit NRZ data, the 8-bit data BYTE2 (7: 0) inputted in synchronization with the 8-bit data output from the multiplexer means is selected for output. And a second multiplexer means further comprising: an address mark detection apparatus for a multi-bit NRZ interface.