KR100242004B1 - Apparatus for detecting syncsignal about multi nrz interface - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous signal detecting apparatus for efficiently detecting a synchronous signal in a multi-bit input non-jet (NRZ) interface in a hard disk drive.

The synchronous signal detecting circuit of the present invention converts NRZ input data into parallel data of a predetermined bit, compares the converted data with a predetermined reference address mark, determines whether or not a synchronous signal is detected as the compared signals, AMFOUND).

In addition, after the address mark signal is detected, the 8-bit data having the same synchronization is finally output as the byte data. If previously synchronized NRZ data is input, a separate comparison means is used.

The apparatus for detecting a synchronous signal of a multi-bit input NRZ interface of the present invention can detect a synchronous signal sufficiently fast in response to high-speed data transmission in a hard disk drive.

Further, by using the error tolerant comparator as the comparison means, the function of the synchronous signal detecting apparatus is improved so that the synchronous signal can be detected even if an error of 3 bits or less occurs.

Description

[0001] APPARATUS FOR DETECTING SYNCSIGNAL ABOUT MULTI NRZ INTERFACE FOR MULTI-BIT ENGINE (NRZ)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous signal detecting apparatus for use in a hard disk drive, and more particularly, to a synchronous (SYNC) signal detecting apparatus for use in a hard disk drive, And more particularly to a synchronizing signal detecting apparatus for efficiently detecting an address mark, that is, a synchronizing signal.

FIG. 1 shows a schematic configuration diagram of a sync signal detecting circuit for NRZ1 data and NRZ0 data in a conventional 2-bit input line NRZ interface. Here, the 2-bit input line means that the NRZ data is inputted in parallel via two input lines.

The conventional synchronous signal detecting circuit comprises data converting means (100) for outputting NRZ data inputted as a 2-bit input line in synchronism with a predetermined clock signal as 12-bit parallel data, (111) for receiving the data of the first and second parallel data and comparing the data with predetermined reference address mark data to determine whether they are the same or not and outputting a first comparison signal (EQ1) A second comparator 112 for receiving the first comparison signal and the second comparison signal EQ2 by comparing the predetermined reference address mark data with the predetermined reference address mark data to determine whether they are the same or not and outputting a second comparison signal EQ2; First latch means (120) latching the output signal of the OR circuit (170) in synchronization with the clock signal by a predetermined reference address mark detection signal, and a second latch means A second latch means (130) for latching a second comparison signal to output a second comparison signal; a frequency division means (160) for dividing a clock signal by a predetermined frequency division ratio in accordance with a predetermined reference address mark and outputting it; Th bit data and the 11th to 4th bit data and selectively outputting one of the two input data by a latch output signal of the second latch means 130; And a third latching means 150 for receiving the output of the latching means 140 and latching the output of the latching means 160 in synchronization with the output signal of the dividing means 160.

The first latch means 120 includes a first flip-flop means 121 latching the output signal of the logical sum operation means 170 in response to a clock signal, and a second flip- And a first flip-flop means 121 for outputting a logic " high " The second latch means 130 includes a third flip-flop means 131 for latching and outputting the second comparison signal in response to the clock signal, a logic " And a fourth flip-flop means 132 for outputting a " high " signal.

The detailed operation of the synchronous signal detecting apparatus for the conventional 2-bit input line NRZ data is disclosed in Korean Patent Application No. 95-2835 filed on Feb. 15, 1995 by the present applicant, " Dual Bit- Quot; address mark detection apparatus "

2 shows an embodiment of a fault tolerant comparator in a conventional synchronous signal detecting apparatus.

The detection device adopting the error-tolerant comparator of Fig. 2 is for detecting an address mark pattern irrespective of occurrence of data error of two or less consecutive bits when reading data of a section in which a reference address mark is recorded.

The details of the detection circuit of the error-permitting synchronizing signal are described in Korean Patent Application No. 94-29360, " Address Mark Pattern Detector of Disk Drive Apparatus " filed on November 9, 1994 by the present applicant.

The synchronous signal detection circuit described above can detect the synchronous signal when the NRZ input is a single bit input or a 2 bit input. However, there is a problem in that the transmission capacity of the 2-bit input line NRZ data reaches the limit in response to the tendency of the transfer rate of the hard disk drive to increase. Also, as the transmission method of the hard disk is changed to the 8 bit NRZ interface, a synchronous signal detecting device suitable for that is required.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an apparatus capable of detecting a synchronization signal for a multi-bit input NRZ interface.

It is still another object of the present invention to provide an 8-bit NRZ direct detection circuit which speeds up the detection of a synchronous signal when using an 8-bit NRZ interface which is input synchronously.

1 is a conventional synchronous signal detecting circuit of a 2-bit input line NRZ interface,

2 is a fault tolerant comparator in a conventional synchronous signal detecting circuit,

3 is a synchronization signal detection circuit for NRZ data used in the present invention,

4 is a circuit diagram of eight comparators in the first comparison means in the sync signal detection circuit of the present invention,

5 is a detailed circuit diagram of a fault tolerant comparator used in the first comparing means and the second comparing means in the synchronous signal detecting apparatus of the present invention,

6 is a detailed circuit diagram of the priority determination means in the synchronization signal detection apparatus of the present invention,

7 is a timing chart of the input signal of the synchronous signal detecting device in the preferred embodiment of the present invention,

8 is a timing chart of the output signal of the synchronous signal detecting device in the preferred embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

200: data conversion means 210, 220: comparison means

230: priority determination means 231: third register

240, 250: multiplexer means 260: fourth register

270: latch means 280:

In order to achieve the above object, the present invention provides an address mark pattern detecting apparatus for a disk drive recording apparatus having predetermined reference address mark data of a hard disk drive, the apparatus comprising: a multi-bit input NRZ interface synchronizing signal detecting circuit, Data converting means for outputting data as 16-bit parallel data; The comparator includes eight fault tolerant comparators, that is, first to eighth comparators, and compares predetermined eight bits of the parallel data with the predetermined reference address mark, First comparison means for comparing the eighth comparison signal; Priority determining means for receiving the first to eighth comparison signals output from the first comparing means and confirming the priority; An OR operation means for receiving the first to eighth comparison signals output from the first comparison means and performing an OR operation; Latch means for outputting an output signal outputted by the logical OR operation means as an address mark detection signal (AMFOUND); Multiplexer means for selecting and outputting 8-bit data whose synchronization is coincident by the priority determination means; And a fourth register for outputting synchronized NRZ byte data output from the second multiplexer means as byte data.

Alternatively, when the 8-bit input line NRZ data is synchronized with 8-bit NRZ data, a second comparing means may be provided to detect a synchronizing signal immediately without delay.

Alternatively, when the 8-bit input line NRZ data is synchronized with 8-bit NRZ data, one of 8-bit data BYTE2 (7: 0) to be input in synchronization with 8-bit data output from the multiplexer means is selected And second multiplexer means for outputting the output signal.

FIG. 3 shows a synchronization signal detecting apparatus for NRZ data used in the present invention.

The synchronizing signal detecting apparatus of the present invention comprises a data converting means (200) for outputting 8 bit input line NRZ data input in synchronism with a predetermined clock signal as 16 bits of parallel data, a 16 A first comparator 210 for comparing the corresponding 8 bits of the bit data with a predetermined address mark, a comparator 210 for comparing the first to eighth comparison signals DT1 to DT8 output from the first comparator 210, A second comparing means (220) for immediately detecting an address mark when the input NRZ data is synchronized with 8-bit data to be inputted, and a second comparison means (280) for receiving the first to eighth comparison signals (DT1 to DT8) output from the first comparison means (210) and the ninth comparison signal (DT0) output from the second comparison means (220) And outputs the output signal of the OR gate arithmetic means 280 in synchronism with the predetermined clock signal A latch means 270 for outputting an address mark detection signal AMFOUND and first multiplexer means 240 for selecting and outputting 8-bit data whose priority is determined by the priority judging means 230, Second multiplexer means 250 for selecting and outputting one of 8-bit data BYTE2 (7: 0) to be inputted synchronously with 8-bit data outputted from the first multiplexer means 240 from the beginning, And a fourth register 260 for outputting the synchronized byte data output from the second multiplexer means 250.

The data conversion means 200 comprises two shift registers 201 and 202 operating at the same predetermined clock to extend the input data of a predetermined bit to 16 bits. The first comparator 210 compares 8-bit data shifted by one bit from the consecutive 2-byte input data to eight comparators (first to eighth comparison signals DT1 to DT8) 211 to 218).

FIG. 4 shows an embodiment of a circuit consisting of eight comparators within the first comparison means 210 of FIG. FIG. 5 shows an embodiment of the error permitting comparators 211 to 218 and 221 used in the first comparing means 210 and the second comparing means 220 in FIG. FIG. 6 shows an embodiment of the priority determination means 230 in FIG.

Hereinafter, the operation of the present invention will be described in detail with reference to FIGS. 3 to 8.

In the preferred embodiment, the predetermined number of bits of NRZ input data is 8 bits. First, the NRZ data NRZ8 (7: 0) of the 8-bit input line is input to the data conversion means 200. [

The data conversion means 200 increases the inputted 8-bit NRZ data NRZ8 (7: 0) to 16 bits in order to find the start position of the synchronization signal in response to a predetermined clock BYTECK.

This is performed by the first and second registers in the data conversion means 200 and converted into 16-bit data (D0 to D15) composed of previously input 8-bit data and currently inputted 8-bit data, .

The first comparing means 210 includes first to eighth comparators 211 to 218. The first comparator 211 is for checking the synchronizing signal. The first comparator 211 compares the most significant bits of the 16-bit data rearranged in the order of input by the data conversion means 200 in descending order, The first byte data BD1 (7: 0) having one byte is compared with the address mark and outputs the first comparison signal DT1 if they are the same.

In general, the address mark uses the hexadecimal value "A5H (10100101B for binary data)" for NRZ data of 8 input bits. The second comparator 212 outputs the second comparison signal DT2 by comparing the address data with the second byte data BD2 (7: 0) having the 15th to 8th bits of the aligned 16-bit data as one byte .

Likewise, the remaining third to eighth comparators 213 to 218 compare the third to the eighth byte data BD3 (7: 0) to BD8 (7), which are shifted downward by one bit from the aligned 16-bit data, : 0) and the address mark and outputs the third to eighth comparison signals DT3 to DT8. When comparing the NRZ data input to the first to eighth comparators 211 to 218 with the sync signal pattern which is an address mark, the error allow enable bit FAULTENI in the first to eighth comparators 211 to 218 must match all the bits , And determines whether to operate as an error permissive comparator that is regarded as synchronous even if an error occurs up to 3 bits or less as a result of comparison between the NRZ data input to the first to eighth comparators 211 to 218 and the address mark Signal.

In the preferred embodiment of the present invention, the error allow enable bit for the first to eighth comparators is set to " 0 " as a normal case in which all bits must match.

Thereafter, the priority determination means 230 receives the first to eighth comparison signals DT1 to DT8 output from the first comparison means 210 to make the synchronization signal that is first captured to be valid.

For example, when the first comparison signal DT1 and the second comparison signal DT2 all indicate that the synchronization signal is caught, the priority determination means 230 determines that the first comparison signal DT1 has a high priority, Is detected.

Therefore, all the sync signals generated after the first comparison signal DT1 are ignored. That is, since the first comparison signal DT1 has the highest priority and the second comparison signal DT8 has the lowest priority in the priority determining means 230, the priority is synchronized from the bit input earlier in time.

Power On Reset (PORB) in FIG. 3 is to initialize all related logic when the power is first applied. It is a signal which is first made logic "low" once and then becomes logic "high" after a certain time.

When the power supply initialization signal PORB is applied for the first time, the DTO (7: 0), DIRSB, AMFOUND, and BYTED (7: 0) signals in the circuit of FIG. 3 are cleared.

In a particular embodiment, if the NRZ data input is a signal that has been pre-synchronized in 8-bit lengths, i.e., in units of bytes, a separate second comparison means 220 is used to reduce the delay of the comparison operation time performed by the first comparison means .

The second comparison unit 220 includes a ninth comparator 221. When the ninth comparator 221 receives the synchronized NRZ data, the ninth comparator 221 compares the NRZ data with the address mark data and determines whether or not the synchronous signal is detected immediately. The output signal DIRSB of the second comparing means 220 is used as a control signal of the second multiplexer means 250 described later.

When the first comparison means 210 and the second comparison means 220 receive the synchronization signal, the first multiplexer means determines the priority of the synchronization signal by the priority determination means 230, And outputs the rearranged data of the position. The signal outputted from the priority judging means 230 is used as a control signal to select the 8 bits of BD1 to BD8, which are the outputs of the data converting means 200, Selects the data and outputs the rearranged data to the second multiplexer means.

The second multiplexer means is for immediately outputting the NRZ input when the synchronized signal is input to the NRZ input as described above, and the output signal DIRSB of the second comparing means 220 is used for outputting the 8 bits of the first multiplexer means Bit output BYTED (7: 0) of the first shift register 201 directly to the 8-bit output BYTED (7: 0) synchronously held through the fourth register 260. [

In the preferred embodiment, NRZ8 (7: 0) NRZ data of an 8-bit input line is input to the data conversion means 200 in the order of 0AH, 50H, 10H and 20H.

Then, the NRZ8 (7: 0) is first converted into 8-bit BYTE2 (7: 0) data by the first shift register 201 operating in correspondence with a predetermined clock BYTECK, Is again connected to the input of the second shift register 202 in correspondence with the same clock BYTECK to make byte data BYTE1 (7: 0) one clock later than the byte data BYTE2 (7: 0).

Then, in order to find the synchronization signal, two bytes of byte data BYTE2 (7: 0) and byte data BYTE1 (7: 0) are increased to 16 bits from bit 7 of BYTE1 to bit 0 of BYTE2 in the order of input, Bit data that is input into the 16-bit data.

Referring to the comparators shown in FIG. 3 and FIG. 5, the first comparison means compares byte data in which the upper eight bits of the 16-bit data, that is, the 16th to the 9th bits, And then outputs the first comparison signal DT1. Next, byte data including eight bits, that is, one bit from the 15th to the eighth bit, which is one bit shifted in descending order, is compared with a predetermined reference address mark, and then the second comparison signal DT2 And sequentially shifts the bits one bit at a time in the same manner to check at which position the synchronization signal is input.

The result of the comparison of the 8-bit data and the address mark input in this manner is the first to eighth comparison signals DT1 to DT8 which are the outputs of the first comparison means 210. These comparison signals are input to the OR circuit 280 It is determined whether or not an address mark is detected.

The output signal of the OR circuit 280 is connected to the latch means 270. If the address mark is detected by the comparing means, the first flip-flop 271 in the latch means 270, in synchronization with the predetermined clock BYTECK, And latches the output signal of the OR circuit 280 to produce a signal AMF1.

The output signal AMF1 of the first flip-flop 271 is input as a clock signal to the third flip-flop 222 in the second comparing means 220 to control the output of the DIRSB signal indicating that the address mark of the 8- do.

The signal AMF1, once activated high, is cleared when signal AMSEN goes low. The signal AMF1 activated to " High " is input to the second flip-flop 272 to make the output signal AMFOUND high. At this time, the signal AMFOUND is cleared when the input signal RG of the AND gate 274 becomes " low ".

Another output signal CON1 of the first flip-flop 272 corresponding to the output signal of the OR circuit 280 is input as a control signal to the third register 231 and is supplied to the 8-bit The signal DTI (7: 0) is connected to the input of the first multiplexer means 240 as an 8-bit signal DTO (7: 0).

When the CON1 signal, which is one of the output signals of the first flip-flop 272, is activated at "low", the byte data DTO (7: 0) having the start position information of the synchronous data output from the priority determination means 230 is Bit data of the 8-bit data BD1 to BD8 whose synchronization is identical among the 8-bit data BD1 to BD8 is selected by the decoding result of the priority judging means 230, 1 < / RTI > multiplexer means 240, as shown in FIG. At this time, if the output signal DIRSB of the second comparison means 220 is active, that is, if the NRZ data string of the 8-bit input line already has synchronous data, the second multiplexer means 250 outputs the input NRZ data Sends BYTE2 (7: 0) to the immediate output.

In contrast, if the DIRSB signal is not active, that is, if unsynchronized data is input, the second multiplexer means 250 selects the first multiplexer means 240 As the output S02 of the second multiplexer means 250. [

Then, the fourth register 260 receives the output S02 of the second multiplexer means 250 and outputs the synchronized byte output BYTED (7: 0) corresponding to the predetermined clock signal BYTECK. In this preferred embodiment, the NRZ data input signal NRZ8 (7: 0), the byte clock BYTECK, the output signal S01 of the first multiplexer means 240, the output signal S02 of the second multiplexer means 250, The timing with respect to the output data BYTED (7: 0) and the reference address mark detection signal AMFOUND is as shown in the input signal timing of FIG. 7 and the output signal timing diagram of FIG.

In the above-described embodiment, the DTO (7: 0) holds 08H because the sync signal is detected in the fifth comparator and DT5 is generated.

As described above, in the above preferred embodiment, NRZ data input is limited to 8-bit byte data. However, Korean Patent Application No. 95-2835, " Address Mark Detection Device of Dual Bit- The present invention can also be applied to a 2-bit input line as well as existing 1-bit and 4-bit input line data.

That is, in the above case, a known circuit for converting NRZ data of 1-bit input line or 4-bit input line into 8-bit input line is added to the front end of the data conversion means 200 of the present invention, It is possible to use the device. At this time, the predetermined clock BYTECK should be set to the bit input line of the corresponding NRZ data.

Those skilled in the art will also appreciate that the present invention can be applied to NRZ data input such as a 16-bit input line to a 32-bit input line by further extending the synchronous signal detecting apparatus of the present invention.

As described above, the synchronous signal detecting apparatus of the multi-bit input NRZ interface enables a synchronous signal to be detected sufficiently fast in response to a request for high-speed data transmission in a hard disk drive.

In addition, when the data synchronized with 8 bits is the input of the NRZ data, a separate comparison means is provided, so that a faster performance can be ensured.

Further, by using the error tolerant comparator, even if an error of 3 bits or less occurs, the synchronous signal can be detected, thereby improving the function of the synchronous signal detecting device.

Further, by adding a known additional circuit, there is an advantage that the detection apparatus of the present invention can be used as it is for existing 1-bit input lines to 4-bit input lines.

Claims (3)

An address mark pattern detecting apparatus of a disk drive recording apparatus having predetermined reference address mark data of a hard disk drive, comprising: Data conversion means for outputting 8-bit input line NRZ data as 16-bit parallel data; The comparator includes eight fault tolerant comparators, that is, first to eighth comparators, and compares predetermined eight bits of the parallel data with the predetermined reference address mark, First comparison means for comparing the eighth comparison signal; Priority determining means for receiving the first to eighth comparison signals output from the first comparing means and confirming the priority; An OR operation means for receiving the first to eighth comparison signals output from the first comparison means and performing an OR operation; Latch means for outputting an output signal outputted by the logical OR operation means as an address mark detection signal (AMFOUND); Multiplexer means for selecting and outputting 8-bit data whose synchronization is coincident by the priority determination means; And And a fourth register for outputting the synchronized NRZ byte data output from the second multiplexer means as byte data. The method according to claim 1, Bit NRZ data is synchronized with the 8-bit NRZ data, and a second comparing means for detecting a synchronous signal immediately without time delay when the 8-bit input line NRZ data is synchronous 8-bit NRZ data. Mark detection device. 3. The method of claim 2, Bit data BYTE2 (7: 0) inputted in synchronization with the 8-bit data output from the multiplexer means when the 8-bit input line NRZ data is synchronous 8-bit NRZ data, Further comprising a second multiplexer means for multiplexing the first and second multiplexed NRZ signals.