KR19980016556A - Computer On / Off Control - Google Patents

Abstract

The present invention relates to an on / off control apparatus for a computer that is capable of controlling an on / off of a corresponding computer by using a telephone at a remote location, the apparatus comprising: first power supply means for generating an operating power required for operation of the device from an input power source; Second power means for generating standby power for standby operation of the device from input power, operation detection means for outputting a computer operation signal according to a user's manual operation, and a ring for detecting a ring signal input from a trunk line in combination with a trunk line Signal detecting means, power control signal output means for operating said first power means in accordance with said ring detection signal and computer operation signal, state storage means for storing output states of said ring detection signal and computer operation signal, from outside Signal input detecting means for detecting a signal input of a predetermined time unit and storing an input state thereof; On the basis of the data stored in the device, if the ON state of the computer is detected by the ring signal, and if no signal input is detected by the signal input detecting means for a predetermined time, the power control signal output means is controlled. And control means for off-controlling the computer.

Description

Computer On / Off Control

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a personal computer used in a home or office, and more particularly, to an on / off control apparatus for a computer that enables a remote computer to be controlled on / off using a telephone.

In recent years, with the rapid development of computer technology, even for personal computers used in homes and offices, a terminal for data communication between a computer and a computer or another facsimile device without going beyond a simple word processor function or data processing function. As its function is gradually diversified.

In the conventional personal computer, however, the device can be used as a communication terminal only when the power of the device is turned on and the computer remains in an operating state. Therefore, if a user uses his computer, the data is transferred to a computer at another location. If you want to send a call to the user of the computer to be inconvenient to require to set the computer to the operating state.

That is, Fig. 1 is a main structural view showing a conventional computer on / off control apparatus.

In the drawing, reference numeral 1 denotes a power plug, and 2 denotes a standby for generating standby power (Vs: 5V) required in a standby mode of the computer based on the input power from the power plug 1. The power supply section 3 operates according to a control signal applied from the RTC 4 to be described later, and generates SMPS (Switching) for generating various operating voltages V1 to V4 based on the input power supply from the power plug 1. Mode Power Supply). 4 is a real time clock (RTC), which means that the output of the AND gate AND1 is a kick start signal input terminal ( ), As well as the output stage ( ) Is coupled to the SMPS 3 described above via a pull-up resistor R2.

In addition, the RTC (4) is a kick start signal input stage ( When a low level signal is applied through the Output low level signal, and if the SMPS (3) is normally driven by this low level signal and normal voltage of + 5V is applied from the SMPS (3), separate power-off operation, that is, system data bus By the data applied through Output stage () until ) Continuously outputs the low-level power control signal.

In addition, the reference numeral SW1 in the drawing is installed on the outside of the computer main body on / off switch for the user to mechanically turn on / off the computer, this switch (SW1) is one end is grounded and the other end pull-up ( It is coupled to one input of the AND gate AND1 via a pull up resistor R1. The other input terminal of the AND gate AND1 is coupled to an infrared receiver (not shown).

Here, the infrared receiver is a general that allows the user to control the on / off the computer device using a remote controller (Remote Controller), which is when a user inputs an infrared signal to turn on the computer for a predetermined time For example, a low level signal is output.

That is, when the user turns on the remote control device or the switch SW1 to turn on the computer, the AND gate AND1 outputs a low level power-on signal for a predetermined time.

That is, in the on / off control device for a computer configured as described above, when a user generates a low level power on signal using a mechanical switch (SW1) or a remote control device, the RTC 4 connected thereto is connected to an SMPS (3). The SMPS 3 is driven by outputting a low level signal, and when the normal voltage of +5 V is applied from the SMPS 3, the output stage is operated by a separate power-off operation, that is, data applied through the system data bus. ( Output stage () until ) Continuously outputs the low-level power control signal.

Therefore, in the above-described conventional computer, since the on / off operation is entirely dependent on the user's manual operation, there is a disadvantage in using the computer as a communication terminal as described above.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is to provide an on / off control apparatus for a computer that enables a computer to be turned on or off remotely using a telephone.

1 is a main configuration diagram showing a conventional on / off control device for a computer.

Figure 2 is a block diagram showing an on / off control device for a computer according to an embodiment of the present invention.

3 is a configuration diagram showing the configuration of the state storage unit in FIG.

Figure 4 is a block diagram showing a schematic configuration of a personal computer to which the present invention is applied.

Fig. 5 is a timing chart for explaining the operation of the apparatus shown in Fig. 2;

*** Brief description of the main parts of the drawing ***

1: power plug, 2: standby power unit,

3: SMPS, 4: RTC,

5: photocoupler, 9: inverter,

10: state storage unit, 61: 3 state buffer,

62, 101, 102, 103: D flip-flop, 107: buffer (74LS245).

An on / off control apparatus for a computer according to the present invention for realizing the above object comprises a first power supply means for generating an operating power source for operation of the device from an input power source, and a standby power source for standby operation of the device from an input power source. Second power supply means, operation detection means for outputting a computer operation signal according to a user's manual operation, ring signal detection means for detecting a ring signal input from a trunk line in combination with a trunk line, and the ring detection signal and computer operation signal Power control signal output means for operating said first power means, state storage means for storing output states of said ring detection signal and computer operation signal, and detecting signal input from an external unit by a predetermined detection time unit A signal input detecting means for storing an input state and a ring signal based on data stored in said state storing means And control means for controlling the power supply control signal output means to off-control the computer when the on state of the computer is detected and if no signal input is detected for a predetermined time by the signal input detection means. do.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention.

Figure 2 is a block diagram showing a computer on / off control device according to an embodiment of the present invention, the same reference numerals for the components performing the same function as the configuration shown in Figure 1 and the detailed description thereof will be omitted. Let's do it.

In FIG. 2, reference numeral 5 is a photocoupler coupled to a tip (TIP) end and a ring (RING) end of a trunk line to detect a ring signal applied through the trunk line. The photocoupler 5 has a photodiode PD having its anode and cathode coupled to a trunk line, and an electrical signal according to an optical signal inputted on / off in accordance with an optical signal emitted from the photodiode PD. It is comprised including the phototransistor PT output.

That is, as shown in Fig. 5A, when a ring signal having a frequency of 20 Hz is input through a trunk line, the photodiode PD flashes according to the frequency signal, and the phototransistor PT is connected to the photodiode PT. The on / off is switched according to the optical signal applied from PD. At this time, since the photo transistor PT does not respond quickly to the flashing period of the photodiode PD, the photo transistor PT is kept on.

Therefore, when the ring signal is input through the trunk line, the photocoupler 5 is set to the on state so that the low level ring detection signal is output as shown in FIG. .

The output of the photocoupler 5 is coupled to one input terminal of the AND gate AND2 through the pull-up resistor R3 and the three-state buffers 8 and 61 which will be described later. The other input terminal is coupled to the output terminal of the AND gate AND1. Therefore, in the AND gate AND2, the user turns on the computer by using a mechanical switch SW1 or a remote control device or from an external source. When a call is received and a ring signal is input, a low level signal is output.

At this time, as shown in Figs. 5C to 5E, once the low level signal is output to the AND gate AND2, the RTC 4 stops the system data bus until there is a separate off operation. Output terminal by data input through The SMPS 3 is driven by continuously outputting a low-level power supply control signal until) is reset to the high level.

In FIG. 2, reference numeral 6 is a selection unit for selectively executing the on / off function of the computer via the telephone. The selector 6 has a tri-state buffer 61 coupled between the photocoupler 5 and the signal line of the AND gate AND2, and a D input coupled to one bit of the system data bus, and the PAL 7 to be described later. One output terminal P1 of the < RTI ID = 0.0 > 1 < / RTI > includes a D flip-flop 62 coupled to the clock input terminal CLK, and the inverted output of this D flip-flop 63 ) Is coupled to the gate end of the tri-state buffer 61.

Also, reference numeral 7 denotes a PAL (Programmable Array Logic 7) which is coupled to the system address bus and outputs a predetermined logic signal according to the address data, which has one output terminal P1 provided at the selector 6. It is coupled to the clock input terminal CLK of the flip-flop 62, and the other output terminal P2 is coupled to the state storage unit 10 to be described later. When the output terminal P1 is selected by the system address bus, the PAL 7 rises from the low level to the high level. When the other output terminal P2 is selected, the corresponding output signal P2 becomes high. It is programmed to descend from level to low level.

When the clock input of the D flip-flop 62 becomes high level, the system data bus coupled to the D input terminal of the D flip flop 62 is set to a high level or a low level. This will run at computer boot, depending on the user's operating state.

On the other hand, when the high level signal is output from the D flip-flop 62 by the above operation, the tri-state buffer 61 is disabled and the output of the photocoupler 5 is applied to the AND gate AND2. When the low level signal is output from the D flip-flop 62, the tri-state buffer 61 is enabled, so that the output of the photocoupler 5 is applied to the AND gate AND2.

In FIG. 2, reference numeral 7 is coupled to an output terminal of the photocoupler 5 so as to intercept that the output of the photocoupler 5 is applied to the AND gate AND2 through the tri-state buffer 61. Is a status buffer, and 8 denotes a power supply control signal output from the above-described RTC 4 Inverter is inputted to the gate terminal of the tri-state buffer 8, and these tri-state buffer 8 and inverter 9 are outputted once the low-level power supply control signal from the RTC 4 The ring detection signal output from the photocoupler 5 is prevented from being applied to the RTC 4 through the AND gate AND2.

In FIG. 2, reference numeral 10 denotes a predetermined power-on signal applied to the system by a mechanical switch SW1, a remote control device, or a ring detection signal, and then stored as predetermined state data. When the output signal of the P2 falls to the low level is a state storage unit for outputting it through the system data bus (SD1 ~ SD3).

FIG. 3 is a block diagram showing the configuration of the state storage unit 10. The clock input terminal CLK is coupled to the output of the switch SW1 and the infrared receiver and the output of the photocoupler 5, respectively. Three D flip-flops (101, 102, 103) whose output power (Vs) is coupled to the D input terminal, and an output enable signal ( And a buffer 107 for coupling the outputs Q1 to Q3 of the D flip-flops 101, 102 and 103 to the system data buses SD1 to SD3, respectively. In addition, the D flip-flops 101, 102, and 103 have a clear stage CLK through the inverters 104, 105, and 106, respectively. Coupled to the output terminal of the RTC (4) ) Is cleared when the computer is turned off, that is, when the computer is turned off, and the buffer 107 outputs the output enable signal (P2) of the above-described PAL (7). When the output signal P2 becomes low level, the output Q1 to Q3 of the D flip-flops 101, 102, and 103 are output to the system data buses SD1 to SD3.

4 is a block diagram schematically illustrating the system configuration of a personal computer to which the present invention is applied. In FIG. 4, the same parts as in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 4, reference numeral 20 denotes a central processor unit (CPU), 21 denotes a main memory for storing various data or programs related to the operation of a computer, and 22 denotes the main memory based on address data applied from the CPU 20. As memory controllers that control the access operation to the memory 21, they are coupled to each other via a CPU bus, that is, a CPU data bus and a CPU address bus.

In FIG. 4, reference numeral 23 denotes a buffer for data transmission and reception between the CPU bus and the Peripheral Component Interconnection Bus (PCI).

Also, reference numeral 24 denotes a PCI slot, to which peripheral devices, such as hard disk drives, which operate at high speed, are combined.

In the drawing, reference numeral 25 denotes a BIOS in which the above-described control program of the CPU 20 is stored, 26 denotes a keyboard controller which executes control of a keyboard or a mouse, and 27 denotes a modem, a floppy disk drive, and a printer. Industry Standard Architecture (ISA) slots that combine peripherals operating at low speeds, which are interconnected via a system bus, a system data bus and a system address bus.

In the drawing, reference numeral 28 denotes a PCI / ISA bridge that controls data transmission and reception between the PCI bus and the system bus, and particularly indicates a data input state from the ISA slot 27 or the keyboard controller 26 therein. If there is no data input for a predetermined detection time by providing a register to be issued, a flag indicating no data is set in the corresponding register. In addition, the detection time is set by the CPU 20. The CPU 20 performs PCI / ISA based on the CMOS data in the RTC 4 at the time of system booting by the program of the BIOS 25. The time setting for the bridge 28 is performed.

In addition, the detection time may be set by the user in a CMOS setup.

Next, the operation of the device having the above configuration will be described.

When the user inserts the power plug 1 into an outlet (not shown), the standby power unit 2 is operated by the input power applied from the power plug 1, excluding the SMPS 3 in FIG. The other circuit part is operated.

Subsequently, when the user operates the mechanical switch SW1 or the remote control device installed in the main body to turn on the computer, the low-level power-on signal is supplied to the RTC 4 through the AND gates AND1 and AND2. Kickstart signal input at ), And accordingly the output of RTC 4 Is set to the low level so that the SMPS 3 is activated. Therefore, in this case, the computer enters into an operating state while executing a cold boot operation.

In the meantime, the booting operation is executed based on the program stored in the BIOS 25. That is, the CPU 20 first executes a system check function for checking an abnormal state of each circuit section, and then reads the CMOS in the RTC 4 to initialize the system, in particular, the selection section 6 and FIG. The control process for the PCI / ISA bridge 28 is executed.

That is, when the power-on function via the telephone line is selected in the CMOS in the RTC 4, the CPU 20 sends address data to the PAL 7 via the system address bus and selects the output terminal P1. The three-state buffer 61 is enabled by raising the signal applied to the clock input terminal CLK of the flip-flop 62 from the low level to the high level and setting its D input to the high level through the system data bus. When the power-on function using the telephone line is not selected, the three states are set by setting the D input of the D flip-flop 62 to the low level through the system data bus at the rising edge of the clock signal CLK. The buffer 61 is set to the disabled state.

The CPU 20 sets the signal input detection time set in the CMOS in the RTC 4 in the PCI / ISA bridge 28.

On the other hand, when the computer is brought into an operating state by the above operation, the PCI / ISA bridge 28 described above is executed by the ISA slot 27 or the keyboard controller during the signal input detection time set by the CPU 20 at the time of booting. 26), it is detected whether data is input from the outside, and if there is no data input for the corresponding time, a flag is set in a predetermined flag register therein.

When the flag is set in the register in the PCI / ISA bridge 28 as described above, the CPU 20 outputs the address data to the PAL 7 via the system address bus to lower the output signal P2. By setting the level, the state data of the state storage unit 10 is read out, and when the on state of the computer is determined to be caused by the ring signal, the computer is turned off.

That is, in the state storage unit 10 as described above, when the computer is turned on by the operation of the mechanical switch SW1 or the remote control device or by the ring signal, the D flip-flops 101, 102, and 103 shown in FIG. The outputs of the corresponding D flip-flops Q1 to Q3 are set to a high level, and the state data accordingly enables the output signal P2 of the PAL 7 to the low level so that the output is enabled in the buffer 107. signal( ) Is applied and outputted through the system data buses SD1 to SD3.

Then, the CPU 20 determines the on state of the computer based on the state data read out from the state storage unit 10, so that if the present on state is not by the mechanical switch SW1 or the remote control device, If it is determined that the ring signal is determined, the use of the computer is determined to be terminated, and predetermined data is sent to the RTC 4 via a system data bus (Fig. 5 (E)) to output the RTC 4 ( ) To the high level.

In this case, therefore, the operation of the SMPS 3 is brought to a stop state, whereby the computer is set to the off state.

In this way, the output of the RTC 4 ( Is raised to a high level, the D flip-flops 101, 102, and 103 of the state storage unit 10 are cleared to return to the initial state.

In the above embodiment, any user can externally drive the computer through a telephone from outside, and when the computer is set to be inactive for a predetermined time after being turned on by the telephone in this manner, the user is automatically turned off.

Therefore, transmission and reception of data through a computer can be facilitated even without a user.

In addition, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the technical scope of the present invention.

As described above, according to the present invention, it is possible to realize an on / off control apparatus for a computer that can drive control a computer at a remote location by using a telephone.

Claims (3)

First power means for generating an operating power source for operation of the apparatus from an input power source; Second power supply means for generating standby power for standby operation of the apparatus from input power, Operation detection means for outputting a computer operation signal according to a user's manual operation; Ring signal detection means for detecting a ring signal input from the trunk line in combination with the trunk line; Power supply control signal output means for operating said first power supply means in accordance with said ring detection signal and computer operation signal; State storage means for storing an output state of the ring detection signal and the computer operation signal; On-state state of the computer by the ring signal is detected on the basis of the signal input detecting means for detecting the signal input from the outside by a predetermined detection time unit and storing the input state, and the data stored in the state storing means. And a control means for controlling the computer by controlling the power supply control signal output means when the signal input detection means detects no signal input for a predetermined period of time. . The method of claim 1, The off-control of the computer by the control means is characterized in that the operating state of the computer is selected by the CMOS setup. The method of claim 1, And a signal input detecting time unit of the signal input detecting means is set by CMOS setup.